Top Failing Paths report for AID_AIDA_FEB Thu Dec 19 13:49:00 2019 Quartus II 64-Bit Version 14.0.0 Build 200 06/17/2014 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Setup: REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk 3. Setup: C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2014 Altera Corporation. All rights reserved. Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, the Altera Quartus II License Agreement, the Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Setup: REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; +--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+--------------+------------+------------+ ; -0.152 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_FIFO:\C_FIFO_HIT:90:C_FIFO_HITX|dcfifo:dcfifo_component|dcfifo_ohv1:auto_generated|wrptr_g[2]~DUPLICATE ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0h_wr[90] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.066 ; 2.536 ; ; -0.136 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_FIFO:\C_FIFO_HIT:90:C_FIFO_HITX|dcfifo:dcfifo_component|dcfifo_ohv1:auto_generated|wrptr_g[0] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0h_wr[90] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.068 ; 2.518 ; ; -0.089 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_FIFO:\C_FIFO_HIT:90:C_FIFO_HITX|dcfifo:dcfifo_component|dcfifo_ohv1:auto_generated|alt_synch_pipe_pc8:ws_dgrp|dffpipe_ld9:dffpipe13|dffe15a[2] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0h_wr[90] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.063 ; 2.476 ; ; -0.076 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_FIFO:\C_FIFO_HIT:90:C_FIFO_HITX|dcfifo:dcfifo_component|dcfifo_ohv1:auto_generated|wrptr_g[3] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0h_wr[90] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.064 ; 2.462 ; ; -0.072 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_FIFO:\C_FIFO_HIT:90:C_FIFO_HITX|dcfifo:dcfifo_component|dcfifo_ohv1:auto_generated|alt_synch_pipe_pc8:ws_dgrp|dffpipe_ld9:dffpipe13|dffe15a[0] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0h_wr[90] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.060 ; 2.462 ; ; -0.033 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_triggered[49][1] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0h_error[49] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.095 ; 2.388 ; ; -0.025 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TRIG_DELAY:\C_TRIG_DELAY_SR:52:C_TRIG_DELAY_SRX|lpm_shiftreg:LPM_SHIFTREG_component|dffs[30] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay_1st_mux[52][3] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.102 ; 2.373 ; +--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+--------------+------------+------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Setup: C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; +--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------+------------+------------+ ; -0.102 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_FIFO:\C_FIFO_HIT:90:C_FIFO_HITX|dcfifo:dcfifo_component|dcfifo_ohv1:auto_generated|wrptr_g[2]~DUPLICATE ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0h_wr[90] ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.066 ; 2.536 ; ; -0.086 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_FIFO:\C_FIFO_HIT:90:C_FIFO_HITX|dcfifo:dcfifo_component|dcfifo_ohv1:auto_generated|wrptr_g[0] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0h_wr[90] ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.068 ; 2.518 ; ; -0.039 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_FIFO:\C_FIFO_HIT:90:C_FIFO_HITX|dcfifo:dcfifo_component|dcfifo_ohv1:auto_generated|alt_synch_pipe_pc8:ws_dgrp|dffpipe_ld9:dffpipe13|dffe15a[2] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0h_wr[90] ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.063 ; 2.476 ; ; -0.026 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_FIFO:\C_FIFO_HIT:90:C_FIFO_HITX|dcfifo:dcfifo_component|dcfifo_ohv1:auto_generated|wrptr_g[3] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0h_wr[90] ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.064 ; 2.462 ; ; -0.022 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_FIFO:\C_FIFO_HIT:90:C_FIFO_HITX|dcfifo:dcfifo_component|dcfifo_ohv1:auto_generated|alt_synch_pipe_pc8:ws_dgrp|dffpipe_ld9:dffpipe13|dffe15a[0] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0h_wr[90] ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.060 ; 2.462 ; +--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------+------------+------------+