Setup: C_PLL100M|aid_pll3_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk report for AID_AIDA_FEB Fri Mar 31 14:20:10 2017 Quartus II 64-Bit Version 14.0.0 Build 200 06/17/2014 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Setup: C_PLL100M|aid_pll3_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2014 Altera Corporation. All rights reserved. Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, the Altera Quartus II License Agreement, the Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Setup: C_PLL100M|aid_pll3_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk ; +--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+ ; -0.025 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1]~SynDup ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[87] ; C_PLL100M|aid_pll3_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk ; C_PLL100M|aid_pll3_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk ; 2.500 ; -0.085 ; 2.390 ; ; -0.017 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1]~DUPLICATE ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[37] ; C_PLL100M|aid_pll3_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk ; C_PLL100M|aid_pll3_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk ; 2.500 ; -0.135 ; 2.332 ; ; -0.004 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1]~SynDup ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[86] ; C_PLL100M|aid_pll3_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk ; C_PLL100M|aid_pll3_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk ; 2.500 ; -0.073 ; 2.381 ; ; -0.003 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay[0][42] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|U_EdgePulse:\C_EDGE_PULSE:42:C_EDGE_PULSEX|sl_int_state.FALLING ; C_PLL100M|aid_pll3_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk ; C_PLL100M|aid_pll3_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk ; 2.500 ; -0.075 ; 2.378 ; +--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+