Top Failing Paths report for AID_AIDA_FEB Tue May 16 11:44:10 2017 Quartus II 64-Bit Version 14.0.0 Build 200 06/17/2014 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Setup: REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk 3. Setup: C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2014 Altera Corporation. All rights reserved. Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, the Altera Quartus II License Agreement, the Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Setup: REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; +--------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+--------------+------------+------------+ ; -0.068 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[36] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.128 ; 2.390 ; ; -0.064 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1]~SynDup ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[74] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.060 ; 2.454 ; ; -0.060 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1]~SynDup ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[73] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.066 ; 2.444 ; ; -0.058 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1]~SynDup ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[83] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.122 ; 2.386 ; ; -0.044 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[44] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.135 ; 2.359 ; ; -0.033 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[39] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.134 ; 2.349 ; ; -0.023 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1]~SynDup_Duplicate_5 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[76] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.052 ; 2.421 ; ; -0.013 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay_2nd_mux_in[45][4] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay[0][45] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.109 ; 2.354 ; ; -0.004 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1]~SynDup ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[54] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.119 ; 2.335 ; +--------+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+--------------+------------+------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Setup: C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; +--------+-------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------+------------+------------+ ; -0.018 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[36] ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.128 ; 2.390 ; ; -0.014 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1]~SynDup ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[74] ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.060 ; 2.454 ; ; -0.010 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1]~SynDup ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[73] ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.066 ; 2.444 ; ; -0.008 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1]~SynDup ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[83] ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.122 ; 2.386 ; +--------+-------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------+------------+------------+