Top Failing Paths report for AID_AIDA_FEB Thu Jun 08 14:42:32 2017 Quartus II 64-Bit Version 14.0.0 Build 200 06/17/2014 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Setup: x_ucPCLK 3. Setup: REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk 4. Setup: C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2014 Altera Corporation. All rights reserved. Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, the Altera Quartus II License Agreement, the Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Setup: x_ucPCLK ; +--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+ ; -0.368 ; UFP_WRAPPER_USB_UART_CHAIN:C_WRAPPER_USB_CHAIN|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_start_state.STARTED ; x_ucSLCSn ; C_SYNC_WRAPPER|C_PLL100M|aid_pll3_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; x_ucPCLK ; 5.000 ; 3.991 ; 7.119 ; +--------+-----------------------------------------------------------------------------------------------------------------------------------+-----------+-----------------------------------------------------------------------------------------------+-------------+--------------+------------+------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Setup: REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; +--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+--------------+------------+------------+ ; -0.106 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay_2nd_mux_in[47][5] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay[0][47] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.125 ; 2.431 ; ; -0.070 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0h_error[15] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_fifo_error_1st_stage[0][1] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.124 ; 2.396 ; ; -0.066 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay_2nd_mux_in[46][5] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay[0][46] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.106 ; 2.410 ; ; -0.044 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[41] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.112 ; 2.382 ; ; -0.041 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TRIG_DELAY:\C_TRIG_DELAY_SR:6:C_TRIG_DELAY_SRX|lpm_shiftreg:LPM_SHIFTREG_component|dffs[0] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay_1st_mux[6][0] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.148 ; 2.343 ; ; -0.040 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_FIFO:\C_FIFO_HIT:50:C_FIFO_HITX|dcfifo:dcfifo_component|dcfifo_ohv1:auto_generated|alt_synch_pipe_pc8:ws_dgrp|dffpipe_ld9:dffpipe13|dffe15a[0] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0h_error[50] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.084 ; 2.406 ; ; -0.038 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay[1][7] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|U_EdgePulse:\C_EDGE_PULSE:7:C_EDGE_PULSEX|sl_int_state.WAIT_FALLING ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.093 ; 2.395 ; ; -0.037 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0h_error[12] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_fifo_error_1st_stage[0][1] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.067 ; 2.420 ; ; -0.034 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[43] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.101 ; 2.383 ; ; -0.034 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay_2nd_mux_in[46][4] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay[0][46] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.106 ; 2.378 ; ; -0.033 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[42] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.106 ; 2.377 ; ; -0.033 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[3] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.094 ; 2.389 ; ; -0.018 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay_2nd_mux_in[47][4] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay[0][47] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.127 ; 2.341 ; ; -0.014 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay[1][7] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|U_EdgePulse:\C_EDGE_PULSE:7:C_EDGE_PULSEX|sl_int_state.RISING ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.093 ; 2.371 ; ; -0.009 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[22] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.114 ; 2.345 ; ; -0.006 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay_2nd_mux_in[55][4] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay[0][55] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.064 ; 2.392 ; ; -0.003 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|sl_int_fifo_L0_error_clr400[1] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0_fifo_error_clr[11] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.085 ; 2.368 ; ; -0.002 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0h_error[78] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_fifo_error_1st_stage[2][1] ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; REF2_C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.080 ; 2.372 ; +--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+--------------+------------+------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Setup: C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; +--------+----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------+------------+------------+ ; -0.056 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay_2nd_mux_in[47][5] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay[0][47] ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.125 ; 2.431 ; ; -0.020 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|AID_L0_TrigCounters:C_TC|sl_int_L0h_error[15] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_fifo_error_1st_stage[0][1] ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.124 ; 2.396 ; ; -0.016 ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay_2nd_mux_in[46][5] ; AID_L1_TC_WRAPPER:C_L1_TC_WRAPPER|AID_L0_TC_WRAPPER:C_TC_WRAPPER|sl_int_trig_delay[0][46] ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; C_SYNC_WRAPPER|C_SYNC_CLK_PLL|aid_pll_sync_clk_inst|altera_pll_i|arriav_pll|counter[1].output_counter|divclk ; 2.500 ; -0.106 ; 2.410 ; +--------+----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------+------------+------------+