v7.1-v535: MUST BE USED with FX3 >= v3.0 and HOST version >= 1.0.1.848, MCB FW-v5 New features visible for user: Solved bugs: - Hold time is now pushed only on spill_gate if 'ReadoutEnOnSpillGate' is ON known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay is required Deep features not visible from user: ------------------------------------------------------------- v7.0-v533: MUST BE USED with FX3 >= v3.0 and HOST version >= 1.0.1.848, MCB FW-v5 New features visible for user: - Add External Trigger Output + parameters to enable NOR32/NOR32_t/SUM - Add External Trigger Input+ parameters to enable Global_PS_trigger/ADC start - Add ASIC Global Peak Sensing Trigger input drive from NOR32/NOR32_t/Ext Trig.IN - Add OR32 Disable to disable ADC start from 3xOR32 - Add NOR32/NOR32_t/Ext Trig.In and associated Enable to start ADC - ADD HW version for v2.1 and 2.2 - HOLD START/STOP TIME to DAQ (with Enable bit) - Allow reset of PS cells during HOLD mask (with Enable bit) Solved bugs: - Change MCB emulation bits latch (removed from sc_config bit) in order to avoid synchronisation issue when FEB in MCB drives several FEBs & MCRs ... - Fix bug when reseting trigger time, now on spill header B known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked Deep features not visible from user: - Added AID_L3_COM_WRAPPER for AID_GTX_FIFO_WRAPPER, AID_L3_TDM_WRAPPER and UFP_WRAPPER_USB_UART_CHAIN wrapping - Added AID_L3_SLOWCONTROL_WRAPPER for AID_L2_ASICSLOWCONTROL, AID_L2_ASICPROBECONTROL, AID_L2_FpgaSlowControl,AID_L2_HVONSLOWCONTROL, UFP_USER_SETGET_ACK and AID_L2_DPRAM wrapping - Prepared DAC_CSn output (no DAC control yet) ------------------------------------------------------------- v6.6-v512: MUST BE USED with FX3 >= v3.0 and HOST version >= 1.0.1.811, MCB FW-v5 New features visible for user: - Add External Trigger Input and output to DEBUG connector - Add Nor32t or Nor32 or External Trigger Input to be enabled and routed to ASIC Global Peak Sensing Trigger input. Delay max from FPGA pin to pin is < 11ns - Add Nor32t or Nor32 to be enabled and routed to external Trigger output.Delay max from FPGA pin to pin is < 11ns - Add OR32 Disable to disable ADC start - Add External Trigger Input to enable ADC start Solved bugs: known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked Deep features not visible from user: ------------------------------------------------------------- v6.5-v438: MUST BE USED with FX3 >= v3.0 and HOST version >= 1.0.1.691, MCB FW-v5 New features visible for user: Solved bugs: - Increase FIFO L1 depth from 8 elements to 84 (Missing Falling Edge when high number of event within 1 GTRIG) known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked Deep features not visible from user: ------------------------------------------------------------- v6.4-v357: MUST BE USED with FX3 >= v3.0 and HOST version >= 1.0.1.691, MCB FW-v5 New features visible for user: - Added SyncRdEn Stop request delay in order to allow FEBs in the chain to let their own data to be dequeued on Slot 0 USB connected FEB. Only work in TDM mode. Solved bugs: - Fix bug with wrong TAG-ID in GTRIG continuous mode - Fix SpillTimeFromGtrig issue (i.e. value not in the [0-1000] range) known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked Deep features not visible from user: ------------------------------------------------------------- v6.3-v351: MUST BE USED with FX3 >= v3.0 and HOST version >= 1.0.1.685, MCB FW-v5 New features visible for user: - Added L3_SM option to start readout with 1st_edge chosen Solved bugs: - Fix bug for SPILL_HEADERB sent before anything else after readout start known issues: - try to fix the bug where TAG-ID of HIT event was not synchronized with GTRIG TAG IN GTRIG CONTINUOUS MODE (NON CONT. mode is OK) seems not working with beam trigger in B2 floor but seems OK with ext. GEN on 200ms/20ms spill gate - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked - FBW mode : rare GTRIG/SPILL coherence errors detected (misses some data) when HOST suspends USB com. due to processor overactivity (GTRIG & SPILL enable mode => to check with STOP FLOW) => seems to be linked with USB issue overwriting a chunk of data = PacketSize * NbOfPackets Deep features not visible from user: ------------------------------------------------------------- v6.3-v350: MUST BE USED with FX3 >= v3.0 and HOST version >= 1.0.1.685, MCB FW-v5 New features visible for user: - Added L3_SM option to start readout with 1st_edge chosen Solved bugs: - Fix bug for SPILL_HEADERB sent before anything else after readout start known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked - FBW mode : rare GTRIG/SPILL coherence errors detected (misses some data) when HOST suspends USB com. due to processor overactivity (GTRIG & SPILL enable mode => to check with STOP FLOW) => seems to be linked with USB issue overwriting a chunk of data = PacketSize * NbOfPackets Deep features not visible from user: ------------------------------------------------------------- v6.2-v349 : MUST BE USED with FX3 >= v3.0 and HOST version >= 1.0.1.681, MCB FW-v5 New features visible for user: - Continuous GTRIG TAG increment option - DAQ type from MCB pushed to DAQ - Error counters for PLL Locked, SYNC Parity/EOF, GTRIG lost, FSYNC lost - Reset Error counter in setDirectParams - Hold MASK from Spill gate Solved bugs: - TDM to FBW mode needs 2 startDAQ to be OK (1st DAQ = KO immediately, 2nd DAQ = 2-4 TDM errors, 3rd DAQ and next OK) known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked - FBW mode : rare GTRIG/SPILL coherence errors detected (misses some data) when HOST suspends USB com. due to processor overactivity (GTRIG & SPILL enable mode => to check with STOP FLOW) Deep features not visible from user: - SYNC encoder/decoder v2 compatible with MCB FW-v5 - New simplified L3_SM with direct spill gate header/trailer pushed to DAQ ------------------------------------------------------------- v6.1-LIB5-v308 : MUST BE USED with FX3 v3.0 and HOST version >= 1.0.1.592 New features visible for user: - No new features, simply an upgrade of the protocol library to V5. FPGA top design version remains 6.1, fully compatible with presvious v6.1-r306 Solved bugs: - TDM to FBW mode needs 2 startDAQ to be OK (1st DAQ = KO immediately, 2nd DAQ = 2-4 TDM errors, 3rd DAQ and next OK) known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked - FBW mode : rare GTRIG/SPILL coherence errors detected (misses some data) when HOST suspends USB com. due to processor overactivity (GTRIG & SPILL enable mode => to check with STOP FLOW) Deep features not visible from user: - LIB V5 with user get cmd data latched on ACK rather than 1 clk later. ------------------------------------------------------------- v6.1-r306 : MUST BE USED with FX3 v3.0 and HOST version >= 1.0.1.592 New features visible for user: - Housekeeping: - Data available on DPRAM and mapped on user get request - Data pushed on readout (enabled with FPGA HKB enable bits config in FPGA slow control bits) Solved bugs: - TDM to FBW mode needs 2 startDAQ to be OK (1st DAQ = KO immediately, 2nd DAQ = 2-4 TDM errors, 3rd DAQ and next OK) known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked - FBW mode : rare GTRIG/SPILL coherence errors detected (misses some data) when HOST suspends USB com. due to processor overactivity (GTRIG & SPILL enable mode => to check with STOP FLOW) Deep features not visible from user: ------------------------------------------------------------- v6.0-r301 : MUST BE USED with FX3 v3.0 and HOST version >= 1.0.1.592 New features visible for user: - LED synchronization improvement for a full MCR - Get Board ID for automatic get Board ID when the host detects a new board connected Solved bugs: - TDM to FBW mode needs 2 startDAQ to be OK (1st DAQ = KO immediately, 2nd DAQ = 2-4 TDM errors, 3rd DAQ and next OK) known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked - FBW mode : rare GTRIG/SPILL coherence errors detected (misses some data) when HOST suspends USB com. due to processor overactivity (GTRIG & SPILL enable mode => to check with STOP FLOW) Deep features not visible from user: - DMA buffer compatible with FX3 new firmware v3.0 (larger data throughput) ------------------------------------------------------------- v5.6-r273 : MUST BE USED with HOST version 1.0.0.547 New features visible for user: - Add SPILL/GTRIG GRESET & FIFO FULL WORDS on readout protocol Solved bugs: - Fixes TDM & GTRIG/SPILL issues - improves robustness for TDM mode known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked - TDM to FBW mode needs 2 startDAQ to be OK (1st DAQ = KO immediately, 2nd DAQ = 2-4 TDM errors, 3rd DAQ and next OK) - FBW mode : rare GTRIG/SPILL coherence errors detected (misses some data) when HOST suspends USB com. due to processor overactivity (GTRIG & SPILL enable mode => to check with STOP FLOW) Deep features not visible from user: - FIFO L2 = 8192 (2x greater than previous versions) : improves readout buffering when HOST suspends USB communication - Hysteresis on USB stop flow ------------------------------------------------------------- v5.5-r270 : New features visible for user: Solved bugs: - FIXED on HOST side with v1.0.0.485 : switching from FBW to TDM since the TDM fifo of the USB device is filled during FBW and will be unfilled during the next TDM DAQ session - L2_TDM_SM : TDM Checksum bug fixed known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked Deep features not visible from user: ------------------------------------------------------------- v5.4-r269 : New features visible for user: - L2_TDM_SM : TDM & FBW mode START/STOP fixed bug and improves TDM decoded slots (PKEND missing) Solved bugs: - a bug remains from switching from FBW to TDM since the TDM fifo of the USB device is filled during FBW and will be unfilled during the next TDM DAQ session known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked Deep features not visible from user: - Reduce TDM fifo depth from 16 to 8 words ------------------------------------------------------------- v5.3-r268 : New features visible for user: - new led blinking for Readout SM - spill gate inverted possibilities for MCB input Solved bugs: - TDM was missing some GTRIG & data due to USB reading latency : solved by adding usb flux control for the chain known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked - FPGA v5.3 does not closed properly the thread in Full Bandwidth mode so switching from FBW to TDM mode will fill an empty file the 1st time Deep features not visible from user: - TDM settings with ACTIVE = 1400 CLK, MUX_END = 1500 CLK, advance = 30 CLK - changed size for USB FIFO TX depth = 128 words ------------------------------------------------------------- v5.2-r266 : New features visible for user: - Gigabit+chain+TDM mode - new L3 readout state machine (see doc) - SYNCIN-RDEN=0 can now also control the Stop request for the readout state machine Solved bugs: known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked Deep features not visible from user: ------------------------------------------------------------- v5.1-r264 : New features visible for user: - SYNC+MCB Solved bugs: - GRESET propagation for spill & gtrig TAG/TIME counters reset known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked Deep features not visible from user: ------------------------------------------------------------- v5.0-r263 : New features visible for user: - SYNC+MCB Solved bugs: known issues: - External GRESET to reset GTRIG/GSPILL is not latched by slave sometimes - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked Deep features not visible from user: ------------------------------------------------------------- FEB-V2/prel-v259.0-r246: New features visible for user: - Preliminary version for FEB-V2 ONLY Solved bugs: known issues: - A0/A1/A2 CH31 missing resolution (FPGA firmware issue) Deep features not visible from user: ------------------------------------------------------------- !!! ALL BELOW VERSIONS ARE COMPATIBLE ONLY WITH FEB-V1 ---!!! !!! DON'T INSTALL THEM ON FEB-V2 -------------------------!!! ------------------------------------------------------------- v3.0-Lib2-r200 : New features visible for user: Solved bugs: known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling - NEVER APPLY config for FPGA & ASIC at the same time (either 0x8, either 0x7 but never 0xF) - Launch start Readout just after the config apply (apply/read status/startReadout from Yordan test) answer a timeout on USB readout EP => 70ms delay has been put by yordan ??? To be reproduced and checked Deep features not visible from user: - New library LIB2 protocol working with FX3 UART and CRC ------------------------------------------------------------- v3.0 : New features visible for user: Solved bugs: known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling Deep features not visible from user: - New library LIB1 protocol working with FX3 UART ------------------------------------------------------------- v2.5 : New features visible for user: - Separated HG/LG per ASIC Solved bugs: known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling Deep features not visible from user: ------------------------------------------------------------- v2.4 : New features visible for user: Solved bugs: - double Timing Falling Edge event on readout when Time Diff is short (typically < 3-4 ticks) known issues: - If Time Diff pulse is below 10ns, ADC is not launched. Occurs in OR32 or OR32t mode for ADC start => Timing Event are seen in readout but no Amplitude Event even with ADC not running from current sampling Deep features not visible from user: ------------------------------------------------------------- V2.3 : New features visible for user: Solved bugs: - multiple Timing events sent to readout due to FIFO error management in L0 => lead to GTRIG header/trailer missing, no Amplitude Events & FIFO errors known issues: - double Timing Falling Edge event on readout when Time Diff is short (typically < 3-4 ticks) Deep features not visible from user: -------------------------------------------------------------