------------------------------------------------------------------------------------ -------------- FPS FASER PRE-SHOWER Firmware --------------------------------------- ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ v1.5 date 05/02/2025 / SVN 1765 GUI config-desc v1765b 12/02/2025: - Status parameters: add PLL Unlocked counter - Fix wrong index to pass sanity check (no issue on parameters/registers/var. layout New features visible for user: - TOP_FASER.vhd : add PLL Unlocked counter Solved bugs: - FPS_RO_TWO_LATCH_CONSEC: Fix bug on DAT pulse = APP_TRAILER pulse, missing DAT_after_trailer pulse to switch L1_fifo_select into L2_WRITER known issues/bugs: - BUG #10: L1A counter sporadic reset (noise on TLB clock ?) - BUG #9: Duplicate event (occurs if chip EOF before DAT, normally should never happended but can be secured if chip emits very small packet) - OPTIMIZE: Ethernet stack optimization on UDP checksum - OPTIMIZE: S/C commands optimization (too slow, wait for calibration specs - next item) - OPTIMIZE: Update/Optimize Calibration (L1A from APP + Chip mode Test Pulse + #cycles + flow & reset management/all chips), wait for Theo's spec. - OPTIMIZE: Update L1A & TLB BUSY & CHIP RESET : ideally send an error if L1A arrives and APP BUSY, or do not inc. L1A if BUSY, Claire’s mail Deep features not visible from user: - Updated tst_L0_L1_L2_WRAPPER to simulate full DAQ around DAT pulse (see "Investigation on DAT and AW.docx") - Updated tst_E_CHIP_DRV for L0-FIFO IP and fix warning on FIFO usedw output ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ v1.4 date 04/02/2025 / SVN 1763 GUI config-desc v1763 04/02/2025: see ..\GUI\GUIv1_3tov1_4.pdf for details - Direct parameters: rename PLL_Auto_Set to PLL_Scan , add PLL_Apply - Status Parameters: remove BoardId - Rename TEST_OUT tab to 'ModuleConfig' and move 'RO_PARAM' into 'General' tab - add Internal Periodic generator in 'RO_PARAM' - Add 'Phase' tab for Get and Set phases used with PLL_Scan and PLL_Apply - Add FW & HW Versions list - Scripts: - add ..\GUI\ scripting for scan phase (need to clean up all config registers and find only required ones) - update ..\GUI\faser-sc-module-config_2.cs for new GUI (renaming + new variables) New features visible for user: - TOP_FASER.vhd : latch board_id, set correct fw_version, product_id an hw_version and above GUI new/renamed/deleted paramaters - E_FPS_AUTO_L1A: Update with internal generator - Add Set and Get Phases Solved bugs: - BUG #8_2: FW stuck when using slow data throughput (radioactive source) : E_FPS_RO_WINDOW: Increase decoder latency to 32 for DAT (fix FW stuck and let data from L0 to L1 pass through, NB:min=20) - BUG #11: Add IP L0_FIFO with registers implementation (no M10K nor MLAB) and use it in E_Chip_drv rather than custom E_L0_FIFO (bug on afull signal asynchronous latch) - BUG #3: Get Board ID returns wrong ROT SWI ID (while BOARD_ID=ROT SWI on protocol com is OK) : removed in status param (unused). known issues/bugs: - BUG #10: L1A counter sporadic reset (noise on TLB clock ?) - BUG #9: Duplicate event (occurs if chip EOF before DAT, normally should never happended but can be secured if chip emits very small packet) - OPTIMIZE: Ethernet stack optimization on UDP checksum - OPTIMIZE: S/C commands optimization (too slow, wait for calibration specs - next item) - OPTIMIZE: Update/Optimize Calibration (L1A from APP + Chip mode Test Pulse + #cycles + flow & reset management/all chips), wait for Theo's spec. - OPTIMIZE: Update L1A & TLB BUSY & CHIP RESET : ideally send an error if L1A arrives and APP BUSY, or do not inc. L1A if BUSY, Claire’s mail Deep features not visible from user: - FPS_SC_FEEDER: Optimize 1 CLK tick on DPRAM address load - E_PLL_PHASE: cleanup some states to optimize condiitions, add a generic port for delay used to stabilize error from chip, same default value than before - E_FPS_AUTO_L1A: cleanup some states to optimize conditions - FASER.QPF : fix warning - FASER_out.sdc : add SYNC set_false_path on s_clk_50_ro + PHASE signals - E_PLL_Phase.vhd : update with x_ph_apply/x_ph_scan inputs and S/C x_phase_out/x_phase_in - Add global simulation L0_L1_L2_WRAPPER.vhd + tst_L0_L1_L2_WRAPPER (use to simulate FIFO-ERR & duplicate event bugs) - FIFO_L1: Use underflow/overflow checking - TOP_FASER.vhd + sdc : Use constants for direct params & general params + renaming + clean some timing warning ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ v1.3 date 23/12/2024 / SVN 1744 GUI config-desc v1752 20/01/2025: - UserSetBlockTransfer = true (optimize S/C transfer) New features visible for user: - Increase L2-FIFO memory to 32KB Solved bugs: - BUG #8: FW stuck when using slow data throughput (radioactive source) : FPS_RO_L2_WRITER : anticipate x_fifo_select on TIMEOUT & TRANSFER_DATA transitions to APP_TRAILER known issues/bugs: - BUG #3 Get Board ID returns wrong ROT SWI ID (while BOARD_ID=ROT SWI on protocol com is OK), still active ? - Ethernet stack optimization on UDP checksum - S/C commands optimization (too slow, wait for calibration specs - next item) - Update/Optimize Calibration (L1A from APP + Chip mode Test Pulse + #cycles + flow & reset management/all chips), wait for Theo's spec. - Update L1A & TLB BUSY & CHIP RESET : ideally send an error if L1A arrives and APP BUSY, or do not inc. L1A if BUSY, Claire’s mail - Get and Apply values of auto detected phases through S/C Deep features not visible from user: - E_merger_L0_L1: - add comments and I/F description + TB updated OK - E_module: - add comments + TB updated OK - FPS_RO_L2_MERGER.vhd: changed signals names, comments and I/F description + TB updated OK - FPS_RO_L2_WRITER.vhd: - add state for TIMEOUT_WAIT, latch acq_ID for x_fifo_select on transition to APP_TRAILER to anticipate MUX RD latency - changed signals names, comments and I/F description + TB updated OK - FPS_RO_L2_WRITER_MUX.vhd: - simplify copied and shifted module_id selection by a loop, add L2 fifo_full protection on L1 RDREQ - changed signals names, comments and I/F description + TB updated OK - FPS_RO_TWO_LATCH_CONSEC.vhd: - add TRAILER_BEFORE_DAT state and fix a missing dat_after_trailer pulse in this state - changed signals names, comments and I/F description + TB updated OK - E_FPS_RO_WINDOW.vhd: - changed signals names, comments and I/F description (port update: x_deser_event_ID becomes x_acq_ID) + TB updated OK ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ v1.2 date 09/12/2024 / SVN 1729 GUI config-desc v1545 9/10/2024 New features visible for user: - Auto_L1A : chips reset synchronization => permits to synchronize the chips - DAQ Chip data with '1' + 7-b chip timing data Solved bugs: - known issues/bugs: - Ethernet stack optimization on UDP checksum - S/C commands optimization (too slow) - Calibration optimization Deep features not visible from user: - enhance signal integrity on Ethernet PHY RGMII TX signals (remove FPGA in-series 25R resistances) - E_FPS_RO_WINDOW : synchroniozed on Readout 50Mhz clock (BCID and L1A counter directly latched and selected according to L1 FIFO selection) - FPS_RO_L2_MERGER : Updated and simplified according to new E_FPS_RO_WINDOW.vhd - E_FPS_AUTO_L1A : Separated process with chip reset management added - Increase FPS_DATA_FIFO size (L2-FIFO) to 16k words (16192 x 33b) - Includes new SC files : - Reduce DPRAM size to handle only 1 super column = 256*16-b = 4096 pixels - Includes new E_chip_dvr (reset management updated) ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ v1.1 (24/11/2024) GUI config-desc v1545 9/10/2024 -- Bug Fixed : corrupted word when L2 is Full v1.1b (26/11/2024) -- SDC file cleanup (timing constraint file) v1.1c (26/11/2024) file : FASER_v1.1c_SVN1696.pof -- E_chip_drv.vhd file (removed useless FIFO data output mux) ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ v1.0 (19/11/2024) GUI config-desc v1545 9/10/2024 file : FASER_v1.0_SVN1667.pof -- 6 modules ; 36 chips -- Independant phase adjustments with 36 internal clocks Remark -- correction : Readout doesn’t seem to be getting stuck