------------------------------------------------------------- v12.1-1494 Ethernet (0x12.1 ETH = v18.1 ETH) Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: - NIOS µC code version 4.2 with Management of DHCP relay agents and RENEWAL more properly: - DHCP REQUEST: - now with DHCP server IP (was missing) - add ARP request if server is in same sub-network - DHCP RENEWAL: - use MAC addr from ARP and IP addr of server rather than broadcast - reduced number of options (no 50 and 54) from REQUEST type Solved bugs: known issues/bugs: Deep features not visible from user: Script examples : ------------------------------------------------------------- v12.0-1446 Ethernet (0x12.0 ETH = v18.0 ETH) Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: - MAC address load from EEPROM if Jumper on J1.3-J1.5 (3A.TXN2 to GND), can be used if the mac addr. sticker is on the board see https://partphys.unige.ch/~favrey/FASER/TRB/FW/Jumper%20MAC-ADDR-EEPROM-v18.0-1446-ETH.jpg - MAC address load from ROT SWITCH (as before) if no Jumper on J1.3-J1.5 - Ethernet LIB 263 (compatible GPIO V1B & V1C) (NIOS µC code version 3.2) Solved bugs: known issues/bugs: Deep features not visible from user: Script examples : ------------------------------------------------------------- v11.F-687 Ethernet (0x11.F ETH, or v17.15 ETH) Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: - Gateway and DHCP enabled version - I2C EEPROM for retrieving SN (not stored, all at FF), and optionnal fixed MAC, IP, Gateway and Subnetmask addresses (not used) Solved bugs: known issues/bugs: Deep features not visible from user: Script examples : ------------------------------------------------------------- v11.E-643 Ethernet & v1.E-643 USB (0x11.E ETH/0x1.E USB = v17.14 ETH/v1.14 USB) Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: Solved bugs: - #006 : Hardware Delay, Tested - Hanging when switching to TLB Clock (Synchronizer added on PLL locked in clock swithing state machine) known issues/bugs: Deep features not visible from user: Script examples : ------------------------------------------------------------- v11.D-641 USB / intermediate version (USB only) Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: Solved bugs: - #007 : CLK0/1 Fine Phase shift value> 31 (180°) and TLB HW signals latch, not tested yet - Hanging during calibration loop (added 2 CLK on L2SM-loopReady and 30CLK delay on LoopReady to Reset state in PCSM) known issues/bugs: - #006 : Hardware Delay, not tested yet - Hanging when switching to TLB Clock Deep features not visible from user: Script examples : ------------------------------------------------------------- v11.C-639 Ethernet & v1.C-639 USB Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: - Added L1A loop with same parameters than Cal Pulse - Added Dynamic Delay increased when L2-FIFO is full or L1-FIFOs are not empty - increase LoopNb to 20-bits - Change size of UserSet 2 (Config) to 4b ADDR, 12b data, 10 words - Change FIFO not full restart level to 53248 wrt 65535. Previously set to 32768 Solved bugs: known issues/bugs: - #006 : Hardware Delay, not tested yet - #007 : CLK0/1 Fine Phase shift value> 31 (180°) and TLB HW signals latch, not tested yet - Hanging when switching to TLB Clock Deep features not visible from user: - Changed CalLoop to Loop for L1A and Cal Pulse Script examples : ------------------------------------------------------------- v11.B-633 Ethernet & v1.B-633 USB Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: - Added softL1A loop with same parameters than Cal Pulse Loop - Added Dynamic Delay increased when L2-FIFO is full or L1-FIFOs are not empty - increase LoopNb to 20-bits - Change size of UserSet 2 (Config) to 4b ADDR, 12b data, 10 words - Change FIFO not full restart level to 53248 wrt 65535. Previously set to 32768 Solved bugs: - #008 : Hanging when TRB is connected board while sending PC commands to SCT commands like SoftReset known issues/bugs: - #006 : Hardware Delay, not tested yet - #007 : CLK0/1 Fine Phase shift value> 31 (180°) and TLB HW signals latch, not tested yet - Hanging when switching to TLB Clock Deep features not visible from user: - Changed CalLoop to Loop for softL1A and Cal Pulse Script examples : ------------------------------------------------------------- v11.B-633 Ethernet & v1.B-633 USB Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: Solved bugs: - #008 : Hanging when TRB is connected board while sending PC commands to SCT commands like SoftReset known issues/bugs: - #006 : Hardware Delay, not tested yet - #007 : CLK0/1 Fine Phase shift value> 31 (180°) and TLB HW signals latch, not tested yet Deep features not visible from user: - Timeout management when missing frame in RX multiframe protocol mode or missing ACk from applicative FW Script examples : ------------------------------------------------------------- v2.2-629 Ethernet & v1.10-629 USB Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: - DAQ data : checksum in trailer - Error counter for PLL unlocked Solved bugs: - BCID latched when L1A occurs (not when L1A sent like in previous versions) - SCT BCID now mapped with TRB BCID: TRB: 7, 8, 9, 10, 11 - 3561 SCT: 3, 4, 5, 6, 7 - 3557 (%256) known issues/bugs: - #006 : Hardware Delay, not tested yet - #007 : CLK0/1 Fine Phase shift value> 31 (180°) and TLB HW signals latch, not tested yet - #008 : Hanging when TRB is connected board while sending PC commands to SCT commands like SoftReset Deep features not visible from user: Script examples : ------------------------------------------------------------- v2.1-615 Ethernet & v1.9-615 USB Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: Solved bugs: - Double L1A+BCID words in DAQ data when soft L1A trigger is requested (essentially seen in ETH version) known issues/bugs: - #006 : Hardware Delay, not tested yet - #007 : CLK0/1 Fine Phase shift value> 31 (180°) and TLB HW signals latch, not tested yet - #008 : Hanging when TRB is connected board while sending PC commands to SCT commands like SoftReset Deep features not visible from user: Script examples : ------------------------------------------------------------- v2.0-v603 Ethernet + L2 FIFO 64K (from V1.8 USB) Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: - Ethernet from v1.8 USB Solved bugs: known issues/bugs: - #006 : Hardware Delay, not tested yet - #007 : CLK0/1 Fine Phase shift value> 31 (180°) and TLB HW signals latch, not tested yet - #008 : Hanging when TRB is connected board while sending PC commands to SCT commands like SoftReset Deep features not visible from user: Script examples : ------------------------------------------------------------- v1.8-v591 L2 FIFO 64K Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: - L2 FIFO = 64K words Solved bugs: known issues/bugs: - #006 : Hardware Delay, not tested yet - #007 : CLK0/1 Fine Phase shift value> 31 (180°) and TLB HW signals latch, not tested yet Deep features not visible from user: Script examples : ------------------------------------------------------------- v1.7-590/-589/-xxx RX Overflow bug fixed + L2 FIFO size increased Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: - L2 FIFO = 32K words for v1.7-590 (official release) - L2 FIFO = 16K words for v1.7-589 (beta version) - L2 FIFO = 8K words for v1.7-xxx (alpha version, same size for v1.6 and below) Solved bugs: - Fix bug for RX overflow : now RX overflow value means 4x bits (1024 value set = 4096 bits overflow error on RX) known issues/bugs: - #006 : Hardware Delay, not tested yet - #007 : CLK0/1 Fine Phase shift value> 31 (180°) and TLB HW signals latch, not tested yet Deep features not visible from user: Script examples : ------------------------------------------------------------- v1.6-v584 Cal Loop command bug fixed Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: Solved bugs: - Fix bug for calibration loop when NbLoop>500 and delay>1000 known issues/bugs: - #006 : Hardware Delay, not tested yet - #007 : CLK0/1 Fine Phase shift value> 31 (180°) and TLB HW signals latch, not tested yet Deep features not visible from user: Script examples : - ThresholdScanL1ALoopAsic_ALL for L1A Calibration Loop mode example within a Threshold Scan ------------------------------------------------------------- v1.5-v557 L1A Loop command Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: - Added L1A loop with Cal. LoopNb, LoopDelay, LoopEn, LoopAbort and LoopProcessing Solved bugs: - Fix bug for HW L1A and BCR sent to all modules even if L1AEn/BCREn is not checked known issues/bugs: - #006 : Hardware Delay, not tested yet - #007 : CLK0/1 Fine Phase shift value> 31 (180°) and TLB HW signals latch, not tested yet Deep features not visible from user: Script examples : - ThresholdScanL1ALoopAsic_ALL for L1A Calibration Loop mode example within a Threshold Scan ------------------------------------------------------------- v1.4-v524: L1-FIFO depth = 2048 words Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: - L1-FIFO depth = 2048 words (older versions with 1024 words) in order to remove L1-FIFO full when high occupency on modules (low thresholds scan) Solved bugs: known issues/bugs: - #006 : Hardware Delay, not tested yet - #007 : CLK0/1 Fine Phase shift value> 31 (180°) and TLB HW signals latch, not tested yet Deep features not visible from user: Script examples : ------------------------------------------------------------- v1.3-v522: 1st version compatible with spec. v0.9, full SCT module communication and TLB connection Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: - Compliant with spec. v0-9 (see parameters & DAQ protocol) - Compliant with TLB signals, HW L1A and BCR propagated to SCT modules - Added L1CounterReset, ErrCntReset and FifoReset on DataReadoutParameters (synchronized with START DAQ) Solved bugs: - #001 : TLB input (BCR & L1A signals) not tested yet known issues/bugs: - #006 : Hardware Delay, not tested yet - #007 : CLK0/1 Fine Phase shift value> 31 (180°) and TLB HW signals latch, not tested yet Deep features not visible from user: Script examples : - Added TLBDataTaking example ------------------------------------------------------------- v1.2-v520: 1st version for SCT module communication Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6, or DPNC420_02A (new version) - GPIO board DPNC397_01A or higher (02A) New features visible for user: - Compliant with spec. v0-9 (see parameters & DAQ protocol) - Added Soft Reset + delayed L1A command - Allows TRB header an trailer when sending software and delayed L1A from Calibration & software reset - Internal to TLB clock switch tested - Added LED/LEDX Safe Phase Detection bit for RX CLK0 & CLK1 domains (when changing cable length or SCT TX CLK) - Added separated Timeout for RXDataModuleManager and L2SM for allowing L1A Trigger + Header - Timeout check between L1 consecutive data read in L2-SM up to SCT module trailer received. Solved bugs: - #002 : TLB clock selection (switch from internal clock to TLB clock) - #003 : Fine Phase shift tested - #004 : 1st DAQ data get after SCT module hard reset will put several FRB errors : Fix with Reset FIFO, no wrong data from module when LED/LEDX switching to CLK/2 mode to normal mode, i.e. on first DAQ run after SCT power up - #005 : DAQ trailer, OK with soft reset when L1Timeout is Enabled and RXTimeout is Disabled known issues/bugs: - #001 : TLB input (BCR & L1A signals) not tested yet - #006 : Hardware Delay not tested yet Deep features not visible from user: Script examples : - Update for Reset Fifos before any DAQ => no wrong data from module when LED/LEDX switching to CLK/2 mode to normal mode - Update for L1A Header & Trailer mode - Add Safe Phase scan ------------------------------------------------------------- v1.1-v505: 1st version for SCT module communication Hardware needed : - TRB adapter DPNC420_01A with wires fix for MODULE#4 & MODULE#6 - GPIO board PNC397_01A New features visible for user: - led0: BUSY, led1: None, led2: FIFO_L2 write, led3: TLB BCRIN - Compliant with spec. v0-8 (see parameters & DAQ protocol) - Tested with configuration read back on 2x6 ASICs chain, read on LED&LEDX lines - Tested for all 8 modules connector - Threshold scan still not tested (probably config. file not correct but fw should be ok) Solved bugs: known issues/bugs: #001- TLB input (Clock, BCR & L1A signals) not operationnal yet #002- TLB clock selection (switch from internal clock to TLB clock) not working yet #003- Fine Phase shift and Hardware Delay not tested yet #004- 1st DAQ data get after SCT module hard reset will put several FRB errors (resynchronization issue, easy to solve in a future release), workaround : bin these values #005- DAQ trailer not working yet (linked with TLB signals and will be fixed when #001 will be operationnal) Deep features not visible from user: ------------------------------------------------------------- ------------------------------------------------------------- v1.0-v494: Base version for test protocol New features visible for user: - LED D1 = Config/SoftCounters/BCID (bit-0) - LED D2 = Config/Global_Control/L1AEn - LED D3 = Board/DirectParameters/SoftCounterMuxEn - LED D4 = SlowControl/SCT_Slow_Command/Field3 (bit-7) Solved bugs: known issues: Deep features not visible from user: -------------------------------------------------------------