Analysis & Synthesis report for FTR_TOP
Mon Nov 30 09:47:21 2020
Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis IP Cores Summary
 10. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|state
 11. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX|sl_int_state
 12. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX|sl_int_state
 13. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX|sl_int_state
 14. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX|sl_int_state
 15. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED|sl_int_state
 16. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED|sl_int_state
 17. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED|sl_int_state
 18. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED|sl_int_state
 19. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|sl_int_detect_state[1]
 20. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|sl_int_detect_state[0]
 21. State Machine - |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|sl_int_state
 22. State Machine - |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE|sl_int_state
 23. State Machine - |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state
 24. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX|sl_int_state
 25. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX|sl_int_state
 26. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX|sl_int_state
 27. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX|sl_int_state
 28. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED|sl_int_state
 29. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED|sl_int_state
 30. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED|sl_int_state
 31. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED|sl_int_state
 32. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_state
 33. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_mux
 34. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_state
 35. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_chk_state
 36. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|sl_int_state[1]
 37. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|sl_int_state[0]
 38. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_L1A_state
 39. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_timeout_state
 40. State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET|sl_int_state
 41. State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET|sl_int_state
 42. State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET|sl_int_state
 43. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_state
 44. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_timeout_state
 45. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|sl_int_state_ack
 46. State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_state
 47. State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_state
 48. State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_state
 49. State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_state
 50. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_state
 51. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_process_state
 52. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_timeout_state
 53. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|state
 54. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_read_cntl:U_LBR|state
 55. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_wrt_cntl:U_LBW|state
 56. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_state
 57. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_state
 58. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|state
 59. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFO_CHECK:C_DAQ_FIFO_CHECK|sl_int_state
 60. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFO_CHECK:C_SC_FIFO_CHECK|sl_int_state
 61. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|a_fefifo:fifo_state|sm_emptyfull
 62. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DISPATCHER:C_MSGDMA_DISPATCHER|sl_int_state_rq
 63. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DISPATCHER:C_MSGDMA_DISPATCHER|sl_int_state_irq
 64. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_state
 65. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_state
 66. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_CSR_SM:C_MSGDMA_CSR_SM|sl_int_state
 67. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_cntl:U_CNTL|state
 68. State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|DRsize
 69. Registers Protected by Synthesis
 70. Registers Removed During Synthesis
 71. Removed Registers Triggering Further Register Optimizations
 72. General Register Statistics
 73. Inverted Register Statistics
 74. Registers Packed Into Inferred Megafunctions
 75. Multiplexer Restructuring Statistics (Restructuring Performed)
 76. Source assignments for Top-level Entity: |FTR_TOP
 77. Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER
 78. Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i
 79. Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0
 80. Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1
 81. Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2
 82. Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3
 83. Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4
 84. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER
 85. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo
 86. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated
 87. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|a_graycounter_pv6:rdptr_g1p
 88. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|a_graycounter_ldc:wrptr_g1p
 89. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|altsyncram_m8d1:fifo_ram
 90. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|dffpipe_3dc:rdaclr
 91. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp
 92. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14
 93. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|dffpipe_3dc:wraclr
 94. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|dffpipe_qe9:ws_brp
 95. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|dffpipe_qe9:ws_bwp
 96. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp
 97. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18
 98. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|altera_std_synchronizer:rdreq_sync_i
 99. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram|altsyncram:the_altsyncram|altsyncram_g572:auto_generated
100. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_tx_dpram:enet_nios_tx_dpram|altsyncram:the_altsyncram|altsyncram_g572:auto_generated
101. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated
102. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated
103. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated|a_dpfifo_b071:dpfifo|altsyncram_rgn1:FIFOram
104. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo|scfifo_p871:auto_generated|a_dpfifo_c071:dpfifo|altsyncram_tgn1:FIFOram
105. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated
106. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated
107. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo|altsyncram_3hn1:FIFOram
108. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram|altsyncram:the_altsyncram|altsyncram_dc72:auto_generated
109. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_demux:cmd_demux
110. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux
111. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_001
112. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_002
113. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_003
114. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_004
115. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_005
116. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_006
117. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_007
118. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_008
119. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_009
120. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_010
121. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_011
122. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_012
123. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_013
124. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_014
125. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1
126. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1
127. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|altsyncram_7pu1:FIFOram
128. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|altsyncram_7pu1:FIFOram
129. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_msi1:auto_generated
130. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_b_module:nios2_nios2_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_msi1:auto_generated
131. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_debug:the_nios2_nios2_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer
132. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_qid1:auto_generated
133. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|altera_std_synchronizer:the_altera_std_synchronizer1
134. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|altera_std_synchronizer:the_altera_std_synchronizer2
135. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3
136. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4
137. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram|altsyncram_pnr1:auto_generated
138. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux:cmd_demux
139. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux_001:cmd_demux_001
140. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux
141. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_001
142. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_002
143. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux_001:rsp_demux_003
144. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_004
145. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_005
146. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_006
147. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_007
148. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_008
149. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux_001:rsp_demux_009
150. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_010
151. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_011
152. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_012
153. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_013
154. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_cmd_demux:cmd_demux
155. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_rsp_demux:rsp_demux
156. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_rsp_demux:rsp_demux_001
157. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller
158. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1
159. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1
160. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001
161. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1
162. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1
163. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002
164. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1
165. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_req_sync_uq1
166. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK|altddio_out:ALTDDIO_OUT_component
167. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
168. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component
169. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated
170. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|a_graycounter_cg6:rdptr_g1p
171. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|a_graycounter_8ub:wrptr_g1p
172. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|altsyncram_cia1:fifo_ram
173. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:rs_brp
174. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:rs_bwp
175. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp
176. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13
177. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:ws_brp
178. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:ws_bwp
179. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp
180. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16
181. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component|scfifo_7l91:auto_generated|a_dpfifo_er91:dpfifo|altsyncram_sqs1:FIFOram
182. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component
183. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated
184. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_uv6:rdptr_g1p
185. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_qdc:wrptr_g1p
186. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram
187. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:rs_brp
188. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:rs_bwp
189. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp
190. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15
191. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:ws_brp
192. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:ws_bwp
193. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp
194. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18
195. Source assignments for FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET
196. Source assignments for FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET
197. Source assignments for FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET
198. Source assignments for FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET
199. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component
200. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
201. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
202. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
203. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
204. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
205. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
206. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp
207. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6
208. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
209. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
210. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp
211. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9
212. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component
213. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
214. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
215. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
216. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
217. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
218. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
219. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp
220. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6
221. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
222. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
223. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp
224. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9
225. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component
226. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
227. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
228. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
229. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
230. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
231. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
232. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp
233. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6
234. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
235. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
236. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp
237. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9
238. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component
239. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
240. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
241. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
242. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
243. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
244. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
245. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp
246. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6
247. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
248. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
249. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp
250. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9
251. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component
252. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
253. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
254. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
255. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
256. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
257. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
258. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp
259. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6
260. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
261. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
262. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp
263. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9
264. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component
265. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
266. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
267. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
268. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
269. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
270. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
271. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp
272. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6
273. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
274. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
275. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp
276. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9
277. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component
278. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
279. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
280. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
281. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
282. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
283. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
284. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp
285. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6
286. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
287. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
288. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp
289. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9
290. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component
291. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
292. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
293. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
294. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
295. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
296. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
297. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp
298. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6
299. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
300. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
301. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp
302. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9
303. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component
304. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
305. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
306. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
307. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
308. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
309. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
310. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp
311. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6
312. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
313. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
314. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp
315. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9
316. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component
317. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
318. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
319. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
320. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
321. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
322. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
323. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp
324. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6
325. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
326. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
327. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp
328. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9
329. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component
330. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
331. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
332. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
333. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
334. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
335. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
336. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp
337. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6
338. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
339. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
340. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp
341. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9
342. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component
343. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
344. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
345. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
346. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
347. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
348. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
349. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp
350. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6
351. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
352. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
353. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp
354. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9
355. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component
356. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
357. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
358. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
359. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
360. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
361. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
362. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp
363. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6
364. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
365. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
366. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp
367. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9
368. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component
369. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
370. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
371. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
372. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
373. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
374. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
375. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp
376. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6
377. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
378. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
379. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp
380. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9
381. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component
382. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
383. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
384. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
385. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
386. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
387. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
388. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp
389. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6
390. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
391. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
392. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp
393. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9
394. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component
395. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
396. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
397. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
398. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
399. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
400. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
401. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp
402. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6
403. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
404. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
405. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp
406. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9
407. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component
408. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
409. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component
410. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
411. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component
412. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
413. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component
414. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
415. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component
416. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
417. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component
418. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
419. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component
420. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
421. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component
422. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
423. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component
424. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
425. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component
426. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
427. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component
428. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
429. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component
430. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
431. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component
432. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
433. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component
434. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
435. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component
436. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
437. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component
438. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
439. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component
440. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
441. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component
442. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
443. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component
444. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
445. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component
446. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
447. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component
448. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
449. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component
450. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
451. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component
452. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
453. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component
454. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
455. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component
456. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
457. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component
458. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
459. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component
460. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
461. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component
462. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
463. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component
464. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
465. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component
466. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
467. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component
468. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
469. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component
470. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
471. Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo|altsyncram:mem_rtl_0|altsyncram_23n1:auto_generated
472. Parameter Settings for User Entity Instance: FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i
473. Parameter Settings for User Entity Instance: FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i
474. Parameter Settings for User Entity Instance: FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE
475. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER
476. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER
477. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo
478. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|altera_std_synchronizer:rdreq_sync_i
479. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram|altsyncram:the_altsyncram
480. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_tx_dpram:enet_nios_tx_dpram|altsyncram:the_altsyncram
481. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal
482. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers
483. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|write_signal_breakout:the_write_signal_breakout
484. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|read_signal_breakout:the_read_signal_breakout
485. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO
486. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram
487. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO
488. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram
489. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block
490. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block
491. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO
492. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal
493. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo
494. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|ST_to_MM_Adapter:the_ST_to_MM_Adapter
495. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|byte_enable_generator:the_byte_enable_generator
496. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|write_burst_control:the_write_burst_control
497. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal
498. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers
499. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|write_signal_breakout:the_write_signal_breakout
500. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|read_signal_breakout:the_read_signal_breakout
501. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO
502. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram
503. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO
504. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram
505. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block
506. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block
507. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal
508. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|MM_to_ST_Adapter:the_MM_to_ST_adapter
509. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo
510. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|read_burst_control:the_read_burst_control
511. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram|altsyncram:the_altsyncram
512. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_avalon_mm_bridge:if_bridge
513. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:if_bridge_m0_translator
514. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_s1_translator
515. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_s1_translator
516. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_s1_translator
517. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_ip_addr_s1_translator
518. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_ip_addr_s1_translator
519. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator
520. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_l_s1_translator
521. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_h_s1_translator
522. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_l_s1_translator
523. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_h_s1_translator
524. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:testing_s1_translator
525. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:version_s1_translator
526. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator
527. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator
528. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator
529. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:if_bridge_m0_agent
530. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_s1_agent
531. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor
532. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo
533. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_s1_agent
534. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor
535. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo
536. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_s1_agent
537. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor
538. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo
539. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_ip_addr_s1_agent
540. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor
541. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo
542. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_ip_addr_s1_agent
543. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor
544. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo
545. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:rot_switch_s1_agent
546. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:rot_switch_s1_agent|altera_merlin_burst_uncompressor:uncompressor
547. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo
548. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_l_s1_agent
549. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor
550. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo
551. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_h_s1_agent
552. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor
553. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo
554. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_l_s1_agent
555. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor
556. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo
557. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_h_s1_agent
558. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor
559. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo
560. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:testing_s1_agent
561. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:testing_s1_agent|altera_merlin_burst_uncompressor:uncompressor
562. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo
563. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:version_s1_agent
564. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:version_s1_agent|altera_merlin_burst_uncompressor:uncompressor
565. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo
566. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_in_s1_agent
567. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor
568. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo
569. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_in_s1_agent
570. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor
571. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo
572. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_in_s1_agent
573. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor
574. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo
575. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router:router|nios2_fabric_if_mm_interconnect_0_router_default_decode:the_default_decode
576. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_001|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode
577. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_002|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode
578. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_003|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode
579. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_004|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode
580. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_005|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode
581. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_006|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode
582. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_007|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode
583. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_008|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode
584. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_009|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode
585. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_010|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode
586. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_011|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode
587. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_012|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode
588. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_013|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode
589. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_014|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode
590. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_015|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode
591. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:if_bridge_m0_limiter
592. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb
593. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder
594. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter
595. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001
596. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002
597. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003
598. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_004
599. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005
600. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006
601. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007
602. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008
603. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009
604. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010
605. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011
606. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012
607. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013
608. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_014
609. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller
610. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1
611. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1
612. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo
613. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r|scfifo:rfifo
614. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a
615. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a|altsyncram:the_altsyncram
616. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_b_module:nios2_nios2_cpu_register_bank_b
617. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_b_module:nios2_nios2_cpu_register_bank_b|altsyncram:the_altsyncram
618. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_debug:the_nios2_nios2_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer
619. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram
620. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram|altsyncram:the_altsyncram
621. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|altera_std_synchronizer:the_altera_std_synchronizer1
622. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|altera_std_synchronizer:the_altera_std_synchronizer2
623. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3
624. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4
625. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:nios2_nios2_cpu_debug_slave_phy
626. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem
627. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram
628. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_pll_enet:pll_enet|altera_pll:altera_pll_i
629. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_data_master_translator
630. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_instruction_master_translator
631. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator
632. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:eth_tse_mac_control_port_translator
633. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_csr_translator
634. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:nios2_debug_mem_slave_translator
635. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator
636. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fabric_if_if_bridge_slave_translator
637. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator
638. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator
639. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_response_translator
640. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:onchip_mem_s1_translator
641. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_tx_dpram_s1_translator
642. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_ctrl_s1_translator
643. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator
644. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_rx_dpram_s1_translator
645. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_data_master_agent
646. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_instruction_master_agent
647. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent
648. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent|altera_merlin_burst_uncompressor:uncompressor
649. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo
650. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:eth_tse_mac_control_port_agent
651. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:eth_tse_mac_control_port_agent|altera_merlin_burst_uncompressor:uncompressor
652. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo
653. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_csr_agent
654. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_csr_agent|altera_merlin_burst_uncompressor:uncompressor
655. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo
656. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:nios2_debug_mem_slave_agent
657. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:nios2_debug_mem_slave_agent|altera_merlin_burst_uncompressor:uncompressor
658. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo
659. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_descriptor_slave_agent
660. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_descriptor_slave_agent|altera_merlin_burst_uncompressor:uncompressor
661. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo
662. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fabric_if_if_bridge_slave_agent
663. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fabric_if_if_bridge_slave_agent|altera_merlin_burst_uncompressor:uncompressor
664. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo
665. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_agent
666. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_agent|altera_merlin_burst_uncompressor:uncompressor
667. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo
668. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_csr_agent
669. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_csr_agent|altera_merlin_burst_uncompressor:uncompressor
670. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo
671. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_response_agent
672. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_response_agent|altera_merlin_burst_uncompressor:uncompressor
673. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo
674. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:onchip_mem_s1_agent
675. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:onchip_mem_s1_agent|altera_merlin_burst_uncompressor:uncompressor
676. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo
677. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_tx_dpram_s1_agent
678. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_tx_dpram_s1_agent|altera_merlin_burst_uncompressor:uncompressor
679. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo
680. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_ctrl_s1_agent
681. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_ctrl_s1_agent|altera_merlin_burst_uncompressor:uncompressor
682. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo
683. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_status_s1_agent
684. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor
685. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo
686. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_rx_dpram_s1_agent
687. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_rx_dpram_s1_agent|altera_merlin_burst_uncompressor:uncompressor
688. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo
689. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router:router|nios2_mm_interconnect_0_router_default_decode:the_default_decode
690. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_001:router_001|nios2_mm_interconnect_0_router_001_default_decode:the_default_decode
691. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_002|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode
692. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_003|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode
693. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_004|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode
694. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_005:router_005|nios2_mm_interconnect_0_router_005_default_decode:the_default_decode
695. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_006:router_006|nios2_mm_interconnect_0_router_006_default_decode:the_default_decode
696. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_007|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode
697. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_008|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode
698. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_009|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode
699. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_010|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode
700. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_005:router_011|nios2_mm_interconnect_0_router_005_default_decode:the_default_decode
701. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_012|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode
702. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_013|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode
703. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_014|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode
704. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_015|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode
705. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003|altera_merlin_arbitrator:arb
706. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder
707. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_009|altera_merlin_arbitrator:arb
708. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_009|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder
709. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb
710. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder
711. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux_001:rsp_mux_001|altera_merlin_arbitrator:arb
712. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux_001:rsp_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder
713. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter
714. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor
715. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_rsp_width_adapter
716. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter
717. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001
718. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002
719. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003
720. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter_004:avalon_st_adapter_004
721. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005
722. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006
723. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007
724. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008
725. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009
726. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010
727. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011
728. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012
729. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013
730. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_translator:enet_tx_msgdma_mm_read_translator
731. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_nios_tx_dpram_s2_translator
732. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_udp_dpram_s2_translator
733. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_agent:enet_tx_msgdma_mm_read_agent
734. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_nios_tx_dpram_s2_agent
735. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_nios_tx_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor
736. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo
737. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_udp_dpram_s2_agent
738. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_udp_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor
739. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo
740. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router:router|nios2_mm_interconnect_1_router_default_decode:the_default_decode
741. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router_001:router_001|nios2_mm_interconnect_1_router_001_default_decode:the_default_decode
742. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router_001:router_002|nios2_mm_interconnect_1_router_001_default_decode:the_default_decode
743. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_traffic_limiter:enet_tx_msgdma_mm_read_limiter
744. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb
745. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder
746. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter
747. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001
748. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_2:mm_interconnect_2|altera_merlin_master_translator:enet_rx_msgdma_mm_write_translator
749. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_2:mm_interconnect_2|altera_merlin_slave_translator:enet_nios_rx_dpram_s2_translator
750. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter
751. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo
752. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller
753. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1
754. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1
755. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001
756. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1
757. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1
758. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002
759. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1
760. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_req_sync_uq1
761. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK|altddio_out:ALTDDIO_OUT_component
762. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER
763. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_CSR_SM:C_MSGDMA_CSR_SM
764. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM
765. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM
766. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DISPATCHER:C_MSGDMA_DISPATCHER
767. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component
768. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFO_CHECK:C_SC_FIFO_CHECK
769. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFO_CHECK:C_DAQ_FIFO_CHECK
770. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component
771. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component
772. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC
773. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC
774. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER
775. Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER
776. Parameter Settings for User Entity Instance: FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component
777. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS
778. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET
779. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET
780. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET
781. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET
782. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET
783. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET
784. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET
785. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SETGET_ACK:C_GET_ACK
786. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER
787. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM
788. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM
789. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED
790. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED
791. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED
792. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED
793. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED
794. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED
795. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED
796. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED
797. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX
798. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX
799. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX
800. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX
801. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX
802. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX
803. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX
804. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX
805. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component
806. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component
807. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component
808. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component
809. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component
810. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component
811. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component
812. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component
813. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component
814. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component
815. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component
816. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component
817. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component
818. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component
819. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component
820. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component
821. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC
822. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM
823. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0
824. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1
825. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component
826. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component
827. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component
828. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component
829. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component
830. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component
831. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component
832. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component
833. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component
834. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component
835. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component
836. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component
837. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component
838. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component
839. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component
840. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component
841. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component
842. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component
843. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component
844. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component
845. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component
846. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component
847. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component
848. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component
849. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component
850. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component
851. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component
852. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component
853. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component
854. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component
855. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component
856. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component
857. Parameter Settings for Inferred Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo|altsyncram:mem_rtl_0
858. dcfifo Parameter Settings by Entity Instance
859. scfifo Parameter Settings by Entity Instance
860. altsyncram Parameter Settings by Entity Instance
861. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1"
862. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1"
863. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1"
864. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1"
865. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1"
866. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1"
867. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1"
868. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1"
869. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0"
870. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0"
871. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0"
872. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0"
873. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0"
874. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0"
875. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0"
876. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0"
877. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX"
878. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX"
879. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX"
880. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX"
881. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX"
882. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX"
883. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX"
884. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX"
885. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED"
886. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED"
887. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED"
888. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED"
889. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED"
890. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED"
891. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED"
892. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED"
893. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER"
894. Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET"
895. Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET"
896. Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET"
897. Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET"
898. Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET"
899. Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET"
900. Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET"
901. Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS"
902. Port Connectivity Checks: "FTR_L2_FIFO:C_L2_FIFO"
903. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER"
904. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER"
905. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC"
906. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX"
907. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO"
908. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK"
909. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_req_sync_uq1"
910. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002"
911. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001"
912. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1"
913. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller"
914. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo"
915. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_2:mm_interconnect_2|altera_merlin_slave_translator:enet_nios_rx_dpram_s2_translator"
916. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_2:mm_interconnect_2|altera_merlin_master_translator:enet_rx_msgdma_mm_write_translator"
917. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router_001:router_001|nios2_mm_interconnect_1_router_001_default_decode:the_default_decode"
918. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router:router|nios2_mm_interconnect_1_router_default_decode:the_default_decode"
919. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo"
920. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_udp_dpram_s2_agent"
921. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo"
922. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_nios_tx_dpram_s2_agent"
923. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_agent:enet_tx_msgdma_mm_read_agent"
924. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_udp_dpram_s2_translator"
925. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_nios_tx_dpram_s2_translator"
926. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_translator:enet_tx_msgdma_mm_read_translator"
927. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_rsp_width_adapter"
928. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor"
929. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter"
930. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux_001:rsp_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder"
931. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder"
932. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder"
933. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_006:router_006|nios2_mm_interconnect_0_router_006_default_decode:the_default_decode"
934. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_005:router_005|nios2_mm_interconnect_0_router_005_default_decode:the_default_decode"
935. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_002|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode"
936. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_001:router_001|nios2_mm_interconnect_0_router_001_default_decode:the_default_decode"
937. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router:router|nios2_mm_interconnect_0_router_default_decode:the_default_decode"
938. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo"
939. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_rx_dpram_s1_agent"
940. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo"
941. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_status_s1_agent"
942. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo"
943. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_ctrl_s1_agent"
944. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo"
945. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_tx_dpram_s1_agent"
946. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo"
947. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:onchip_mem_s1_agent"
948. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo"
949. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_response_agent"
950. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo"
951. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_csr_agent"
952. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo"
953. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_agent"
954. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo"
955. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fabric_if_if_bridge_slave_agent"
956. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo"
957. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_descriptor_slave_agent"
958. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo"
959. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:nios2_debug_mem_slave_agent"
960. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo"
961. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_csr_agent"
962. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo"
963. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:eth_tse_mac_control_port_agent"
964. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo"
965. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent"
966. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_instruction_master_agent"
967. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_data_master_agent"
968. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_rx_dpram_s1_translator"
969. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator"
970. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_ctrl_s1_translator"
971. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_tx_dpram_s1_translator"
972. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:onchip_mem_s1_translator"
973. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_response_translator"
974. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator"
975. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator"
976. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fabric_if_if_bridge_slave_translator"
977. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator"
978. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:nios2_debug_mem_slave_translator"
979. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_csr_translator"
980. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:eth_tse_mac_control_port_translator"
981. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator"
982. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_instruction_master_translator"
983. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_data_master_translator"
984. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_pll_enet:pll_enet|altera_pll:altera_pll_i"
985. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem"
986. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:nios2_nios2_cpu_debug_slave_phy"
987. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4"
988. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3"
989. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_pib:the_nios2_nios2_cpu_nios2_oci_pib"
990. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_fifo:the_nios2_nios2_cpu_nios2_oci_fifo|nios2_nios2_cpu_nios2_oci_fifo_wrptr_inc:the_nios2_nios2_cpu_nios2_oci_fifo_wrptr_inc"
991. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_dtrace:the_nios2_nios2_cpu_nios2_oci_dtrace|nios2_nios2_cpu_nios2_oci_td_mode:nios2_nios2_cpu_nios2_oci_trc_ctrl_td_mode"
992. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_itrace:the_nios2_nios2_cpu_nios2_oci_itrace"
993. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_dbrk:the_nios2_nios2_cpu_nios2_oci_dbrk"
994. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_xbrk:the_nios2_nios2_cpu_nios2_oci_xbrk"
995. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_debug:the_nios2_nios2_cpu_nios2_oci_debug"
996. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci"
997. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_test_bench:the_nios2_nios2_cpu_test_bench"
998. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2"
999. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic"
1000. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0"
1001. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1"
1002. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller"
1003. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder"
1004. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_001|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode"
1005. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router:router|nios2_fabric_if_mm_interconnect_0_router_default_decode:the_default_decode"
1006. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo"
1007. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_in_s1_agent"
1008. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo"
1009. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_in_s1_agent"
1010. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo"
1011. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_in_s1_agent"
1012. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo"
1013. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:version_s1_agent"
1014. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo"
1015. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:testing_s1_agent"
1016. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo"
1017. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_h_s1_agent"
1018. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo"
1019. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_l_s1_agent"
1020. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo"
1021. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_h_s1_agent"
1022. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo"
1023. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_l_s1_agent"
1024. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo"
1025. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:rot_switch_s1_agent"
1026. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo"
1027. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_ip_addr_s1_agent"
1028. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo"
1029. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_ip_addr_s1_agent"
1030. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo"
1031. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_s1_agent"
1032. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo"
1033. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_s1_agent"
1034. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo"
1035. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_s1_agent"
1036. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:if_bridge_m0_agent"
1037. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator"
1038. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator"
1039. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator"
1040. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:version_s1_translator"
1041. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:testing_s1_translator"
1042. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_h_s1_translator"
1043. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_l_s1_translator"
1044. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_h_s1_translator"
1045. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_l_s1_translator"
1046. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator"
1047. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_ip_addr_s1_translator"
1048. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_ip_addr_s1_translator"
1049. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_s1_translator"
1050. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_s1_translator"
1051. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_s1_translator"
1052. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:if_bridge_m0_translator"
1053. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_avalon_mm_bridge:if_bridge"
1054. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac"
1055. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram"
1056. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|read_burst_control:the_read_burst_control"
1057. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal"
1058. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block"
1059. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO"
1060. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|read_signal_breakout:the_read_signal_breakout"
1061. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|write_signal_breakout:the_write_signal_breakout"
1062. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal"
1063. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|write_burst_control:the_write_burst_control"
1064. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|byte_enable_generator:the_byte_enable_generator"
1065. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal"
1066. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block"
1067. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO"
1068. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|read_signal_breakout:the_read_signal_breakout"
1069. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|write_signal_breakout:the_write_signal_breakout"
1070. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal"
1071. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_tx_dpram:enet_nios_tx_dpram"
1072. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram"
1073. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS"
1074. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER"
1075. Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER"
1076. Port Connectivity Checks: "FTR_CLK_WRAPPER:C_CLK_WRAPPER"
1077. Post-Synthesis Netlist Statistics for Top Partition
1078. Elapsed Time Per Partition
1079. Analysis & Synthesis Messages
1080. Analysis & Synthesis Suppressed Messages



----------------
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refer to the applicable agreement for further details.



+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                      ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status     ; Successful - Mon Nov 30 09:47:20 2020           ;
; Quartus Prime Version           ; 18.0.0 Build 614 04/24/2018 SJ Standard Edition ;
; Revision Name                   ; FTR_TOP                                         ;
; Top-level Entity Name           ; FTR_TOP                                         ;
; Family                          ; Cyclone V                                       ;
; Logic utilization (in ALMs)     ; N/A                                             ;
; Total registers                 ; 10062                                           ;
; Total pins                      ; 195                                             ;
; Total virtual pins              ; 0                                               ;
; Total block memory bits         ; 4,379,392                                       ;
; Total DSP Blocks                ; 0                                               ;
; Total HSSI RX PCSs              ; 0                                               ;
; Total HSSI PMA RX Deserializers ; 0                                               ;
; Total HSSI TX PCSs              ; 0                                               ;
; Total HSSI PMA TX Serializers   ; 0                                               ;
; Total PLLs                      ; 3                                               ;
; Total DLLs                      ; 0                                               ;
+---------------------------------+-------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                             ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                          ; Setting            ; Default Value      ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                          ; 5CEBA7F23C8        ;                    ;
; Top-level entity name                                                           ; FTR_TOP            ; FTR_TOP            ;
; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
; VHDL Show LMF Mapping Messages                                                  ; Off                ;                    ;
; VHDL Version                                                                    ; VHDL_2008          ; VHDL_1993          ;
; Use smart compilation                                                           ; Off                ; Off                ;
; Enable parallel Assembler and Timing Analyzer during compilation                ; On                 ; On                 ;
; Enable compact report table                                                     ; Off                ; Off                ;
; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
; Preserve fewer node names                                                       ; On                 ; On                 ;
; Intel FPGA IP Evaluation Mode                                                   ; Enable             ; Enable             ;
; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
; State Machine Processing                                                        ; Auto               ; Auto               ;
; Safe State Machine                                                              ; Off                ; Off                ;
; Extract Verilog State Machines                                                  ; On                 ; On                 ;
; Extract VHDL State Machines                                                     ; On                 ; On                 ;
; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
; Parallel Synthesis                                                              ; On                 ; On                 ;
; DSP Block Balancing                                                             ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                              ; On                 ; On                 ;
; Power-Up Don't Care                                                             ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
; Remove Duplicate Registers                                                      ; On                 ; On                 ;
; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
; Optimization Technique                                                          ; Balanced           ; Balanced           ;
; Carry Chain Length                                                              ; 70                 ; 70                 ;
; Auto Carry Chains                                                               ; On                 ; On                 ;
; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
; Auto ROM Replacement                                                            ; On                 ; On                 ;
; Auto RAM Replacement                                                            ; On                 ; On                 ;
; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
; Strict RAM Replacement                                                          ; Off                ; Off                ;
; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                           ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
; Report Parameter Settings                                                       ; On                 ; On                 ;
; Report Source Assignments                                                       ; On                 ; On                 ;
; Report Connectivity Checks                                                      ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
; Power Optimization During Synthesis                                             ; Normal compilation ; Normal compilation ;
; HDL message level                                                               ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                            ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
; Block Design Naming                                                             ; Auto               ; Auto               ;
; SDC constraint protection                                                       ; Off                ; Off                ;
; Synthesis Effort                                                                ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
+---------------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.23        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   7.6%      ;
;     Processor 3            ;   7.6%      ;
;     Processor 4            ;   7.6%      ;
+----------------------------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------------------------------+-----------------+----------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+-------------+
; File Name with User-Entered Path                                                                                                 ; Used in Netlist ; File Type                                    ; File Name with Absolute Path                                                                                                             ; Library     ;
+----------------------------------------------------------------------------------------------------------------------------------+-----------------+----------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+-------------+
; ../../../lib/u_util/exp/u_size.vhd                                                                                               ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/u_util/exp/u_size.vhd                                                                                               ;             ;
; ../../../lib/usb_usb/exp/usb_usb.vhd                                                                                             ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/usb_usb/exp/usb_usb.vhd                                                                                             ;             ;
; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                                                                              ; yes             ; User Wizard-Generated File                   ; J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                                                                              ;             ;
; ../../../lib/ser_serialCommunication/exp/ser_crc_pck.vhd                                                                         ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/exp/ser_crc_pck.vhd                                                                         ;             ;
; ../../../lib/ser_serialCommunication/src/ser_crc_pck_polynomial.vhd                                                              ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc_pck_polynomial.vhd                                                              ;             ;
; ../../../lib/ser_serialCommunication/src/ser_crc.vhd                                                                             ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc.vhd                                                                             ;             ;
; ../../../lib/ser_serialCommunication/src/crc_pol/ser_crc_pol16_DIN16_D4_1a2eb.vhd                                                ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/crc_pol/ser_crc_pol16_DIN16_D4_1a2eb.vhd                                                ;             ;
; ../../../lib/UFP_UsbFrontEndProtocol/exp/UFP_Protocol.vhd                                                                        ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_Protocol.vhd                                                                        ;             ;
; ../../../lib/UFP_UsbFrontEndProtocol/exp/UFP_fw_version.vhd                                                                      ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_fw_version.vhd                                                                      ;             ;
; ../../../lib/UFP_UsbFrontEndProtocol/src/UFP_Decoder.vhd                                                                         ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Decoder.vhd                                                                         ;             ;
; ../../../lib/UFP_UsbFrontEndProtocol/src/UFP_Encoder_uart.vhd                                                                    ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Encoder_uart.vhd                                                                    ;             ;
; ../../../lib/UFP_UsbFrontEndProtocol/src/UFP_USER_GET_CONFIG.vhd                                                                 ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_GET_CONFIG.vhd                                                                 ;             ;
; ../../../lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SET_CONFIG.vhd                                                                 ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SET_CONFIG.vhd                                                                 ;             ;
; ../../../lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SETGET_ACK.vhd                                                                 ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SETGET_ACK.vhd                                                                 ;             ;
; ../../../lib/eth_ethernet/exp/ETH_ETHERNET.vhd                                                                                   ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/eth_ethernet/exp/ETH_ETHERNET.vhd                                                                                   ;             ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v                                                                     ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v                                                                     ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_reset_controller.v                                        ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_reset_controller.v                                        ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_reset_synchronizer.v                                      ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_reset_synchronizer.v                                      ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_avalon_st_adapter.v                                        ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_avalon_st_adapter.v                                        ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_avalon_st_adapter_timing_adapter_0.sv                      ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_avalon_st_adapter_timing_adapter_0.sv                      ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_avalon_st_adapter_timing_adapter_0_fifo.sv                 ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_avalon_st_adapter_timing_adapter_0_fifo.sv                 ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_irq_mapper.sv                                              ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_irq_mapper.sv                                              ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_2.v                                        ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_2.v                                        ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_slave_translator.sv                                ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_slave_translator.sv                                ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_master_translator.sv                               ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_master_translator.sv                               ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1.v                                        ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1.v                                        ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter.v                      ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter.v                      ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv     ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv     ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_rsp_mux.sv                               ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_rsp_mux.sv                               ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_arbitrator.sv                                      ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_arbitrator.sv                                      ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_rsp_demux.sv                             ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_rsp_demux.sv                             ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_cmd_mux.sv                               ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_cmd_mux.sv                               ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_cmd_demux.sv                             ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_cmd_demux.sv                             ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_traffic_limiter.sv                                 ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_traffic_limiter.sv                                 ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_avalon_sc_fifo.v                                          ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_avalon_sc_fifo.v                                          ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_router_001.sv                            ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_router_001.sv                            ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_router.sv                                ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_router.sv                                ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_slave_agent.sv                                     ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_slave_agent.sv                                     ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_burst_uncompressor.sv                              ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_burst_uncompressor.sv                              ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_master_agent.sv                                    ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_master_agent.sv                                    ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v                                        ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v                                        ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter_004.v                  ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter_004.v                  ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0.sv ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0.sv ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_width_adapter.sv                                   ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_width_adapter.sv                                   ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_mux_001.sv                           ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_mux_001.sv                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_mux.sv                               ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_mux.sv                               ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_demux.sv                             ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_demux.sv                             ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_mux_003.sv                           ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_mux_003.sv                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_mux.sv                               ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_mux.sv                               ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_demux_001.sv                         ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_demux_001.sv                         ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_demux.sv                             ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_demux.sv                             ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_006.sv                            ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_006.sv                            ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_005.sv                            ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_005.sv                            ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_002.sv                            ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_002.sv                            ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_001.sv                            ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_001.sv                            ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router.sv                                ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router.sv                                ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_pll_enet.v                                                 ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_pll_enet.v                                                 ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_onchip_mem.v                                               ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_onchip_mem.v                                               ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2.v                                                    ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2.v                                                    ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v                                                ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v                                                ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_sysclk.v                             ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_sysclk.v                             ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_tck.v                                ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_tck.v                                ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_wrapper.v                            ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_wrapper.v                            ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_test_bench.v                                     ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_test_bench.v                                     ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_jtag_uart_0.v                                              ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_jtag_uart_0.v                                              ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if.v                                                ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if.v                                                ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v                              ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v                              ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_rsp_mux.sv                     ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_rsp_mux.sv                     ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_rsp_demux.sv                   ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_rsp_demux.sv                   ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_cmd_mux.sv                     ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_cmd_mux.sv                     ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_cmd_demux.sv                   ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_cmd_demux.sv                   ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_router_001.sv                  ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_router_001.sv                  ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_router.sv                      ; yes             ; User SystemVerilog HDL File                  ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_router.sv                      ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_rot_switch.v                                     ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_rot_switch.v                                     ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_TX_STATUS.v                                                ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_TX_STATUS.v                                                ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_own_ip_addr_in.v                                 ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_own_ip_addr_in.v                                 ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_avalon_mm_bridge.v                                        ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_avalon_mm_bridge.v                                        ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_daq_dest_ip_addr.v                               ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_daq_dest_ip_addr.v                               ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_TX_CTRL.v                                                  ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_TX_CTRL.v                                                  ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_eth_tse_mac.v                                              ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_eth_tse_mac.v                                              ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_mac.v                                             ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_mac.v                                             ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_clk_cntl.v                                            ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_clk_cntl.v                                            ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc328checker.v                                       ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc328checker.v                                       ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc328generator.v                                     ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc328generator.v                                     ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc32ctl8.v                                           ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc32ctl8.v                                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc32galois8.v                                        ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc32galois8.v                                        ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_gmii_io.v                                             ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_gmii_io.v                                             ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_lb_read_cntl.v                                        ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_lb_read_cntl.v                                        ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_lb_wrt_cntl.v                                         ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_lb_wrt_cntl.v                                         ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_host_control.v                                        ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_host_control.v                                        ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_control.v                                         ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_control.v                                         ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_register_map.v                                        ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_register_map.v                                        ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_loopback_ff.v                                         ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_loopback_ff.v                                         ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altshifttaps.v                                        ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altshifttaps.v                                        ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_rx.v                                              ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_rx.v                                              ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_tx.v                                              ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_tx.v                                              ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mdio.v                                                ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mdio.v                                                ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mdio_clk_gen.v                                        ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mdio_clk_gen.v                                        ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mdio_cntl.v                                           ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mdio_cntl.v                                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_mdio.v                                            ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_mdio.v                                            ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mii_rx_if.v                                           ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mii_rx_if.v                                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mii_tx_if.v                                           ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mii_tx_if.v                                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_in1.v                                           ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_in1.v                                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_in4.v                                           ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_in4.v                                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_module.v                                        ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_module.v                                        ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_out1.v                                          ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_out1.v                                          ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_out4.v                                          ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_out4.v                                          ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_min_ff.v                                           ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_min_ff.v                                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_stat_extract.v                                     ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_stat_extract.v                                     ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_1geth.v                                           ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_1geth.v                                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo.v                                          ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo.v                                          ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v                              ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v                              ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_min_ff.v                                           ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_min_ff.v                                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_stat_extract.v                                     ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_stat_extract.v                                     ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_std_synchronizer.v                                ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_std_synchronizer.v                                ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_std_synchronizer_bundle.v                         ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_std_synchronizer_bundle.v                         ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_reset_synchronizer.v                                  ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_reset_synchronizer.v                                  ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_clock_crosser.v                                       ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_clock_crosser.v                                       ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_13.v                                           ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_13.v                                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_24.v                                           ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_24.v                                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_34.v                                           ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_34.v                                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_opt_1246.v                                     ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_opt_1246.v                                     ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_gray_cnt.v                                            ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_gray_cnt.v                                            ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_sdpm_altsyncram.v                                     ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_sdpm_altsyncram.v                                     ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v                                 ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v                                 ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_bin_cnt.v                                             ; yes             ; Encrypted User Verilog HDL File              ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_bin_cnt.v                                             ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_std_synchronizer_nocut.v                                  ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_std_synchronizer_nocut.v                                  ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_udp_dpram.v                                           ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_udp_dpram.v                                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_tx_msgdma.v                                           ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_tx_msgdma.v                                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_master.v                                                    ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_master.v                                                    ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/MM_to_ST_Adapter.v                                               ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/MM_to_ST_Adapter.v                                               ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_burst_control.v                                             ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_burst_control.v                                             ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/dispatcher.v                                                     ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/dispatcher.v                                                     ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/descriptor_buffers.v                                             ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/descriptor_buffers.v                                             ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/csr_block.v                                                      ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/csr_block.v                                                      ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/response_block.v                                                 ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/response_block.v                                                 ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/fifo_with_byteenables.v                                          ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/fifo_with_byteenables.v                                          ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_signal_breakout.v                                           ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_signal_breakout.v                                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_signal_breakout.v                                          ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_signal_breakout.v                                          ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_rx_msgdma.v                                           ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_rx_msgdma.v                                           ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_master.v                                                   ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_master.v                                                   ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/byte_enable_generator.v                                          ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/byte_enable_generator.v                                          ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/ST_to_MM_Adapter.v                                               ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/ST_to_MM_Adapter.v                                               ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_burst_control.v                                            ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_burst_control.v                                            ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_nios_tx_dpram.v                                       ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_nios_tx_dpram.v                                       ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_nios_rx_dpram.v                                       ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_nios_rx_dpram.v                                       ; nios2       ;
; ../../../lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_SER_FIFO_RX.v                                              ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_SER_FIFO_RX.v                                              ; nios2       ;
; ../../../lib/eth_ethernet/src/ETH_MSGDMA_CSR_SM.vhd                                                                              ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_CSR_SM.vhd                                                                              ;             ;
; ../../../lib/eth_ethernet/src/ETH_MSGDMA_DESC_SM.vhd                                                                             ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_DESC_SM.vhd                                                                             ;             ;
; ../../../lib/eth_ethernet/src/ETH_MSGDMA_DISPATCHER.vhd                                                                          ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_DISPATCHER.vhd                                                                          ;             ;
; ../../../lib/eth_ethernet/c_cyclone5/src/ETH_MSGDMA_IRQ_FIFO.vhd                                                                 ; yes             ; User Wizard-Generated File                   ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_MSGDMA_IRQ_FIFO.vhd                                                                 ;             ;
; ../../../lib/eth_ethernet/src/ETH_FIFO_CHECK.vhd                                                                                 ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_FIFO_CHECK.vhd                                                                                 ;             ;
; ../../../lib/eth_ethernet/src/ETH_FIFOS_TO_DPRAM_SM.vhd                                                                          ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_FIFOS_TO_DPRAM_SM.vhd                                                                          ;             ;
; ../../../lib/eth_ethernet/src/ETH_MSGDMA_WRAPPER.vhd                                                                             ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_WRAPPER.vhd                                                                             ;             ;
; ../../../lib/eth_ethernet/src/ETH_WRAPPER.vhd                                                                                    ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_WRAPPER.vhd                                                                                    ;             ;
; ../../../lib/eth_ethernet/src/ETH_UFP_WRAPPER.vhd                                                                                ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_UFP_WRAPPER.vhd                                                                                ;             ;
; ../../../lib/eth_ethernet/c_cyclone5/src/ETH_TX_CLK.vhd                                                                          ; yes             ; User Wizard-Generated File                   ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_TX_CLK.vhd                                                                          ;             ;
; ../../../lib/eth_ethernet/c_cyclone5/src/ETH_SC_FIFO_TX.vhd                                                                      ; yes             ; User Wizard-Generated File                   ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_SC_FIFO_TX.vhd                                                                      ;             ;
; ../../../lib/eth_ethernet/c_cyclone5/src/ETH_SC_FIFO_RX.vhd                                                                      ; yes             ; User Wizard-Generated File                   ; J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_SC_FIFO_RX.vhd                                                                      ;             ;
; ../src/PLL_MAIN.vhd                                                                                                              ; yes             ; User Wizard-Generated File                   ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN.vhd                                                                        ; PLL_MAIN    ;
; ../src/PLL_MAIN/PLL_MAIN_0002.v                                                                                                  ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN/PLL_MAIN_0002.v                                                            ; PLL_MAIN    ;
; ../src/PLL_4K.vhd                                                                                                                ; yes             ; User Wizard-Generated File                   ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K.vhd                                                                          ; PLL_4K      ;
; ../src/PLL_4K/PLL_4K_0002.v                                                                                                      ; yes             ; User Verilog HDL File                        ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K/PLL_4K_0002.v                                                                ; PLL_4K      ;
; ../src/FTR_FINE_PHASE_SM.vhd                                                                                                     ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FINE_PHASE_SM.vhd                                                               ;             ;
; ../src/FTR_PatchPanelControllerSM.vhd                                                                                            ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PatchPanelControllerSM.vhd                                                      ;             ;
; ../src/FTR_PlaneControllerSM.vhd                                                                                                 ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PlaneControllerSM.vhd                                                           ;             ;
; ../src/FTR_PlaneController.vhd                                                                                                   ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PlaneController.vhd                                                             ;             ;
; ../src/FTR_RXDataModuleManager.vhd                                                                                               ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_RXDataModuleManager.vhd                                                         ;             ;
; ../src/FTR_RXDataPlaneManager.vhd                                                                                                ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_RXDataPlaneManager.vhd                                                          ;             ;
; ../src/FTR_L2_SM.vhd                                                                                                             ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_SM.vhd                                                                       ;             ;
; ../src/FTR_FaserWrapper.vhd                                                                                                      ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FaserWrapper.vhd                                                                ;             ;
; ../src/FTR_CLK_WRAPPER.vhd                                                                                                       ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_CLK_WRAPPER.vhd                                                                 ;             ;
; ../src/FTR_REG_WRAPPER.vhd                                                                                                       ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd                                                                 ;             ;
; ../src/FTR_L2_FIFO.vhd                                                                                                           ; yes             ; User Wizard-Generated File                   ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_FIFO.vhd                                                                     ;             ;
; ../src/FTR_L1_FIFO.vhd                                                                                                           ; yes             ; User Wizard-Generated File                   ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L1_FIFO.vhd                                                                     ;             ;
; ../src/FTR_GLOBAL_CONST.vhd                                                                                                      ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_GLOBAL_CONST.vhd                                                                ;             ;
; src/FTR_TOP.vhd                                                                                                                  ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd                                                                 ;             ;
; altera_pll.v                                                                                                                     ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v                                                                           ;             ;
; altera_pll_dps_lcell_comb.v                                                                                                      ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll_dps_lcell_comb.v                                                            ;             ;
; altera_cyclonev_pll.v                                                                                                            ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v                                                                  ;             ;
; dcfifo.tdf                                                                                                                       ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo.tdf                                                                             ;             ;
; lpm_counter.inc                                                                                                                  ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_counter.inc                                                                        ;             ;
; lpm_add_sub.inc                                                                                                                  ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_add_sub.inc                                                                        ;             ;
; altdpram.inc                                                                                                                     ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altdpram.inc                                                                           ;             ;
; a_graycounter.inc                                                                                                                ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_graycounter.inc                                                                      ;             ;
; a_fefifo.inc                                                                                                                     ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fefifo.inc                                                                           ;             ;
; a_gray2bin.inc                                                                                                                   ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_gray2bin.inc                                                                         ;             ;
; dffpipe.inc                                                                                                                      ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/dffpipe.inc                                                                            ;             ;
; alt_sync_fifo.inc                                                                                                                ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/alt_sync_fifo.inc                                                                      ;             ;
; lpm_compare.inc                                                                                                                  ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_compare.inc                                                                        ;             ;
; altsyncram_fifo.inc                                                                                                              ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram_fifo.inc                                                                    ;             ;
; aglobal180.inc                                                                                                                   ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/aglobal180.inc                                                                         ;             ;
; db/dcfifo_iq62.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_iq62.tdf                                                              ;             ;
; db/a_gray2bin_qab.tdf                                                                                                            ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_gray2bin_qab.tdf                                                           ;             ;
; db/a_graycounter_pv6.tdf                                                                                                         ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_graycounter_pv6.tdf                                                        ;             ;
; db/a_graycounter_ldc.tdf                                                                                                         ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_graycounter_ldc.tdf                                                        ;             ;
; db/altsyncram_m8d1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_m8d1.tdf                                                          ;             ;
; db/dffpipe_3dc.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_3dc.tdf                                                              ;             ;
; db/alt_synch_pipe_apl.tdf                                                                                                        ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_apl.tdf                                                       ;             ;
; db/dffpipe_re9.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_re9.tdf                                                              ;             ;
; db/dffpipe_qe9.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_qe9.tdf                                                              ;             ;
; db/alt_synch_pipe_bpl.tdf                                                                                                        ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_bpl.tdf                                                       ;             ;
; db/dffpipe_se9.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_se9.tdf                                                              ;             ;
; db/cmpr_b06.tdf                                                                                                                  ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cmpr_b06.tdf                                                                 ;             ;
; altera_std_synchronizer.v                                                                                                        ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_std_synchronizer.v                                                              ;             ;
; altsyncram.tdf                                                                                                                   ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram.tdf                                                                         ;             ;
; stratix_ram_block.inc                                                                                                            ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/stratix_ram_block.inc                                                                  ;             ;
; lpm_mux.inc                                                                                                                      ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_mux.inc                                                                            ;             ;
; lpm_decode.inc                                                                                                                   ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_decode.inc                                                                         ;             ;
; a_rdenreg.inc                                                                                                                    ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_rdenreg.inc                                                                          ;             ;
; altrom.inc                                                                                                                       ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altrom.inc                                                                             ;             ;
; altram.inc                                                                                                                       ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altram.inc                                                                             ;             ;
; db/altsyncram_g572.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_g572.tdf                                                          ;             ;
; db/altsyncram_p5j1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf                                                          ;             ;
; scfifo.tdf                                                                                                                       ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/scfifo.tdf                                                                             ;             ;
; a_regfifo.inc                                                                                                                    ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_regfifo.inc                                                                          ;             ;
; a_dpfifo.inc                                                                                                                     ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_dpfifo.inc                                                                           ;             ;
; a_i2fifo.inc                                                                                                                     ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_i2fifo.inc                                                                           ;             ;
; a_fffifo.inc                                                                                                                     ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fffifo.inc                                                                           ;             ;
; a_f2fifo.inc                                                                                                                     ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_f2fifo.inc                                                                           ;             ;
; db/scfifo_o871.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/scfifo_o871.tdf                                                              ;             ;
; db/a_dpfifo_b071.tdf                                                                                                             ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_b071.tdf                                                            ;             ;
; db/altsyncram_rgn1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_rgn1.tdf                                                          ;             ;
; db/cmpr_4l8.tdf                                                                                                                  ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cmpr_4l8.tdf                                                                 ;             ;
; db/cntr_hgb.tdf                                                                                                                  ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cntr_hgb.tdf                                                                 ;             ;
; db/cntr_ug7.tdf                                                                                                                  ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cntr_ug7.tdf                                                                 ;             ;
; db/cntr_igb.tdf                                                                                                                  ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cntr_igb.tdf                                                                 ;             ;
; db/scfifo_p871.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/scfifo_p871.tdf                                                              ;             ;
; db/a_dpfifo_c071.tdf                                                                                                             ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_c071.tdf                                                            ;             ;
; db/altsyncram_tgn1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_tgn1.tdf                                                          ;             ;
; db/scfifo_s871.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/scfifo_s871.tdf                                                              ;             ;
; db/a_dpfifo_f071.tdf                                                                                                             ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_f071.tdf                                                            ;             ;
; db/altsyncram_3hn1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_3hn1.tdf                                                          ;             ;
; db/altsyncram_dc72.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_dc72.tdf                                                          ;             ;
; altddio_in.tdf                                                                                                                   ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altddio_in.tdf                                                                         ;             ;
; stratix_ddio.inc                                                                                                                 ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/stratix_ddio.inc                                                                       ;             ;
; cyclone_ddio.inc                                                                                                                 ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/cyclone_ddio.inc                                                                       ;             ;
; db/ddio_in_jsd.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ddio_in_jsd.tdf                                                              ;             ;
; db/ddio_in_gsd.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ddio_in_gsd.tdf                                                              ;             ;
; altddio_out.tdf                                                                                                                  ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altddio_out.tdf                                                                        ;             ;
; stratix_lcell.inc                                                                                                                ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/stratix_lcell.inc                                                                      ;             ;
; db/ddio_out_jhb.tdf                                                                                                              ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ddio_out_jhb.tdf                                                             ;             ;
; db/ddio_out_ghb.tdf                                                                                                              ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ddio_out_ghb.tdf                                                             ;             ;
; db/altsyncram_2vl1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_2vl1.tdf                                                          ;             ;
; db/altsyncram_5ao1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_5ao1.tdf                                                          ;             ;
; db/altsyncram_b9o1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf                                                          ;             ;
; db/altsyncram_n3o1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_n3o1.tdf                                                          ;             ;
; db/altsyncram_3ao1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_3ao1.tdf                                                          ;             ;
; db/altsyncram_n0o1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_n0o1.tdf                                                          ;             ;
; db/scfifo_3291.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/scfifo_3291.tdf                                                              ;             ;
; db/a_dpfifo_5771.tdf                                                                                                             ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_5771.tdf                                                            ;             ;
; db/a_fefifo_7cf.tdf                                                                                                              ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_fefifo_7cf.tdf                                                             ;             ;
; db/cntr_vg7.tdf                                                                                                                  ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cntr_vg7.tdf                                                                 ;             ;
; db/altsyncram_7pu1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_7pu1.tdf                                                          ;             ;
; db/cntr_jgb.tdf                                                                                                                  ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cntr_jgb.tdf                                                                 ;             ;
; alt_jtag_atlantic.v                                                                                                              ; yes             ; Encrypted Megafunction                       ; c:/intelfpga/18.0/quartus/libraries/megafunctions/alt_jtag_atlantic.v                                                                    ;             ;
; sld_jtag_endpoint_adapter.vhd                                                                                                    ; yes             ; Encrypted Megafunction                       ; c:/intelfpga/18.0/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd                                                          ;             ;
; sld_jtag_endpoint_adapter_impl.sv                                                                                                ; yes             ; Encrypted Megafunction                       ; c:/intelfpga/18.0/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter_impl.sv                                                      ;             ;
; db/altsyncram_msi1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_msi1.tdf                                                          ;             ;
; db/altsyncram_qid1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_qid1.tdf                                                          ;             ;
; sld_virtual_jtag_basic.v                                                                                                         ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v                                                               ;             ;
; db/altsyncram_pnr1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_pnr1.tdf                                                          ;             ;
; J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex                                                        ; yes             ; Auto-Found Memory Initialization File        ; J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex                                                                ;             ;
; db/decode_8la.tdf                                                                                                                ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/decode_8la.tdf                                                               ;             ;
; db/mux_5hb.tdf                                                                                                                   ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/mux_5hb.tdf                                                                  ;             ;
; db/ddio_out_b2j.tdf                                                                                                              ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ddio_out_b2j.tdf                                                             ;             ;
; a_fffifo.tdf                                                                                                                     ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fffifo.tdf                                                                           ;             ;
; lpm_ff.inc                                                                                                                       ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_ff.inc                                                                             ;             ;
; lpm_ff.tdf                                                                                                                       ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_ff.tdf                                                                             ;             ;
; lpm_constant.inc                                                                                                                 ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_constant.inc                                                                       ;             ;
; lpm_mux.tdf                                                                                                                      ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_mux.tdf                                                                            ;             ;
; muxlut.inc                                                                                                                       ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/muxlut.inc                                                                             ;             ;
; bypassff.inc                                                                                                                     ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/bypassff.inc                                                                           ;             ;
; altshift.inc                                                                                                                     ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altshift.inc                                                                           ;             ;
; db/mux_ujc.tdf                                                                                                                   ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/mux_ujc.tdf                                                                  ;             ;
; lpm_counter.tdf                                                                                                                  ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_counter.tdf                                                                        ;             ;
; cmpconst.inc                                                                                                                     ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/cmpconst.inc                                                                           ;             ;
; dffeea.inc                                                                                                                       ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/dffeea.inc                                                                             ;             ;
; alt_counter_stratix.inc                                                                                                          ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/alt_counter_stratix.inc                                                                ;             ;
; db/cntr_j3f.tdf                                                                                                                  ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cntr_j3f.tdf                                                                 ;             ;
; a_fefifo.tdf                                                                                                                     ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fefifo.tdf                                                                           ;             ;
; lpm_compare.tdf                                                                                                                  ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_compare.tdf                                                                        ;             ;
; comptree.inc                                                                                                                     ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/comptree.inc                                                                           ;             ;
; db/cmpr_p7g.tdf                                                                                                                  ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cmpr_p7g.tdf                                                                 ;             ;
; db/dcfifo_p6n1.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_p6n1.tdf                                                              ;             ;
; db/a_gray2bin_f9b.tdf                                                                                                            ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_gray2bin_f9b.tdf                                                           ;             ;
; db/a_graycounter_cg6.tdf                                                                                                         ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_graycounter_cg6.tdf                                                        ;             ;
; db/a_graycounter_8ub.tdf                                                                                                         ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_graycounter_8ub.tdf                                                        ;             ;
; db/altsyncram_cia1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_cia1.tdf                                                          ;             ;
; db/dffpipe_0v8.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_0v8.tdf                                                              ;             ;
; db/alt_synch_pipe_g9l.tdf                                                                                                        ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_g9l.tdf                                                       ;             ;
; db/dffpipe_1v8.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_1v8.tdf                                                              ;             ;
; db/alt_synch_pipe_h9l.tdf                                                                                                        ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_h9l.tdf                                                       ;             ;
; db/dffpipe_2v8.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_2v8.tdf                                                              ;             ;
; db/cmpr_0v5.tdf                                                                                                                  ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cmpr_0v5.tdf                                                                 ;             ;
; db/scfifo_7l91.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/scfifo_7l91.tdf                                                              ;             ;
; db/a_dpfifo_er91.tdf                                                                                                             ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_er91.tdf                                                            ;             ;
; db/a_fefifo_b6f.tdf                                                                                                              ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_fefifo_b6f.tdf                                                             ;             ;
; db/altsyncram_sqs1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_sqs1.tdf                                                          ;             ;
; db/dcfifo_kvr1.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_kvr1.tdf                                                              ;             ;
; db/a_gray2bin_vab.tdf                                                                                                            ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_gray2bin_vab.tdf                                                           ;             ;
; db/a_graycounter_uv6.tdf                                                                                                         ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_graycounter_uv6.tdf                                                        ;             ;
; db/a_graycounter_qdc.tdf                                                                                                         ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_graycounter_qdc.tdf                                                        ;             ;
; db/altsyncram_29d1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_29d1.tdf                                                          ;             ;
; db/decode_417.tdf                                                                                                                ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/decode_417.tdf                                                               ;             ;
; db/mux_2t7.tdf                                                                                                                   ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/mux_2t7.tdf                                                                  ;             ;
; db/dffpipe_2f9.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_2f9.tdf                                                              ;             ;
; db/alt_synch_pipe_gpl.tdf                                                                                                        ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_gpl.tdf                                                       ;             ;
; db/dffpipe_3f9.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_3f9.tdf                                                              ;             ;
; db/alt_synch_pipe_hpl.tdf                                                                                                        ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_hpl.tdf                                                       ;             ;
; db/dffpipe_4f9.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_4f9.tdf                                                              ;             ;
; db/cmpr_g06.tdf                                                                                                                  ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cmpr_g06.tdf                                                                 ;             ;
; db/dcfifo_jtr1.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_jtr1.tdf                                                              ;             ;
; db/altsyncram_t8d1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_t8d1.tdf                                                          ;             ;
; db/alt_synch_pipe_epl.tdf                                                                                                        ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_epl.tdf                                                       ;             ;
; db/dffpipe_0f9.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_0f9.tdf                                                              ;             ;
; db/alt_synch_pipe_fpl.tdf                                                                                                        ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_fpl.tdf                                                       ;             ;
; db/dffpipe_1f9.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_1f9.tdf                                                              ;             ;
; sld_hub.vhd                                                                                                                      ; yes             ; Encrypted Megafunction                       ; c:/intelfpga/18.0/quartus/libraries/megafunctions/sld_hub.vhd                                                                            ; altera_sld  ;
; db/ip/sldb91a0071/alt_sld_fab.v                                                                                                  ; yes             ; Encrypted Auto-Found Verilog HDL File        ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ip/sldb91a0071/alt_sld_fab.v                                                 ; alt_sld_fab ;
; db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab.v                                                                           ; yes             ; Encrypted Auto-Found Verilog HDL File        ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab.v                          ; alt_sld_fab ;
; db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_ident.sv                                                                    ; yes             ; Auto-Found SystemVerilog HDL File            ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_ident.sv                   ; alt_sld_fab ;
; db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_presplit.sv                                                                 ; yes             ; Encrypted Auto-Found SystemVerilog HDL File  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_presplit.sv                ; alt_sld_fab ;
; db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd                                                               ; yes             ; Encrypted Auto-Found VHDL File               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd              ; alt_sld_fab ;
; db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_splitter.sv                                                                 ; yes             ; Encrypted Auto-Found SystemVerilog HDL File  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_splitter.sv                ; alt_sld_fab ;
; sld_jtag_hub.vhd                                                                                                                 ; yes             ; Encrypted Megafunction                       ; c:/intelfpga/18.0/quartus/libraries/megafunctions/sld_jtag_hub.vhd                                                                       ;             ;
; sld_rom_sr.vhd                                                                                                                   ; yes             ; Encrypted Megafunction                       ; c:/intelfpga/18.0/quartus/libraries/megafunctions/sld_rom_sr.vhd                                                                         ;             ;
; altshift_taps.tdf                                                                                                                ; yes             ; Megafunction                                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altshift_taps.tdf                                                                      ;             ;
; db/shift_taps_ffv.tdf                                                                                                            ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/shift_taps_ffv.tdf                                                           ;             ;
; db/altsyncram_1r91.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_1r91.tdf                                                          ;             ;
; db/cntr_eif.tdf                                                                                                                  ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cntr_eif.tdf                                                                 ;             ;
; db/altsyncram_23n1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_23n1.tdf                                                          ;             ;
; ../../../lib/UFP_UsbFrontEndProtocol/exp/UFP_UsbFrontEndProtocol.vhd                                                             ; yes             ; User VHDL File                               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_UsbFrontEndProtocol.vhd                                                             ;             ;
; db/dcfifo_ptr1.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_ptr1.tdf                                                              ;             ;
; db/a_gray2bin_sab.tdf                                                                                                            ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_gray2bin_sab.tdf                                                           ;             ;
; db/a_graycounter_rv6.tdf                                                                                                         ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_graycounter_rv6.tdf                                                        ;             ;
; db/a_graycounter_ndc.tdf                                                                                                         ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_graycounter_ndc.tdf                                                        ;             ;
; db/altsyncram_s8d1.tdf                                                                                                           ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_s8d1.tdf                                                          ;             ;
; db/dffpipe_te9.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_te9.tdf                                                              ;             ;
; db/alt_synch_pipe_cpl.tdf                                                                                                        ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_cpl.tdf                                                       ;             ;
; db/dffpipe_ue9.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_ue9.tdf                                                              ;             ;
; db/alt_synch_pipe_dpl.tdf                                                                                                        ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_dpl.tdf                                                       ;             ;
; db/dffpipe_ve9.tdf                                                                                                               ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_ve9.tdf                                                              ;             ;
; db/cmpr_d06.tdf                                                                                                                  ; yes             ; Auto-Generated Megafunction                  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cmpr_d06.tdf                                                                 ;             ;
+----------------------------------------------------------------------------------------------------------------------------------+-----------------+----------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+-------------+


+---------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                   ;
+---------------------------------------------+-----------------+
; Resource                                    ; Usage           ;
+---------------------------------------------+-----------------+
; Estimate of Logic utilization (ALMs needed) ; 6886            ;
;                                             ;                 ;
; Combinational ALUT usage for logic          ; 10095           ;
;     -- 7 input functions                    ; 78              ;
;     -- 6 input functions                    ; 2103            ;
;     -- 5 input functions                    ; 1771            ;
;     -- 4 input functions                    ; 1937            ;
;     -- <=3 input functions                  ; 4206            ;
;                                             ;                 ;
; Dedicated logic registers                   ; 9976            ;
;                                             ;                 ;
; I/O pins                                    ; 195             ;
; I/O registers                               ; 86              ;
; Total MLAB memory bits                      ; 0               ;
; Total block memory bits                     ; 4379392         ;
;                                             ;                 ;
; Total DSP Blocks                            ; 0               ;
;                                             ;                 ;
; Total PLLs                                  ; 3               ;
;     -- PLLs                                 ; 2               ;
;     -- Fractional PLLs                      ; 1               ;
;                                             ;                 ;
; Maximum fan-out node                        ; sl_int_main_clk ;
; Maximum fan-out                             ; 5492            ;
; Total fan-out                               ; 108595          ;
; Average fan-out                             ; 4.94            ;
+---------------------------------------------+-----------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------+--------------+
; Compilation Hierarchy Node                                                                                                              ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                                                                                                                                                                                                                ; Entity Name                                   ; Library Name ;
+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------+--------------+
; |FTR_TOP                                                                                                                                ; 10095 (17)          ; 9976 (20)                 ; 4379392           ; 0          ; 195  ; 0            ; |FTR_TOP                                                                                                                                                                                                                                                                                                                                                                                                                           ; FTR_TOP                                       ; work         ;
;    |ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|                                                                                                  ; 5279 (1)            ; 5255 (0)                  ; 1430272           ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER                                                                                                                                                                                                                                                                                                                                                                                         ; ETH_UFP_WRAPPER                               ; work         ;
;       |ETH_SC_FIFO_RX:C_SC_FIFO_RX|                                                                                                     ; 26 (0)              ; 20 (0)                    ; 2048              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX                                                                                                                                                                                                                                                                                                                                                             ; ETH_SC_FIFO_RX                                ; work         ;
;          |scfifo:scfifo_component|                                                                                                      ; 26 (0)              ; 20 (0)                    ; 2048              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component                                                                                                                                                                                                                                                                                                                                     ; scfifo                                        ; work         ;
;             |scfifo_7l91:auto_generated|                                                                                                ; 26 (0)              ; 20 (0)                    ; 2048              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component|scfifo_7l91:auto_generated                                                                                                                                                                                                                                                                                                          ; scfifo_7l91                                   ; work         ;
;                |a_dpfifo_er91:dpfifo|                                                                                                   ; 26 (2)              ; 20 (0)                    ; 2048              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component|scfifo_7l91:auto_generated|a_dpfifo_er91:dpfifo                                                                                                                                                                                                                                                                                     ; a_dpfifo_er91                                 ; work         ;
;                   |a_fefifo_b6f:fifo_state|                                                                                             ; 12 (6)              ; 8 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component|scfifo_7l91:auto_generated|a_dpfifo_er91:dpfifo|a_fefifo_b6f:fifo_state                                                                                                                                                                                                                                                             ; a_fefifo_b6f                                  ; work         ;
;                      |cntr_vg7:count_usedw|                                                                                             ; 6 (6)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component|scfifo_7l91:auto_generated|a_dpfifo_er91:dpfifo|a_fefifo_b6f:fifo_state|cntr_vg7:count_usedw                                                                                                                                                                                                                                        ; cntr_vg7                                      ; work         ;
;                   |altsyncram_sqs1:FIFOram|                                                                                             ; 0 (0)               ; 0 (0)                     ; 2048              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component|scfifo_7l91:auto_generated|a_dpfifo_er91:dpfifo|altsyncram_sqs1:FIFOram                                                                                                                                                                                                                                                             ; altsyncram_sqs1                               ; work         ;
;                   |cntr_jgb:rd_ptr_count|                                                                                               ; 6 (6)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component|scfifo_7l91:auto_generated|a_dpfifo_er91:dpfifo|cntr_jgb:rd_ptr_count                                                                                                                                                                                                                                                               ; cntr_jgb                                      ; work         ;
;                   |cntr_jgb:wr_ptr|                                                                                                     ; 6 (6)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component|scfifo_7l91:auto_generated|a_dpfifo_er91:dpfifo|cntr_jgb:wr_ptr                                                                                                                                                                                                                                                                     ; cntr_jgb                                      ; work         ;
;       |ETH_SC_FIFO_TX:C_SC_FIFO_TX|                                                                                                     ; 78 (0)              ; 106 (0)                   ; 4096              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX                                                                                                                                                                                                                                                                                                                                                             ; ETH_SC_FIFO_TX                                ; work         ;
;          |dcfifo:dcfifo_component|                                                                                                      ; 78 (0)              ; 106 (0)                   ; 4096              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                                                     ; dcfifo                                        ; work         ;
;             |dcfifo_p6n1:auto_generated|                                                                                                ; 78 (18)             ; 106 (24)                  ; 4096              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated                                                                                                                                                                                                                                                                                                          ; dcfifo_p6n1                                   ; work         ;
;                |a_gray2bin_f9b:rdptr_g_gray2bin|                                                                                        ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|a_gray2bin_f9b:rdptr_g_gray2bin                                                                                                                                                                                                                                                                          ; a_gray2bin_f9b                                ; work         ;
;                |a_gray2bin_f9b:rs_dgwp_gray2bin|                                                                                        ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|a_gray2bin_f9b:rs_dgwp_gray2bin                                                                                                                                                                                                                                                                          ; a_gray2bin_f9b                                ; work         ;
;                |a_gray2bin_f9b:wrptr_g_gray2bin|                                                                                        ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|a_gray2bin_f9b:wrptr_g_gray2bin                                                                                                                                                                                                                                                                          ; a_gray2bin_f9b                                ; work         ;
;                |a_gray2bin_f9b:ws_dgrp_gray2bin|                                                                                        ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|a_gray2bin_f9b:ws_dgrp_gray2bin                                                                                                                                                                                                                                                                          ; a_gray2bin_f9b                                ; work         ;
;                |a_graycounter_8ub:wrptr_g1p|                                                                                            ; 12 (12)             ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|a_graycounter_8ub:wrptr_g1p                                                                                                                                                                                                                                                                              ; a_graycounter_8ub                             ; work         ;
;                |a_graycounter_cg6:rdptr_g1p|                                                                                            ; 13 (13)             ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|a_graycounter_cg6:rdptr_g1p                                                                                                                                                                                                                                                                              ; a_graycounter_cg6                             ; work         ;
;                |alt_synch_pipe_g9l:rs_dgwp|                                                                                             ; 0 (0)               ; 16 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp                                                                                                                                                                                                                                                                               ; alt_synch_pipe_g9l                            ; work         ;
;                   |dffpipe_1v8:dffpipe13|                                                                                               ; 0 (0)               ; 16 (16)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13                                                                                                                                                                                                                                                         ; dffpipe_1v8                                   ; work         ;
;                |alt_synch_pipe_h9l:ws_dgrp|                                                                                             ; 0 (0)               ; 16 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp                                                                                                                                                                                                                                                                               ; alt_synch_pipe_h9l                            ; work         ;
;                   |dffpipe_2v8:dffpipe16|                                                                                               ; 0 (0)               ; 16 (16)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16                                                                                                                                                                                                                                                         ; dffpipe_2v8                                   ; work         ;
;                |altsyncram_cia1:fifo_ram|                                                                                               ; 0 (0)               ; 0 (0)                     ; 4096              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|altsyncram_cia1:fifo_ram                                                                                                                                                                                                                                                                                 ; altsyncram_cia1                               ; work         ;
;                |cmpr_0v5:rdempty_eq_comp|                                                                                               ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|cmpr_0v5:rdempty_eq_comp                                                                                                                                                                                                                                                                                 ; cmpr_0v5                                      ; work         ;
;                |cmpr_0v5:wrfull_eq_comp|                                                                                                ; 3 (3)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|cmpr_0v5:wrfull_eq_comp                                                                                                                                                                                                                                                                                  ; cmpr_0v5                                      ; work         ;
;                |dffpipe_0v8:rs_brp|                                                                                                     ; 0 (0)               ; 7 (7)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:rs_brp                                                                                                                                                                                                                                                                                       ; dffpipe_0v8                                   ; work         ;
;                |dffpipe_0v8:rs_bwp|                                                                                                     ; 0 (0)               ; 7 (7)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:rs_bwp                                                                                                                                                                                                                                                                                       ; dffpipe_0v8                                   ; work         ;
;                |dffpipe_0v8:ws_brp|                                                                                                     ; 0 (0)               ; 7 (7)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:ws_brp                                                                                                                                                                                                                                                                                       ; dffpipe_0v8                                   ; work         ;
;                |dffpipe_0v8:ws_bwp|                                                                                                     ; 0 (0)               ; 7 (7)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:ws_bwp                                                                                                                                                                                                                                                                                       ; dffpipe_0v8                                   ; work         ;
;       |ETH_WRAPPER:C_ETH_WRAPPER|                                                                                                       ; 4775 (21)           ; 4910 (20)                 ; 1424128           ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER                                                                                                                                                                                                                                                                                                                                                               ; ETH_WRAPPER                                   ; work         ;
;          |ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|                                                                                      ; 856 (0)             ; 295 (0)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER                                                                                                                                                                                                                                                                                                                       ; ETH_MSGDMA_WRAPPER                            ; work         ;
;             |ETH_FIFOS_TO_DPRAM_SM:C_SM|                                                                                                ; 724 (724)           ; 187 (187)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM                                                                                                                                                                                                                                                                                            ; ETH_FIFOS_TO_DPRAM_SM                         ; work         ;
;             |ETH_FIFO_CHECK:C_DAQ_FIFO_CHECK|                                                                                           ; 33 (33)             ; 20 (20)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFO_CHECK:C_DAQ_FIFO_CHECK                                                                                                                                                                                                                                                                                       ; ETH_FIFO_CHECK                                ; work         ;
;             |ETH_FIFO_CHECK:C_SC_FIFO_CHECK|                                                                                            ; 28 (28)             ; 20 (20)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFO_CHECK:C_SC_FIFO_CHECK                                                                                                                                                                                                                                                                                        ; ETH_FIFO_CHECK                                ; work         ;
;             |ETH_MSGDMA_CSR_SM:C_MSGDMA_CSR_SM|                                                                                         ; 10 (10)             ; 9 (9)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_CSR_SM:C_MSGDMA_CSR_SM                                                                                                                                                                                                                                                                                     ; ETH_MSGDMA_CSR_SM                             ; work         ;
;             |ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|                                                                                       ; 19 (19)             ; 22 (22)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM                                                                                                                                                                                                                                                                                   ; ETH_MSGDMA_DESC_SM                            ; work         ;
;             |ETH_MSGDMA_DISPATCHER:C_MSGDMA_DISPATCHER|                                                                                 ; 27 (27)             ; 17 (17)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DISPATCHER:C_MSGDMA_DISPATCHER                                                                                                                                                                                                                                                                             ; ETH_MSGDMA_DISPATCHER                         ; work         ;
;             |ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|                                                                                            ; 15 (0)              ; 20 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO                                                                                                                                                                                                                                                                                        ; ETH_MSGDMA_IRQ_FIFO                           ; work         ;
;                |scfifo:scfifo_component|                                                                                                ; 15 (0)              ; 20 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component                                                                                                                                                                                                                                                                ; scfifo                                        ; work         ;
;                   |a_fffifo:subfifo|                                                                                                    ; 15 (2)              ; 20 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo                                                                                                                                                                                                                                               ; a_fffifo                                      ; work         ;
;                      |a_fefifo:fifo_state|                                                                                              ; 7 (7)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|a_fefifo:fifo_state                                                                                                                                                                                                                           ; a_fefifo                                      ; work         ;
;                      |lpm_counter:rd_ptr|                                                                                               ; 3 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_counter:rd_ptr                                                                                                                                                                                                                            ; lpm_counter                                   ; work         ;
;                         |cntr_j3f:auto_generated|                                                                                       ; 3 (3)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_counter:rd_ptr|cntr_j3f:auto_generated                                                                                                                                                                                                    ; cntr_j3f                                      ; work         ;
;                      |lpm_ff:last_data_node[0]|                                                                                         ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_ff:last_data_node[0]                                                                                                                                                                                                                      ; lpm_ff                                        ; work         ;
;                      |lpm_ff:last_data_node[1]|                                                                                         ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_ff:last_data_node[1]                                                                                                                                                                                                                      ; lpm_ff                                        ; work         ;
;                      |lpm_ff:last_data_node[2]|                                                                                         ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_ff:last_data_node[2]                                                                                                                                                                                                                      ; lpm_ff                                        ; work         ;
;                      |lpm_ff:last_data_node[3]|                                                                                         ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_ff:last_data_node[3]                                                                                                                                                                                                                      ; lpm_ff                                        ; work         ;
;                      |lpm_ff:output_buffer|                                                                                             ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_ff:output_buffer                                                                                                                                                                                                                          ; lpm_ff                                        ; work         ;
;                      |lpm_mux:last_row_data_out_mux|                                                                                    ; 3 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_mux:last_row_data_out_mux                                                                                                                                                                                                                 ; lpm_mux                                       ; work         ;
;                         |mux_ujc:auto_generated|                                                                                        ; 3 (3)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_mux:last_row_data_out_mux|mux_ujc:auto_generated                                                                                                                                                                                          ; mux_ujc                                       ; work         ;
;          |ETH_TX_CLK:C_ETH_PCLK|                                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK                                                                                                                                                                                                                                                                                                                                         ; ETH_TX_CLK                                    ; work         ;
;             |altddio_out:ALTDDIO_OUT_component|                                                                                         ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                       ; altddio_out                                   ; work         ;
;                |ddio_out_b2j:auto_generated|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                           ; ddio_out_b2j                                  ; work         ;
;          |nios2:C_NIOS_SYS|                                                                                                             ; 3898 (0)            ; 4595 (0)                  ; 1424128           ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS                                                                                                                                                                                                                                                                                                                                              ; nios2                                         ; nios2        ;
;             |altera_reset_controller:rst_controller_001|                                                                                ; 6 (5)               ; 16 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001                                                                                                                                                                                                                                                                                                   ; altera_reset_controller                       ; nios2        ;
;                |altera_reset_synchronizer:alt_rst_req_sync_uq1|                                                                         ; 1 (1)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1                                                                                                                                                                                                                                                    ; altera_reset_synchronizer                     ; nios2        ;
;                |altera_reset_synchronizer:alt_rst_sync_uq1|                                                                             ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1                                                                                                                                                                                                                                                        ; altera_reset_synchronizer                     ; nios2        ;
;             |altera_reset_controller:rst_controller_002|                                                                                ; 7 (6)               ; 16 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002                                                                                                                                                                                                                                                                                                   ; altera_reset_controller                       ; nios2        ;
;                |altera_reset_synchronizer:alt_rst_req_sync_uq1|                                                                         ; 1 (1)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_req_sync_uq1                                                                                                                                                                                                                                                    ; altera_reset_synchronizer                     ; nios2        ;
;                |altera_reset_synchronizer:alt_rst_sync_uq1|                                                                             ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1                                                                                                                                                                                                                                                        ; altera_reset_synchronizer                     ; nios2        ;
;             |altera_reset_controller:rst_controller|                                                                                    ; 6 (5)               ; 16 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller                                                                                                                                                                                                                                                                                                       ; altera_reset_controller                       ; nios2        ;
;                |altera_reset_synchronizer:alt_rst_req_sync_uq1|                                                                         ; 1 (1)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1                                                                                                                                                                                                                                                        ; altera_reset_synchronizer                     ; nios2        ;
;                |altera_reset_synchronizer:alt_rst_sync_uq1|                                                                             ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1                                                                                                                                                                                                                                                            ; altera_reset_synchronizer                     ; nios2        ;
;             |nios2_SER_FIFO_RX:ser_fifo_rx|                                                                                             ; 182 (1)             ; 200 (1)                   ; 65536             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx                                                                                                                                                                                                                                                                                                                ; nios2_SER_FIFO_RX                             ; nios2        ;
;                |nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|                                                        ; 181 (84)            ; 199 (55)                  ; 65536             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls                                                                                                                                                                                                                                                ; nios2_SER_FIFO_RX_dcfifo_with_controls        ; nios2        ;
;                   |altera_std_synchronizer:rdreq_sync_i|                                                                                ; 0 (0)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|altera_std_synchronizer:rdreq_sync_i                                                                                                                                                                                                           ; altera_std_synchronizer                       ; work         ;
;                   |nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|                                                                        ; 97 (5)              ; 140 (0)                   ; 65536             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo                                                                                                                                                                                                   ; nios2_SER_FIFO_RX_dual_clock_fifo             ; nios2        ;
;                      |dcfifo:dual_clock_fifo|                                                                                           ; 92 (0)              ; 140 (0)                   ; 65536             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo                                                                                                                                                                            ; dcfifo                                        ; work         ;
;                         |dcfifo_iq62:auto_generated|                                                                                    ; 92 (17)             ; 140 (36)                  ; 65536             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated                                                                                                                                                 ; dcfifo_iq62                                   ; work         ;
;                            |a_gray2bin_qab:wrptr_g_gray2bin|                                                                            ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                 ; a_gray2bin_qab                                ; work         ;
;                            |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                            ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                 ; a_gray2bin_qab                                ; work         ;
;                            |a_graycounter_ldc:wrptr_g1p|                                                                                ; 19 (19)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                     ; a_graycounter_ldc                             ; work         ;
;                            |a_graycounter_pv6:rdptr_g1p|                                                                                ; 20 (20)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                     ; a_graycounter_pv6                             ; work         ;
;                            |alt_synch_pipe_apl:rs_dgwp|                                                                                 ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                                                                      ; alt_synch_pipe_apl                            ; work         ;
;                               |dffpipe_re9:dffpipe14|                                                                                   ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14                                                                                                ; dffpipe_re9                                   ; work         ;
;                            |alt_synch_pipe_bpl:ws_dgrp|                                                                                 ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                                                                      ; alt_synch_pipe_bpl                            ; work         ;
;                               |dffpipe_se9:dffpipe18|                                                                                   ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18                                                                                                ; dffpipe_se9                                   ; work         ;
;                            |altsyncram_m8d1:fifo_ram|                                                                                   ; 0 (0)               ; 0 (0)                     ; 65536             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|altsyncram_m8d1:fifo_ram                                                                                                                        ; altsyncram_m8d1                               ; work         ;
;                            |cmpr_b06:rdempty_eq_comp|                                                                                   ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                        ; cmpr_b06                                      ; work         ;
;                            |cmpr_b06:wrempty_eq_comp|                                                                                   ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|cmpr_b06:wrempty_eq_comp                                                                                                                        ; cmpr_b06                                      ; work         ;
;                            |cmpr_b06:wrfull_eq_comp|                                                                                    ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                         ; cmpr_b06                                      ; work         ;
;                            |dffpipe_3dc:rdaclr|                                                                                         ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|dffpipe_3dc:rdaclr                                                                                                                              ; dffpipe_3dc                                   ; work         ;
;                            |dffpipe_3dc:wraclr|                                                                                         ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|dffpipe_3dc:wraclr                                                                                                                              ; dffpipe_3dc                                   ; work         ;
;                            |dffpipe_qe9:ws_brp|                                                                                         ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|dffpipe_qe9:ws_brp                                                                                                                              ; dffpipe_qe9                                   ; work         ;
;                            |dffpipe_qe9:ws_bwp|                                                                                         ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                              ; dffpipe_qe9                                   ; work         ;
;             |nios2_TX_CTRL:tx_ctrl|                                                                                                     ; 19 (19)             ; 16 (16)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_CTRL:tx_ctrl                                                                                                                                                                                                                                                                                                                        ; nios2_TX_CTRL                                 ; nios2        ;
;             |nios2_TX_STATUS:tx_status|                                                                                                 ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status                                                                                                                                                                                                                                                                                                                    ; nios2_TX_STATUS                               ; nios2        ;
;             |nios2_avalon_st_adapter:avalon_st_adapter|                                                                                 ; 22 (0)              ; 11 (0)                    ; 672               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter                                                                                                                                                                                                                                                                                                    ; nios2_avalon_st_adapter                       ; nios2        ;
;                |nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|                                                              ; 22 (1)              ; 11 (0)                    ; 672               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0                                                                                                                                                                                                                                          ; nios2_avalon_st_adapter_timing_adapter_0      ; nios2        ;
;                   |nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo|                         ; 21 (21)             ; 11 (11)                   ; 672               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo                                                                                                                                              ; nios2_avalon_st_adapter_timing_adapter_0_fifo ; nios2        ;
;                      |altsyncram:mem_rtl_0|                                                                                             ; 0 (0)               ; 0 (0)                     ; 672               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo|altsyncram:mem_rtl_0                                                                                                                         ; altsyncram                                    ; work         ;
;                         |altsyncram_23n1:auto_generated|                                                                                ; 0 (0)               ; 0 (0)                     ; 672               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo|altsyncram:mem_rtl_0|altsyncram_23n1:auto_generated                                                                                          ; altsyncram_23n1                               ; work         ;
;             |nios2_enet_nios_rx_dpram:enet_nios_rx_dpram|                                                                               ; 1 (1)               ; 0 (0)                     ; 16384             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram                                                                                                                                                                                                                                                                                                  ; nios2_enet_nios_rx_dpram                      ; nios2        ;
;                |altsyncram:the_altsyncram|                                                                                              ; 0 (0)               ; 0 (0)                     ; 16384             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram|altsyncram:the_altsyncram                                                                                                                                                                                                                                                                        ; altsyncram                                    ; work         ;
;                   |altsyncram_g572:auto_generated|                                                                                      ; 0 (0)               ; 0 (0)                     ; 16384             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram|altsyncram:the_altsyncram|altsyncram_g572:auto_generated                                                                                                                                                                                                                                         ; altsyncram_g572                               ; work         ;
;             |nios2_enet_nios_tx_dpram:enet_nios_tx_dpram|                                                                               ; 1 (1)               ; 0 (0)                     ; 16384             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_tx_dpram:enet_nios_tx_dpram                                                                                                                                                                                                                                                                                                  ; nios2_enet_nios_tx_dpram                      ; nios2        ;
;                |altsyncram:the_altsyncram|                                                                                              ; 0 (0)               ; 0 (0)                     ; 16384             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_tx_dpram:enet_nios_tx_dpram|altsyncram:the_altsyncram                                                                                                                                                                                                                                                                        ; altsyncram                                    ; work         ;
;                   |altsyncram_g572:auto_generated|                                                                                      ; 0 (0)               ; 0 (0)                     ; 16384             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_tx_dpram:enet_nios_tx_dpram|altsyncram:the_altsyncram|altsyncram_g572:auto_generated                                                                                                                                                                                                                                         ; altsyncram_g572                               ; work         ;
;             |nios2_enet_rx_msgdma:enet_rx_msgdma|                                                                                       ; 282 (0)             ; 198 (0)                   ; 3120              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma                                                                                                                                                                                                                                                                                                          ; nios2_enet_rx_msgdma                          ; nios2        ;
;                |dispatcher:dispatcher_internal|                                                                                         ; 128 (1)             ; 119 (1)                   ; 1808              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal                                                                                                                                                                                                                                                                           ; dispatcher                                    ; nios2        ;
;                   |csr_block:the_csr_block|                                                                                             ; 46 (46)             ; 68 (68)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block                                                                                                                                                                                                                                                   ; csr_block                                     ; nios2        ;
;                   |descriptor_buffers:the_descriptor_buffers|                                                                           ; 29 (7)              ; 23 (10)                   ; 496               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers                                                                                                                                                                                                                                 ; descriptor_buffers                            ; nios2        ;
;                      |fifo_with_byteenables:the_write_command_FIFO|                                                                     ; 22 (22)             ; 13 (13)                   ; 496               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO                                                                                                                                                                                    ; fifo_with_byteenables                         ; nios2        ;
;                         |altsyncram:the_dp_ram|                                                                                         ; 0 (0)               ; 0 (0)                     ; 496               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram                                                                                                                                                              ; altsyncram                                    ; work         ;
;                            |altsyncram_p5j1:auto_generated|                                                                             ; 0 (0)               ; 0 (0)                     ; 496               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated                                                                                                                               ; altsyncram_p5j1                               ; work         ;
;                   |response_block:the_response_block|                                                                                   ; 52 (11)             ; 27 (0)                    ; 1312              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block                                                                                                                                                                                                                                         ; response_block                                ; nios2        ;
;                      |scfifo:the_response_FIFO|                                                                                         ; 41 (0)              ; 27 (0)                    ; 1312              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO                                                                                                                                                                                                                ; scfifo                                        ; work         ;
;                         |scfifo_o871:auto_generated|                                                                                    ; 41 (0)              ; 27 (0)                    ; 1312              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated                                                                                                                                                                                     ; scfifo_o871                                   ; work         ;
;                            |a_dpfifo_b071:dpfifo|                                                                                       ; 41 (25)             ; 27 (13)                   ; 1312              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated|a_dpfifo_b071:dpfifo                                                                                                                                                                ; a_dpfifo_b071                                 ; work         ;
;                               |altsyncram_rgn1:FIFOram|                                                                                 ; 0 (0)               ; 0 (0)                     ; 1312              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated|a_dpfifo_b071:dpfifo|altsyncram_rgn1:FIFOram                                                                                                                                        ; altsyncram_rgn1                               ; work         ;
;                               |cntr_hgb:rd_ptr_msb|                                                                                     ; 5 (5)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated|a_dpfifo_b071:dpfifo|cntr_hgb:rd_ptr_msb                                                                                                                                            ; cntr_hgb                                      ; work         ;
;                               |cntr_igb:wr_ptr|                                                                                         ; 6 (6)               ; 5 (5)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated|a_dpfifo_b071:dpfifo|cntr_igb:wr_ptr                                                                                                                                                ; cntr_igb                                      ; work         ;
;                               |cntr_ug7:usedw_counter|                                                                                  ; 5 (5)               ; 5 (5)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated|a_dpfifo_b071:dpfifo|cntr_ug7:usedw_counter                                                                                                                                         ; cntr_ug7                                      ; work         ;
;                |write_master:write_mstr_internal|                                                                                       ; 154 (101)           ; 79 (51)                   ; 1312              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal                                                                                                                                                                                                                                                                         ; write_master                                  ; nios2        ;
;                   |ST_to_MM_Adapter:the_ST_to_MM_Adapter|                                                                               ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|ST_to_MM_Adapter:the_ST_to_MM_Adapter                                                                                                                                                                                                                                   ; ST_to_MM_Adapter                              ; nios2        ;
;                   |byte_enable_generator:the_byte_enable_generator|                                                                     ; 8 (0)               ; 1 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|byte_enable_generator:the_byte_enable_generator                                                                                                                                                                                                                         ; byte_enable_generator                         ; nios2        ;
;                      |thirty_two_bit_byteenable_FSM:the_thirty_two_bit_byteenable_FSM|                                                  ; 8 (5)               ; 1 (1)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|byte_enable_generator:the_byte_enable_generator|thirty_two_bit_byteenable_FSM:the_thirty_two_bit_byteenable_FSM                                                                                                                                                         ; thirty_two_bit_byteenable_FSM                 ; nios2        ;
;                         |sixteen_bit_byteenable_FSM:lower_sixteen_bit_byteenable_FSM|                                                   ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|byte_enable_generator:the_byte_enable_generator|thirty_two_bit_byteenable_FSM:the_thirty_two_bit_byteenable_FSM|sixteen_bit_byteenable_FSM:lower_sixteen_bit_byteenable_FSM                                                                                             ; sixteen_bit_byteenable_FSM                    ; nios2        ;
;                         |sixteen_bit_byteenable_FSM:upper_sixteen_bit_byteenable_FSM|                                                   ; 2 (2)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|byte_enable_generator:the_byte_enable_generator|thirty_two_bit_byteenable_FSM:the_thirty_two_bit_byteenable_FSM|sixteen_bit_byteenable_FSM:upper_sixteen_bit_byteenable_FSM                                                                                             ; sixteen_bit_byteenable_FSM                    ; nios2        ;
;                   |scfifo:the_st_to_master_fifo|                                                                                        ; 41 (0)              ; 27 (0)                    ; 1312              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo                                                                                                                                                                                                                                            ; scfifo                                        ; work         ;
;                      |scfifo_p871:auto_generated|                                                                                       ; 41 (0)              ; 27 (0)                    ; 1312              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo|scfifo_p871:auto_generated                                                                                                                                                                                                                 ; scfifo_p871                                   ; work         ;
;                         |a_dpfifo_c071:dpfifo|                                                                                          ; 41 (24)             ; 27 (13)                   ; 1312              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo|scfifo_p871:auto_generated|a_dpfifo_c071:dpfifo                                                                                                                                                                                            ; a_dpfifo_c071                                 ; work         ;
;                            |altsyncram_tgn1:FIFOram|                                                                                    ; 0 (0)               ; 0 (0)                     ; 1312              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo|scfifo_p871:auto_generated|a_dpfifo_c071:dpfifo|altsyncram_tgn1:FIFOram                                                                                                                                                                    ; altsyncram_tgn1                               ; work         ;
;                            |cntr_hgb:rd_ptr_msb|                                                                                        ; 5 (5)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo|scfifo_p871:auto_generated|a_dpfifo_c071:dpfifo|cntr_hgb:rd_ptr_msb                                                                                                                                                                        ; cntr_hgb                                      ; work         ;
;                            |cntr_igb:wr_ptr|                                                                                            ; 6 (6)               ; 5 (5)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo|scfifo_p871:auto_generated|a_dpfifo_c071:dpfifo|cntr_igb:wr_ptr                                                                                                                                                                            ; cntr_igb                                      ; work         ;
;                            |cntr_ug7:usedw_counter|                                                                                     ; 6 (6)               ; 5 (5)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo|scfifo_p871:auto_generated|a_dpfifo_c071:dpfifo|cntr_ug7:usedw_counter                                                                                                                                                                     ; cntr_ug7                                      ; work         ;
;             |nios2_enet_tx_msgdma:enet_tx_msgdma|                                                                                       ; 154 (0)             ; 89 (0)                    ; 1648              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma                                                                                                                                                                                                                                                                                                          ; nios2_enet_tx_msgdma                          ; nios2        ;
;                |dispatcher:dispatcher_internal|                                                                                         ; 35 (0)              ; 21 (0)                    ; 464               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal                                                                                                                                                                                                                                                                           ; dispatcher                                    ; nios2        ;
;                   |csr_block:the_csr_block|                                                                                             ; 7 (7)               ; 5 (5)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block                                                                                                                                                                                                                                                   ; csr_block                                     ; nios2        ;
;                   |descriptor_buffers:the_descriptor_buffers|                                                                           ; 28 (3)              ; 16 (3)                    ; 464               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers                                                                                                                                                                                                                                 ; descriptor_buffers                            ; nios2        ;
;                      |fifo_with_byteenables:the_read_command_FIFO|                                                                      ; 25 (25)             ; 13 (13)                   ; 464               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO                                                                                                                                                                                     ; fifo_with_byteenables                         ; nios2        ;
;                         |altsyncram:the_dp_ram|                                                                                         ; 0 (0)               ; 0 (0)                     ; 464               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram                                                                                                                                                               ; altsyncram                                    ; work         ;
;                            |altsyncram_p5j1:auto_generated|                                                                             ; 0 (0)               ; 0 (0)                     ; 464               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated                                                                                                                                ; altsyncram_p5j1                               ; work         ;
;                |read_master:read_mstr_internal|                                                                                         ; 119 (76)            ; 68 (38)                   ; 1184              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal                                                                                                                                                                                                                                                                           ; read_master                                   ; nios2        ;
;                   |MM_to_ST_Adapter:the_MM_to_ST_adapter|                                                                               ; 2 (2)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|MM_to_ST_Adapter:the_MM_to_ST_adapter                                                                                                                                                                                                                                     ; MM_to_ST_Adapter                              ; nios2        ;
;                   |scfifo:the_master_to_st_fifo|                                                                                        ; 41 (0)              ; 27 (0)                    ; 1184              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo                                                                                                                                                                                                                                              ; scfifo                                        ; work         ;
;                      |scfifo_s871:auto_generated|                                                                                       ; 41 (0)              ; 27 (0)                    ; 1184              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated                                                                                                                                                                                                                   ; scfifo_s871                                   ; work         ;
;                         |a_dpfifo_f071:dpfifo|                                                                                          ; 41 (25)             ; 27 (13)                   ; 1184              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo                                                                                                                                                                                              ; a_dpfifo_f071                                 ; work         ;
;                            |altsyncram_3hn1:FIFOram|                                                                                    ; 0 (0)               ; 0 (0)                     ; 1184              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo|altsyncram_3hn1:FIFOram                                                                                                                                                                      ; altsyncram_3hn1                               ; work         ;
;                            |cntr_hgb:rd_ptr_msb|                                                                                        ; 5 (5)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo|cntr_hgb:rd_ptr_msb                                                                                                                                                                          ; cntr_hgb                                      ; work         ;
;                            |cntr_igb:wr_ptr|                                                                                            ; 6 (6)               ; 5 (5)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo|cntr_igb:wr_ptr                                                                                                                                                                              ; cntr_igb                                      ; work         ;
;                            |cntr_ug7:usedw_counter|                                                                                     ; 5 (5)               ; 5 (5)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo|cntr_ug7:usedw_counter                                                                                                                                                                       ; cntr_ug7                                      ; work         ;
;             |nios2_enet_udp_dpram:enet_udp_dpram|                                                                                       ; 0 (0)               ; 0 (0)                     ; 32768             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram                                                                                                                                                                                                                                                                                                          ; nios2_enet_udp_dpram                          ; nios2        ;
;                |altsyncram:the_altsyncram|                                                                                              ; 0 (0)               ; 0 (0)                     ; 32768             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram|altsyncram:the_altsyncram                                                                                                                                                                                                                                                                                ; altsyncram                                    ; work         ;
;                   |altsyncram_dc72:auto_generated|                                                                                      ; 0 (0)               ; 0 (0)                     ; 32768             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram|altsyncram:the_altsyncram|altsyncram_dc72:auto_generated                                                                                                                                                                                                                                                 ; altsyncram_dc72                               ; work         ;
;             |nios2_eth_tse_mac:eth_tse_mac|                                                                                             ; 1348 (0)            ; 2263 (0)                  ; 227776            ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac                                                                                                                                                                                                                                                                                                                ; nios2_eth_tse_mac                             ; nios2        ;
;                |altera_eth_tse_mac:i_tse_mac|                                                                                           ; 1348 (1)            ; 2263 (1)                  ; 227776            ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac                                                                                                                                                                                                                                                                                   ; altera_eth_tse_mac                            ; nios2        ;
;                   |altera_tse_mac_control:U_MAC_CONTROL|                                                                                ; 240 (0)             ; 342 (0)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL                                                                                                                                                                                                                                              ; altera_tse_mac_control                        ; nios2        ;
;                      |altera_tse_host_control:U_CTRL|                                                                                   ; 31 (31)             ; 27 (21)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL                                                                                                                                                                                                               ; altera_tse_host_control                       ; nios2        ;
;                         |altera_eth_tse_std_synchronizer:U_SYNC_1|                                                                      ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|altera_eth_tse_std_synchronizer:U_SYNC_1                                                                                                                                                                      ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                            |altera_std_synchronizer_nocut:std_sync_no_cut|                                                              ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                                                        ; altera_std_synchronizer_nocut                 ; nios2        ;
;                         |altera_eth_tse_std_synchronizer:U_SYNC_2|                                                                      ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|altera_eth_tse_std_synchronizer:U_SYNC_2                                                                                                                                                                      ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                            |altera_std_synchronizer_nocut:std_sync_no_cut|                                                              ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                                                        ; altera_std_synchronizer_nocut                 ; nios2        ;
;                      |altera_tse_register_map:U_REG|                                                                                    ; 209 (204)           ; 315 (298)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG                                                                                                                                                                                                                ; altera_tse_register_map                       ; nios2        ;
;                         |altera_eth_tse_std_synchronizer:U_MAGIC_DETECT|                                                                ; 1 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_MAGIC_DETECT                                                                                                                                                                 ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                            |altera_std_synchronizer_nocut:std_sync_no_cut|                                                              ; 1 (1)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_MAGIC_DETECT|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                                                   ; altera_std_synchronizer_nocut                 ; nios2        ;
;                         |altera_eth_tse_std_synchronizer:U_SYNC_2|                                                                      ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_SYNC_2                                                                                                                                                                       ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                            |altera_std_synchronizer_nocut:std_sync_no_cut|                                                              ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                                                         ; altera_std_synchronizer_nocut                 ; nios2        ;
;                         |altera_eth_tse_std_synchronizer:U_SYNC_5|                                                                      ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_SYNC_5                                                                                                                                                                       ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                            |altera_std_synchronizer_nocut:std_sync_no_cut|                                                              ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_SYNC_5|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                                                         ; altera_std_synchronizer_nocut                 ; nios2        ;
;                         |altera_tse_clock_crosser:U_EXCESS_COL|                                                                         ; 2 (1)               ; 4 (1)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL                                                                                                                                                                          ; altera_tse_clock_crosser                      ; nios2        ;
;                            |altera_eth_tse_std_synchronizer:in_to_out_synchronizer|                                                     ; 1 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|altera_eth_tse_std_synchronizer:in_to_out_synchronizer                                                                                                                   ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                               |altera_std_synchronizer_nocut:std_sync_no_cut|                                                           ; 1 (1)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut                                                                     ; altera_std_synchronizer_nocut                 ; nios2        ;
;                         |altera_tse_clock_crosser:U_LATE_COL|                                                                           ; 2 (1)               ; 4 (1)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL                                                                                                                                                                            ; altera_tse_clock_crosser                      ; nios2        ;
;                            |altera_eth_tse_std_synchronizer:in_to_out_synchronizer|                                                     ; 1 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|altera_eth_tse_std_synchronizer:in_to_out_synchronizer                                                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                               |altera_std_synchronizer_nocut:std_sync_no_cut|                                                           ; 1 (1)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut                                                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                   |altera_tse_reset_synchronizer:reset_sync_0|                                                                          ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_0                                                                                                                                                                                                                                        ; altera_tse_reset_synchronizer                 ; nios2        ;
;                   |altera_tse_reset_synchronizer:reset_sync_1|                                                                          ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_1                                                                                                                                                                                                                                        ; altera_tse_reset_synchronizer                 ; nios2        ;
;                   |altera_tse_reset_synchronizer:reset_sync_2|                                                                          ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_2                                                                                                                                                                                                                                        ; altera_tse_reset_synchronizer                 ; nios2        ;
;                   |altera_tse_reset_synchronizer:reset_sync_3|                                                                          ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_3                                                                                                                                                                                                                                        ; altera_tse_reset_synchronizer                 ; nios2        ;
;                   |altera_tse_reset_synchronizer:reset_sync_4|                                                                          ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_4                                                                                                                                                                                                                                        ; altera_tse_reset_synchronizer                 ; nios2        ;
;                   |altera_tse_rgmii_module:U_RGMII|                                                                                     ; 11 (11)             ; 18 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII                                                                                                                                                                                                                                                   ; altera_tse_rgmii_module                       ; nios2        ;
;                      |altera_eth_tse_std_synchronizer:U_SYNC_2|                                                                         ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_eth_tse_std_synchronizer:U_SYNC_2                                                                                                                                                                                                          ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                         |altera_std_synchronizer_nocut:std_sync_no_cut|                                                                 ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                                                                                            ; altera_std_synchronizer_nocut                 ; nios2        ;
;                      |altera_tse_rgmii_in1:the_rgmii_in1|                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in1:the_rgmii_in1                                                                                                                                                                                                                ; altera_tse_rgmii_in1                          ; nios2        ;
;                         |altddio_in:altddio_in_component|                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in1:the_rgmii_in1|altddio_in:altddio_in_component                                                                                                                                                                                ; altddio_in                                    ; work         ;
;                            |ddio_in_gsd:auto_generated|                                                                                 ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in1:the_rgmii_in1|altddio_in:altddio_in_component|ddio_in_gsd:auto_generated                                                                                                                                                     ; ddio_in_gsd                                   ; work         ;
;                      |altera_tse_rgmii_in4:the_rgmii_in4|                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in4:the_rgmii_in4                                                                                                                                                                                                                ; altera_tse_rgmii_in4                          ; nios2        ;
;                         |altddio_in:altddio_in_component|                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in4:the_rgmii_in4|altddio_in:altddio_in_component                                                                                                                                                                                ; altddio_in                                    ; work         ;
;                            |ddio_in_jsd:auto_generated|                                                                                 ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in4:the_rgmii_in4|altddio_in:altddio_in_component|ddio_in_jsd:auto_generated                                                                                                                                                     ; ddio_in_jsd                                   ; work         ;
;                      |altera_tse_rgmii_out1:the_rgmii_out1|                                                                             ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_out1:the_rgmii_out1                                                                                                                                                                                                              ; altera_tse_rgmii_out1                         ; nios2        ;
;                         |altddio_out:altddio_out_component|                                                                             ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_out1:the_rgmii_out1|altddio_out:altddio_out_component                                                                                                                                                                            ; altddio_out                                   ; work         ;
;                            |ddio_out_ghb:auto_generated|                                                                                ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_out1:the_rgmii_out1|altddio_out:altddio_out_component|ddio_out_ghb:auto_generated                                                                                                                                                ; ddio_out_ghb                                  ; work         ;
;                      |altera_tse_rgmii_out4:the_rgmii_out4|                                                                             ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_out4:the_rgmii_out4                                                                                                                                                                                                              ; altera_tse_rgmii_out4                         ; nios2        ;
;                         |altddio_out:altddio_out_component|                                                                             ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_out4:the_rgmii_out4|altddio_out:altddio_out_component                                                                                                                                                                            ; altddio_out                                   ; work         ;
;                            |ddio_out_jhb:auto_generated|                                                                                ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_out4:the_rgmii_out4|altddio_out:altddio_out_component|ddio_out_jhb:auto_generated                                                                                                                                                ; ddio_out_jhb                                  ; work         ;
;                   |altera_tse_top_mdio:U_MDIO|                                                                                          ; 82 (1)              ; 152 (36)                  ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO                                                                                                                                                                                                                                                        ; altera_tse_top_mdio                           ; nios2        ;
;                      |altera_tse_mdio:U_MDIO|                                                                                           ; 38 (38)             ; 71 (71)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio:U_MDIO                                                                                                                                                                                                                                 ; altera_tse_mdio                               ; nios2        ;
;                      |altera_tse_mdio_clk_gen:U_CLKGEN|                                                                                 ; 12 (12)             ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_clk_gen:U_CLKGEN                                                                                                                                                                                                                       ; altera_tse_mdio_clk_gen                       ; nios2        ;
;                      |altera_tse_mdio_cntl:U_CNTL|                                                                                      ; 31 (31)             ; 35 (35)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_cntl:U_CNTL                                                                                                                                                                                                                            ; altera_tse_mdio_cntl                          ; nios2        ;
;                   |altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|                                                                         ; 1014 (0)            ; 1735 (0)                  ; 227776            ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP                                                                                                                                                                                                                                       ; altera_tse_top_w_fifo_10_100_1000             ; nios2        ;
;                      |altera_eth_tse_std_synchronizer:U_SYNC_1|                                                                         ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_eth_tse_std_synchronizer:U_SYNC_1                                                                                                                                                                                              ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                         |altera_std_synchronizer_nocut:std_sync_no_cut|                                                                 ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                                                                                ; altera_std_synchronizer_nocut                 ; nios2        ;
;                      |altera_eth_tse_std_synchronizer:U_SYNC_2|                                                                         ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_eth_tse_std_synchronizer:U_SYNC_2                                                                                                                                                                                              ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                         |altera_std_synchronizer_nocut:std_sync_no_cut|                                                                 ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                                                                                ; altera_std_synchronizer_nocut                 ; nios2        ;
;                      |altera_tse_clk_cntl:U_CLKCT|                                                                                      ; 3 (3)               ; 9 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT                                                                                                                                                                                                           ; altera_tse_clk_cntl                           ; nios2        ;
;                         |altera_eth_tse_std_synchronizer:U_SYNC_RX_ETH_MODE|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT|altera_eth_tse_std_synchronizer:U_SYNC_RX_ETH_MODE                                                                                                                                                        ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                            |altera_std_synchronizer_nocut:std_sync_no_cut|                                                              ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT|altera_eth_tse_std_synchronizer:U_SYNC_RX_ETH_MODE|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                                          ; altera_std_synchronizer_nocut                 ; nios2        ;
;                         |altera_eth_tse_std_synchronizer:U_SYNC_TX_ETH_MODE|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT|altera_eth_tse_std_synchronizer:U_SYNC_TX_ETH_MODE                                                                                                                                                        ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                            |altera_std_synchronizer_nocut:std_sync_no_cut|                                                              ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT|altera_eth_tse_std_synchronizer:U_SYNC_TX_ETH_MODE|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                                          ; altera_std_synchronizer_nocut                 ; nios2        ;
;                      |altera_tse_gmii_io:U_GMIF|                                                                                        ; 0 (0)               ; 23 (20)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_gmii_io:U_GMIF                                                                                                                                                                                                             ; altera_tse_gmii_io                            ; nios2        ;
;                         |altera_eth_tse_std_synchronizer:U_SYNC_1|                                                                      ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_gmii_io:U_GMIF|altera_eth_tse_std_synchronizer:U_SYNC_1                                                                                                                                                                    ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                            |altera_std_synchronizer_nocut:std_sync_no_cut|                                                              ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_gmii_io:U_GMIF|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                                                      ; altera_std_synchronizer_nocut                 ; nios2        ;
;                      |altera_tse_loopback_ff:U_LBFF|                                                                                    ; 60 (11)             ; 102 (20)                  ; 320               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF                                                                                                                                                                                                         ; altera_tse_loopback_ff                        ; nios2        ;
;                         |altera_eth_tse_std_synchronizer:U_SYNC_1|                                                                      ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_eth_tse_std_synchronizer:U_SYNC_1                                                                                                                                                                ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                            |altera_std_synchronizer_nocut:std_sync_no_cut|                                                              ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                                                  ; altera_std_synchronizer_nocut                 ; nios2        ;
;                         |altera_tse_a_fifo_24:U_LBFF|                                                                                   ; 40 (21)             ; 68 (18)                   ; 320               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF                                                                                                                                                                             ; altera_tse_a_fifo_24                          ; nios2        ;
;                            |altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|                                                     ; 0 (0)               ; 10 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR                                                                                                                      ; altera_eth_tse_std_synchronizer_bundle        ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[0].u|                                                               ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[0].u                                                                            ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut                              ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[1].u|                                                               ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[1].u                                                                            ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut                              ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[2].u|                                                               ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[2].u                                                                            ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut                              ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[3].u|                                                               ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[3].u                                                                            ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut                              ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[4].u|                                                               ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[4].u                                                                            ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut                              ; altera_std_synchronizer_nocut                 ; nios2        ;
;                            |altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|                                                     ; 0 (0)               ; 10 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR                                                                                                                      ; altera_eth_tse_std_synchronizer_bundle        ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[0].u|                                                               ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[0].u                                                                            ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut                              ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[1].u|                                                               ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[1].u                                                                            ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut                              ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[2].u|                                                               ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[2].u                                                                            ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut                              ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[3].u|                                                               ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[3].u                                                                            ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut                              ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[4].u|                                                               ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[4].u                                                                            ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut                              ; altera_std_synchronizer_nocut                 ; nios2        ;
;                            |altera_tse_gray_cnt:U_RD|                                                                                   ; 10 (10)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD                                                                                                                                                    ; altera_tse_gray_cnt                           ; nios2        ;
;                            |altera_tse_gray_cnt:U_WRT|                                                                                  ; 9 (9)               ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT                                                                                                                                                   ; altera_tse_gray_cnt                           ; nios2        ;
;                            |altera_tse_sdpm_altsyncram:U_RAM|                                                                           ; 0 (0)               ; 0 (0)                     ; 320               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_sdpm_altsyncram:U_RAM                                                                                                                                            ; altera_tse_sdpm_altsyncram                    ; nios2        ;
;                               |altsyncram:altsyncram_component|                                                                         ; 0 (0)               ; 0 (0)                     ; 320               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_sdpm_altsyncram:U_RAM|altsyncram:altsyncram_component                                                                                                            ; altsyncram                                    ; work         ;
;                                  |altsyncram_2vl1:auto_generated|                                                                       ; 0 (0)               ; 0 (0)                     ; 320               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_sdpm_altsyncram:U_RAM|altsyncram:altsyncram_component|altsyncram_2vl1:auto_generated                                                                             ; altsyncram_2vl1                               ; work         ;
;                         |altera_tse_lb_read_cntl:U_LBR|                                                                                 ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_read_cntl:U_LBR                                                                                                                                                                           ; altera_tse_lb_read_cntl                       ; nios2        ;
;                         |altera_tse_lb_wrt_cntl:U_LBW|                                                                                  ; 5 (5)               ; 7 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_wrt_cntl:U_LBW                                                                                                                                                                            ; altera_tse_lb_wrt_cntl                        ; nios2        ;
;                            |altera_eth_tse_std_synchronizer:U_SYNC_LOOPBACK_ENA|                                                        ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_wrt_cntl:U_LBW|altera_eth_tse_std_synchronizer:U_SYNC_LOOPBACK_ENA                                                                                                                        ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                               |altera_std_synchronizer_nocut:std_sync_no_cut|                                                           ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_wrt_cntl:U_LBW|altera_eth_tse_std_synchronizer:U_SYNC_LOOPBACK_ENA|altera_std_synchronizer_nocut:std_sync_no_cut                                                                          ; altera_std_synchronizer_nocut                 ; nios2        ;
;                      |altera_tse_mii_rx_if:U_MRX|                                                                                       ; 16 (16)             ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_rx_if:U_MRX                                                                                                                                                                                                            ; altera_tse_mii_rx_if                          ; nios2        ;
;                      |altera_tse_mii_tx_if:U_MTX|                                                                                       ; 7 (7)               ; 10 (7)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_tx_if:U_MTX                                                                                                                                                                                                            ; altera_tse_mii_tx_if                          ; nios2        ;
;                         |altera_eth_tse_std_synchronizer:U_SYNC_1|                                                                      ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_tx_if:U_MTX|altera_eth_tse_std_synchronizer:U_SYNC_1                                                                                                                                                                   ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                            |altera_std_synchronizer_nocut:std_sync_no_cut|                                                              ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_tx_if:U_MTX|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                                                     ; altera_std_synchronizer_nocut                 ; nios2        ;
;                      |altera_tse_top_w_fifo:U_MAC|                                                                                      ; 928 (0)             ; 1561 (0)                  ; 227456            ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC                                                                                                                                                                                                           ; altera_tse_top_w_fifo                         ; nios2        ;
;                         |altera_tse_rx_min_ff:U_RXFF|                                                                                   ; 291 (91)            ; 479 (73)                  ; 152576            ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF                                                                                                                                                                               ; altera_tse_rx_min_ff                          ; nios2        ;
;                            |altera_eth_tse_std_synchronizer:U_SYNC_1|                                                                   ; 1 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_1                                                                                                                                      ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                               |altera_std_synchronizer_nocut:std_sync_no_cut|                                                           ; 1 (1)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                        ; altera_std_synchronizer_nocut                 ; nios2        ;
;                            |altera_eth_tse_std_synchronizer:U_SYNC_4|                                                                   ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_4                                                                                                                                      ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                               |altera_std_synchronizer_nocut:std_sync_no_cut|                                                           ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_4|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                        ; altera_std_synchronizer_nocut                 ; nios2        ;
;                            |altera_eth_tse_std_synchronizer:U_SYNC_5|                                                                   ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_5                                                                                                                                      ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                               |altera_std_synchronizer_nocut:std_sync_no_cut|                                                           ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_5|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                        ; altera_std_synchronizer_nocut                 ; nios2        ;
;                            |altera_eth_tse_std_synchronizer:U_SYNC_6|                                                                   ; 1 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_6                                                                                                                                      ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                               |altera_std_synchronizer_nocut:std_sync_no_cut|                                                           ; 1 (1)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_6|altera_std_synchronizer_nocut:std_sync_no_cut                                                                                        ; altera_std_synchronizer_nocut                 ; nios2        ;
;                            |altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|                                                            ; 0 (0)               ; 36 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2                                                                                                                               ; altera_eth_tse_std_synchronizer_bundle        ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[0].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[10].u|                                                              ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[10].u                                                                                    ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut                                      ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[11].u|                                                              ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[11].u                                                                                    ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut                                      ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[1].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[2].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[3].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[4].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[5].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[6].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[7].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[8].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[9].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[9].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                            |altera_tse_a_fifo_34:RX_STATUS|                                                                             ; 61 (22)             ; 91 (21)                   ; 5120              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS                                                                                                                                                ; altera_tse_a_fifo_34                          ; nios2        ;
;                               |altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|                                                  ; 0 (0)               ; 20 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR                                                                                         ; altera_eth_tse_std_synchronizer_bundle        ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[0].u|                                                            ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[0].u                                               ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[1].u|                                                            ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[1].u                                               ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[2].u|                                                            ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[2].u                                               ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[3].u|                                                            ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[3].u                                               ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[4].u|                                                            ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[4].u                                               ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[5].u|                                                            ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[5].u                                               ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[6].u|                                                            ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[6].u                                               ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[7].u|                                                            ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[7].u                                               ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[8].u|                                                            ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[8].u                                               ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[9].u|                                                            ; 0 (0)               ; 2 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[9].u                                               ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_tse_altsyncram_dpm_fifo:U_RAM|                                                                    ; 0 (0)               ; 0 (0)                     ; 5120              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM                                                                                                           ; altera_tse_altsyncram_dpm_fifo                ; nios2        ;
;                                  |altsyncram:altsyncram_component|                                                                      ; 0 (0)               ; 0 (0)                     ; 5120              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component                                                                           ; altsyncram                                    ; work         ;
;                                     |altsyncram_b9o1:auto_generated|                                                                    ; 0 (0)               ; 0 (0)                     ; 5120              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated                                            ; altsyncram_b9o1                               ; work         ;
;                               |altera_tse_bin_cnt:U_RD|                                                                                 ; 15 (15)             ; 20 (20)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_bin_cnt:U_RD                                                                                                                        ; altera_tse_bin_cnt                            ; nios2        ;
;                               |altera_tse_gray_cnt:U_WRT|                                                                               ; 24 (24)             ; 30 (30)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT                                                                                                                      ; altera_tse_gray_cnt                           ; nios2        ;
;                            |altera_tse_a_fifo_opt_1246:RX_DATA|                                                                         ; 137 (81)            ; 267 (51)                  ; 147456            ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA                                                                                                                                            ; altera_tse_a_fifo_opt_1246                    ; nios2        ;
;                               |altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|                                                         ; 0 (0)               ; 36 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1                                                                                            ; altera_eth_tse_std_synchronizer_bundle        ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[0].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[0].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[10].u|                                                           ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[10].u                                                 ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut   ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[11].u|                                                           ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[11].u                                                 ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut   ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[1].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[1].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[2].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[2].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[3].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[3].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[4].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[4].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[5].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[5].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[6].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[6].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[7].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[7].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[8].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[8].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[9].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[9].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|                                                         ; 0 (0)               ; 36 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2                                                                                            ; altera_eth_tse_std_synchronizer_bundle        ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[0].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[10].u|                                                           ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[10].u                                                 ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut   ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[11].u|                                                           ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[11].u                                                 ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut   ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[1].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[2].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[3].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[4].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[5].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[6].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[7].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[8].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[9].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[9].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|                                                         ; 0 (0)               ; 36 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3                                                                                            ; altera_eth_tse_std_synchronizer_bundle        ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[0].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[0].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[10].u|                                                           ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[10].u                                                 ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut   ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[11].u|                                                           ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[11].u                                                 ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut   ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[1].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[1].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[2].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[2].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[3].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[3].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[4].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[4].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[5].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[5].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[6].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[6].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[7].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[7].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[8].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[8].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[9].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[9].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|                                                         ; 0 (0)               ; 36 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4                                                                                            ; altera_eth_tse_std_synchronizer_bundle        ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[0].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[0].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[10].u|                                                           ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[10].u                                                 ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut   ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[11].u|                                                           ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[11].u                                                 ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut   ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[1].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[1].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[2].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[2].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[3].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[3].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[4].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[4].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[5].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[5].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[6].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[6].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[7].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[7].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[8].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[8].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[9].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[9].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_tse_altsyncram_dpm_fifo:U_RAM|                                                                    ; 0 (0)               ; 0 (0)                     ; 147456            ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM                                                                                                       ; altera_tse_altsyncram_dpm_fifo                ; nios2        ;
;                                  |altsyncram:altsyncram_component|                                                                      ; 0 (0)               ; 0 (0)                     ; 147456            ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component                                                                       ; altsyncram                                    ; work         ;
;                                     |altsyncram_5ao1:auto_generated|                                                                    ; 0 (0)               ; 0 (0)                     ; 147456            ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_5ao1:auto_generated                                        ; altsyncram_5ao1                               ; work         ;
;                               |altera_tse_gray_cnt:U_RD|                                                                                ; 28 (28)             ; 36 (36)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD                                                                                                                   ; altera_tse_gray_cnt                           ; nios2        ;
;                               |altera_tse_gray_cnt:U_WRT|                                                                               ; 28 (28)             ; 36 (36)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT                                                                                                                  ; altera_tse_gray_cnt                           ; nios2        ;
;                         |altera_tse_top_1geth:U_GETH|                                                                                   ; 386 (0)             ; 634 (0)                   ; 128               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH                                                                                                                                                                               ; altera_tse_top_1geth                          ; nios2        ;
;                            |altera_tse_mac_rx:U_RX|                                                                                     ; 209 (157)           ; 377 (315)                 ; 128               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX                                                                                                                                                        ; altera_tse_mac_rx                             ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:U_SYNC_11|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_11                                                                                                              ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_11|altera_std_synchronizer_nocut:std_sync_no_cut                                                                ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:U_SYNC_4|                                                                ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_4                                                                                                               ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_4|altera_std_synchronizer_nocut:std_sync_no_cut                                                                 ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:U_SYNC_6|                                                                ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_6                                                                                                               ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_6|altera_std_synchronizer_nocut:std_sync_no_cut                                                                 ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:U_SYNC_7|                                                                ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_7                                                                                                               ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_7|altera_std_synchronizer_nocut:std_sync_no_cut                                                                 ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:U_SYNC_9|                                                                ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_9                                                                                                               ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_9|altera_std_synchronizer_nocut:std_sync_no_cut                                                                 ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:U_SYNC_PAD_ENA|                                                          ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_PAD_ENA                                                                                                         ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_PAD_ENA|altera_std_synchronizer_nocut:std_sync_no_cut                                                           ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_tse_altshifttaps:U_SHIFTTAPS|                                                                     ; 10 (0)              ; 8 (0)                     ; 128               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_altshifttaps:U_SHIFTTAPS                                                                                                                    ; altera_tse_altshifttaps                       ; nios2        ;
;                                  |altshift_taps:shift_reg_rtl_0|                                                                        ; 10 (0)              ; 8 (0)                     ; 128               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_altshifttaps:U_SHIFTTAPS|altshift_taps:shift_reg_rtl_0                                                                                      ; altshift_taps                                 ; work         ;
;                                     |shift_taps_ffv:auto_generated|                                                                     ; 10 (6)              ; 8 (4)                     ; 128               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_altshifttaps:U_SHIFTTAPS|altshift_taps:shift_reg_rtl_0|shift_taps_ffv:auto_generated                                                        ; shift_taps_ffv                                ; work         ;
;                                        |altsyncram_1r91:altsyncram4|                                                                    ; 0 (0)               ; 0 (0)                     ; 128               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_altshifttaps:U_SHIFTTAPS|altshift_taps:shift_reg_rtl_0|shift_taps_ffv:auto_generated|altsyncram_1r91:altsyncram4                            ; altsyncram_1r91                               ; work         ;
;                                        |cntr_eif:cntr1|                                                                                 ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_altshifttaps:U_SHIFTTAPS|altshift_taps:shift_reg_rtl_0|shift_taps_ffv:auto_generated|cntr_eif:cntr1                                         ; cntr_eif                                      ; work         ;
;                               |altera_tse_crc328checker:U_CRC|                                                                          ; 42 (7)              ; 36 (4)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_crc328checker:U_CRC                                                                                                                         ; altera_tse_crc328checker                      ; nios2        ;
;                                  |altera_tse_crc32galois8:U_GALS|                                                                       ; 35 (35)             ; 32 (32)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_crc328checker:U_CRC|altera_tse_crc32galois8:U_GALS                                                                                          ; altera_tse_crc32galois8                       ; nios2        ;
;                            |altera_tse_mac_tx:U_TX|                                                                                     ; 177 (110)           ; 257 (201)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX                                                                                                                                                        ; altera_tse_mac_tx                             ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:U_SYNC_1|                                                                ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer:U_SYNC_1                                                                                                               ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut                                                                 ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:U_SYNC_2|                                                                ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer:U_SYNC_2                                                                                                               ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut                                                                 ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|                                                         ; 0 (0)               ; 15 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3                                                                                                        ; altera_eth_tse_std_synchronizer_bundle        ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[0].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[0].u                                                              ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut                ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[1].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[1].u                                                              ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut                ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[2].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[2].u                                                              ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut                ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[3].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[3].u                                                              ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut                ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[4].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[4].u                                                              ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut                ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_tse_crc328generator:U_CRC|                                                                        ; 67 (0)              ; 35 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC                                                                                                                       ; altera_tse_crc328generator                    ; nios2        ;
;                                  |altera_tse_crc32ctl8:U_CTL|                                                                           ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|altera_tse_crc32ctl8:U_CTL                                                                                            ; altera_tse_crc32ctl8                          ; nios2        ;
;                                  |altera_tse_crc32galois8:U_GALS|                                                                       ; 67 (67)             ; 32 (32)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|altera_tse_crc32galois8:U_GALS                                                                                        ; altera_tse_crc32galois8                       ; nios2        ;
;                         |altera_tse_tx_min_ff:U_TXFF|                                                                                   ; 251 (62)            ; 448 (81)                  ; 74752             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF                                                                                                                                                                               ; altera_tse_tx_min_ff                          ; nios2        ;
;                            |altera_eth_tse_std_synchronizer:U_SYNC_TX_SHIFT16|                                                          ; 1 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer:U_SYNC_TX_SHIFT16                                                                                                                             ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                               |altera_std_synchronizer_nocut:std_sync_no_cut|                                                           ; 1 (1)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer:U_SYNC_TX_SHIFT16|altera_std_synchronizer_nocut:std_sync_no_cut                                                                               ; altera_std_synchronizer_nocut                 ; nios2        ;
;                            |altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|                                                            ; 0 (0)               ; 33 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1                                                                                                                               ; altera_eth_tse_std_synchronizer_bundle        ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[0].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[0].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[10].u|                                                              ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[10].u                                                                                    ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut                                      ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[1].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[1].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[2].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[2].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[3].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[3].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[4].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[4].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[5].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[5].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[6].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[6].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[7].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[7].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[8].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[8].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer:sync[9].u|                                                               ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[9].u                                                                                     ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                  |altera_std_synchronizer_nocut:std_sync_no_cut|                                                        ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut                                       ; altera_std_synchronizer_nocut                 ; nios2        ;
;                            |altera_tse_a_fifo_13:TX_STATUS|                                                                             ; 53 (19)             ; 83 (11)                   ; 1024              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS                                                                                                                                                ; altera_tse_a_fifo_13                          ; nios2        ;
;                               |altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|                                                         ; 0 (0)               ; 27 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2                                                                                                ; altera_eth_tse_std_synchronizer_bundle        ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[0].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u                                                      ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut        ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[1].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u                                                      ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut        ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[2].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u                                                      ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut        ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[3].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u                                                      ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut        ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[4].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u                                                      ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut        ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[5].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u                                                      ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut        ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[6].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u                                                      ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut        ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[7].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u                                                      ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut        ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[8].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u                                                      ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut        ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_tse_altsyncram_dpm_fifo:U_RAM|                                                                    ; 0 (0)               ; 0 (0)                     ; 1024              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM                                                                                                           ; altera_tse_altsyncram_dpm_fifo                ; nios2        ;
;                                  |altsyncram:altsyncram_component|                                                                      ; 0 (0)               ; 0 (0)                     ; 1024              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component                                                                           ; altsyncram                                    ; work         ;
;                                     |altsyncram_n0o1:auto_generated|                                                                    ; 0 (0)               ; 0 (0)                     ; 1024              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_n0o1:auto_generated                                            ; altsyncram_n0o1                               ; work         ;
;                               |altera_tse_gray_cnt:U_RD|                                                                                ; 13 (13)             ; 18 (18)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_RD                                                                                                                       ; altera_tse_gray_cnt                           ; nios2        ;
;                               |altera_tse_gray_cnt:U_WRT|                                                                               ; 21 (21)             ; 27 (27)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT                                                                                                                      ; altera_tse_gray_cnt                           ; nios2        ;
;                            |altera_tse_a_fifo_opt_1246:TX_DATA|                                                                         ; 135 (83)            ; 248 (50)                  ; 73728             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA                                                                                                                                            ; altera_tse_a_fifo_opt_1246                    ; nios2        ;
;                               |altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|                                                         ; 0 (0)               ; 33 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1                                                                                            ; altera_eth_tse_std_synchronizer_bundle        ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[0].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[0].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[10].u|                                                           ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[10].u                                                 ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut   ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[1].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[1].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[2].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[2].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[3].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[3].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[4].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[4].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[5].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[5].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[6].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[6].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[7].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[7].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[8].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[8].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[9].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[9].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|                                                         ; 0 (0)               ; 33 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2                                                                                            ; altera_eth_tse_std_synchronizer_bundle        ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[0].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[10].u|                                                           ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[10].u                                                 ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut   ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[1].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[2].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[3].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[4].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[5].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[6].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[7].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[8].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[9].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[9].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|                                                         ; 0 (0)               ; 33 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3                                                                                            ; altera_eth_tse_std_synchronizer_bundle        ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[0].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[0].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[10].u|                                                           ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[10].u                                                 ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut   ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[1].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[1].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[2].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[2].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[3].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[3].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[4].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[4].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[5].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[5].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[6].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[6].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[7].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[7].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[8].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[8].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[9].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[9].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|                                                         ; 0 (0)               ; 33 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4                                                                                            ; altera_eth_tse_std_synchronizer_bundle        ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[0].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[0].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[10].u|                                                           ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[10].u                                                 ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut   ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[1].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[1].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[2].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[2].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[3].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[3].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[4].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[4].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[5].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[5].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[6].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[6].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[7].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[7].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[8].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[8].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                                  |altera_eth_tse_std_synchronizer:sync[9].u|                                                            ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[9].u                                                  ; altera_eth_tse_std_synchronizer               ; nios2        ;
;                                     |altera_std_synchronizer_nocut:std_sync_no_cut|                                                     ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut    ; altera_std_synchronizer_nocut                 ; nios2        ;
;                               |altera_tse_altsyncram_dpm_fifo:U_RAM|                                                                    ; 0 (0)               ; 0 (0)                     ; 73728             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM                                                                                                       ; altera_tse_altsyncram_dpm_fifo                ; nios2        ;
;                                  |altsyncram:altsyncram_component|                                                                      ; 0 (0)               ; 0 (0)                     ; 73728             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component                                                                       ; altsyncram                                    ; work         ;
;                                     |altsyncram_3ao1:auto_generated|                                                                    ; 0 (0)               ; 0 (0)                     ; 73728             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_3ao1:auto_generated                                        ; altsyncram_3ao1                               ; work         ;
;                               |altera_tse_gray_cnt:U_RD|                                                                                ; 26 (26)             ; 33 (33)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD                                                                                                                   ; altera_tse_gray_cnt                           ; nios2        ;
;                               |altera_tse_gray_cnt:U_WRT|                                                                               ; 26 (26)             ; 33 (33)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT                                                                                                                  ; altera_tse_gray_cnt                           ; nios2        ;
;             |nios2_fabric_if:fabric_if|                                                                                                 ; 382 (0)             ; 684 (0)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if                                                                                                                                                                                                                                                                                                                    ; nios2_fabric_if                               ; nios2        ;
;                |altera_reset_controller:rst_controller|                                                                                 ; 0 (0)               ; 3 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller                                                                                                                                                                                                                                                                             ; altera_reset_controller                       ; nios2        ;
;                   |altera_reset_synchronizer:alt_rst_sync_uq1|                                                                          ; 0 (0)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1                                                                                                                                                                                                                                  ; altera_reset_synchronizer                     ; nios2        ;
;                |nios2_TX_CTRL:daq_dest_mac_addr_h|                                                                                      ; 2 (2)               ; 16 (16)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_CTRL:daq_dest_mac_addr_h                                                                                                                                                                                                                                                                                  ; nios2_TX_CTRL                                 ; nios2        ;
;                |nios2_TX_CTRL:own_mac_addr_h|                                                                                           ; 2 (2)               ; 16 (16)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_CTRL:own_mac_addr_h                                                                                                                                                                                                                                                                                       ; nios2_TX_CTRL                                 ; nios2        ;
;                |nios2_TX_CTRL:sc_dest_mac_addr_h|                                                                                       ; 2 (2)               ; 16 (16)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_CTRL:sc_dest_mac_addr_h                                                                                                                                                                                                                                                                                   ; nios2_TX_CTRL                                 ; nios2        ;
;                |nios2_TX_CTRL:testing|                                                                                                  ; 2 (2)               ; 16 (16)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_CTRL:testing                                                                                                                                                                                                                                                                                              ; nios2_TX_CTRL                                 ; nios2        ;
;                |nios2_TX_CTRL:version|                                                                                                  ; 18 (18)             ; 16 (16)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_CTRL:version                                                                                                                                                                                                                                                                                              ; nios2_TX_CTRL                                 ; nios2        ;
;                |nios2_TX_STATUS:own_mac_addr_h_in|                                                                                      ; 5 (5)               ; 5 (5)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in                                                                                                                                                                                                                                                                                  ; nios2_TX_STATUS                               ; nios2        ;
;                |nios2_fabric_if_daq_dest_ip_addr:daq_dest_ip_addr|                                                                      ; 2 (2)               ; 32 (32)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_daq_dest_ip_addr:daq_dest_ip_addr                                                                                                                                                                                                                                                                  ; nios2_fabric_if_daq_dest_ip_addr              ; nios2        ;
;                |nios2_fabric_if_daq_dest_ip_addr:daq_dest_mac_addr_l|                                                                   ; 2 (2)               ; 32 (32)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_daq_dest_ip_addr:daq_dest_mac_addr_l                                                                                                                                                                                                                                                               ; nios2_fabric_if_daq_dest_ip_addr              ; nios2        ;
;                |nios2_fabric_if_daq_dest_ip_addr:own_ip_addr|                                                                           ; 2 (2)               ; 32 (32)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_daq_dest_ip_addr:own_ip_addr                                                                                                                                                                                                                                                                       ; nios2_fabric_if_daq_dest_ip_addr              ; nios2        ;
;                |nios2_fabric_if_daq_dest_ip_addr:own_mac_addr_l|                                                                        ; 2 (2)               ; 32 (32)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_daq_dest_ip_addr:own_mac_addr_l                                                                                                                                                                                                                                                                    ; nios2_fabric_if_daq_dest_ip_addr              ; nios2        ;
;                |nios2_fabric_if_daq_dest_ip_addr:sc_dest_ip_addr|                                                                       ; 2 (2)               ; 32 (32)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_daq_dest_ip_addr:sc_dest_ip_addr                                                                                                                                                                                                                                                                   ; nios2_fabric_if_daq_dest_ip_addr              ; nios2        ;
;                |nios2_fabric_if_daq_dest_ip_addr:sc_dest_mac_addr_l|                                                                    ; 5 (5)               ; 32 (32)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_daq_dest_ip_addr:sc_dest_mac_addr_l                                                                                                                                                                                                                                                                ; nios2_fabric_if_daq_dest_ip_addr              ; nios2        ;
;                |nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|                                                                    ; 336 (0)             ; 404 (0)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0                                                                                                                                                                                                                                                                ; nios2_fabric_if_mm_interconnect_0             ; nios2        ;
;                   |altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|                                                            ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo                                                                                                                                                                                                       ; altera_avalon_sc_fifo                         ; nios2        ;
;                   |altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|                                                         ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo                                                                                                                                                                                                    ; altera_avalon_sc_fifo                         ; nios2        ;
;                   |altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|                                                         ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo                                                                                                                                                                                                    ; altera_avalon_sc_fifo                         ; nios2        ;
;                   |altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|                                                              ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo                                                                                                                                                                                                         ; altera_avalon_sc_fifo                         ; nios2        ;
;                   |altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|                                                                 ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo                                                                                                                                                                                                            ; altera_avalon_sc_fifo                         ; nios2        ;
;                   |altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|                                                           ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo                                                                                                                                                                                                      ; altera_avalon_sc_fifo                         ; nios2        ;
;                   |altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|                                                              ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo                                                                                                                                                                                                         ; altera_avalon_sc_fifo                         ; nios2        ;
;                   |altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|                                                           ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo                                                                                                                                                                                                      ; altera_avalon_sc_fifo                         ; nios2        ;
;                   |altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|                                                              ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo                                                                                                                                                                                                         ; altera_avalon_sc_fifo                         ; nios2        ;
;                   |altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|                                                                  ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo                                                                                                                                                                                                             ; altera_avalon_sc_fifo                         ; nios2        ;
;                   |altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|                                                             ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo                                                                                                                                                                                                        ; altera_avalon_sc_fifo                         ; nios2        ;
;                   |altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|                                                          ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo                                                                                                                                                                                                     ; altera_avalon_sc_fifo                         ; nios2        ;
;                   |altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|                                                          ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo                                                                                                                                                                                                     ; altera_avalon_sc_fifo                         ; nios2        ;
;                   |altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|                                                                     ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo                                                                                                                                                                                                                ; altera_avalon_sc_fifo                         ; nios2        ;
;                   |altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|                                                                     ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo                                                                                                                                                                                                                ; altera_avalon_sc_fifo                         ; nios2        ;
;                   |altera_merlin_master_agent:if_bridge_m0_agent|                                                                       ; 2 (2)               ; 1 (1)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:if_bridge_m0_agent                                                                                                                                                                                                                  ; altera_merlin_master_agent                    ; nios2        ;
;                   |altera_merlin_slave_agent:own_ip_addr_s1_agent|                                                                      ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_s1_agent                                                                                                                                                                                                                 ; altera_merlin_slave_agent                     ; nios2        ;
;                   |altera_merlin_slave_agent:own_mac_addr_h_in_s1_agent|                                                                ; 3 (3)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_in_s1_agent                                                                                                                                                                                                           ; altera_merlin_slave_agent                     ; nios2        ;
;                   |altera_merlin_slave_agent:own_mac_addr_h_s1_agent|                                                                   ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_s1_agent                                                                                                                                                                                                              ; altera_merlin_slave_agent                     ; nios2        ;
;                   |altera_merlin_slave_agent:own_mac_addr_l_in_s1_agent|                                                                ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_in_s1_agent                                                                                                                                                                                                           ; altera_merlin_slave_agent                     ; nios2        ;
;                   |altera_merlin_slave_agent:rot_switch_s1_agent|                                                                       ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:rot_switch_s1_agent                                                                                                                                                                                                                  ; altera_merlin_slave_agent                     ; nios2        ;
;                   |altera_merlin_slave_agent:sc_dest_ip_addr_s1_agent|                                                                  ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_ip_addr_s1_agent                                                                                                                                                                                                             ; altera_merlin_slave_agent                     ; nios2        ;
;                   |altera_merlin_slave_translator:daq_dest_ip_addr_s1_translator|                                                       ; 5 (5)               ; 35 (35)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_ip_addr_s1_translator                                                                                                                                                                                                  ; altera_merlin_slave_translator                ; nios2        ;
;                   |altera_merlin_slave_translator:daq_dest_mac_addr_h_s1_translator|                                                    ; 5 (5)               ; 19 (19)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_h_s1_translator                                                                                                                                                                                               ; altera_merlin_slave_translator                ; nios2        ;
;                   |altera_merlin_slave_translator:daq_dest_mac_addr_l_s1_translator|                                                    ; 4 (4)               ; 35 (35)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_l_s1_translator                                                                                                                                                                                               ; altera_merlin_slave_translator                ; nios2        ;
;                   |altera_merlin_slave_translator:own_ip_addr_in_s1_translator|                                                         ; 7 (7)               ; 8 (8)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator                                                                                                                                                                                                    ; altera_merlin_slave_translator                ; nios2        ;
;                   |altera_merlin_slave_translator:own_ip_addr_s1_translator|                                                            ; 5 (5)               ; 35 (35)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_s1_translator                                                                                                                                                                                                       ; altera_merlin_slave_translator                ; nios2        ;
;                   |altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|                                                      ; 6 (6)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator                                                                                                                                                                                                 ; altera_merlin_slave_translator                ; nios2        ;
;                   |altera_merlin_slave_translator:own_mac_addr_h_s1_translator|                                                         ; 5 (5)               ; 19 (19)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_s1_translator                                                                                                                                                                                                    ; altera_merlin_slave_translator                ; nios2        ;
;                   |altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|                                                      ; 7 (7)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator                                                                                                                                                                                                 ; altera_merlin_slave_translator                ; nios2        ;
;                   |altera_merlin_slave_translator:own_mac_addr_l_s1_translator|                                                         ; 9 (9)               ; 35 (35)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_s1_translator                                                                                                                                                                                                    ; altera_merlin_slave_translator                ; nios2        ;
;                   |altera_merlin_slave_translator:rot_switch_s1_translator|                                                             ; 7 (7)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator                                                                                                                                                                                                        ; altera_merlin_slave_translator                ; nios2        ;
;                   |altera_merlin_slave_translator:sc_dest_ip_addr_s1_translator|                                                        ; 5 (5)               ; 35 (35)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_ip_addr_s1_translator                                                                                                                                                                                                   ; altera_merlin_slave_translator                ; nios2        ;
;                   |altera_merlin_slave_translator:sc_dest_mac_addr_h_s1_translator|                                                     ; 5 (5)               ; 19 (19)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_h_s1_translator                                                                                                                                                                                                ; altera_merlin_slave_translator                ; nios2        ;
;                   |altera_merlin_slave_translator:sc_dest_mac_addr_l_s1_translator|                                                     ; 4 (4)               ; 35 (35)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_l_s1_translator                                                                                                                                                                                                ; altera_merlin_slave_translator                ; nios2        ;
;                   |altera_merlin_slave_translator:testing_s1_translator|                                                                ; 5 (5)               ; 19 (19)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:testing_s1_translator                                                                                                                                                                                                           ; altera_merlin_slave_translator                ; nios2        ;
;                   |altera_merlin_slave_translator:version_s1_translator|                                                                ; 5 (5)               ; 19 (19)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:version_s1_translator                                                                                                                                                                                                           ; altera_merlin_slave_translator                ; nios2        ;
;                   |altera_merlin_traffic_limiter:if_bridge_m0_limiter|                                                                  ; 22 (22)             ; 21 (21)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:if_bridge_m0_limiter                                                                                                                                                                                                             ; altera_merlin_traffic_limiter                 ; nios2        ;
;                   |nios2_fabric_if_mm_interconnect_0_cmd_demux:cmd_demux|                                                               ; 30 (30)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_demux:cmd_demux                                                                                                                                                                                                          ; nios2_fabric_if_mm_interconnect_0_cmd_demux   ; nios2        ;
;                   |nios2_fabric_if_mm_interconnect_0_router:router|                                                                     ; 33 (33)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router:router                                                                                                                                                                                                                ; nios2_fabric_if_mm_interconnect_0_router      ; nios2        ;
;                   |nios2_fabric_if_mm_interconnect_0_rsp_mux:rsp_mux|                                                                   ; 97 (97)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_mux:rsp_mux                                                                                                                                                                                                              ; nios2_fabric_if_mm_interconnect_0_rsp_mux     ; nios2        ;
;             |nios2_jtag_uart_0:jtag_uart_0|                                                                                             ; 114 (34)            ; 112 (13)                  ; 1024              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0                                                                                                                                                                                                                                                                                                                ; nios2_jtag_uart_0                             ; nios2        ;
;                |alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|                                                                  ; 32 (32)             ; 59 (59)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic                                                                                                                                                                                                                                                          ; alt_jtag_atlantic                             ; work         ;
;                |nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r|                                                              ; 24 (0)              ; 20 (0)                    ; 512               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r                                                                                                                                                                                                                                                      ; nios2_jtag_uart_0_scfifo_r                    ; nios2        ;
;                   |scfifo:rfifo|                                                                                                        ; 24 (0)              ; 20 (0)                    ; 512               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r|scfifo:rfifo                                                                                                                                                                                                                                         ; scfifo                                        ; work         ;
;                      |scfifo_3291:auto_generated|                                                                                       ; 24 (0)              ; 20 (0)                    ; 512               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_3291:auto_generated                                                                                                                                                                                                              ; scfifo_3291                                   ; work         ;
;                         |a_dpfifo_5771:dpfifo|                                                                                          ; 24 (0)              ; 20 (0)                    ; 512               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo                                                                                                                                                                                         ; a_dpfifo_5771                                 ; work         ;
;                            |a_fefifo_7cf:fifo_state|                                                                                    ; 12 (6)              ; 8 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|a_fefifo_7cf:fifo_state                                                                                                                                                                 ; a_fefifo_7cf                                  ; work         ;
;                               |cntr_vg7:count_usedw|                                                                                    ; 6 (6)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|a_fefifo_7cf:fifo_state|cntr_vg7:count_usedw                                                                                                                                            ; cntr_vg7                                      ; work         ;
;                            |altsyncram_7pu1:FIFOram|                                                                                    ; 0 (0)               ; 0 (0)                     ; 512               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|altsyncram_7pu1:FIFOram                                                                                                                                                                 ; altsyncram_7pu1                               ; work         ;
;                            |cntr_jgb:rd_ptr_count|                                                                                      ; 6 (6)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|cntr_jgb:rd_ptr_count                                                                                                                                                                   ; cntr_jgb                                      ; work         ;
;                            |cntr_jgb:wr_ptr|                                                                                            ; 6 (6)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|cntr_jgb:wr_ptr                                                                                                                                                                         ; cntr_jgb                                      ; work         ;
;                |nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|                                                              ; 24 (0)              ; 20 (0)                    ; 512               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w                                                                                                                                                                                                                                                      ; nios2_jtag_uart_0_scfifo_w                    ; nios2        ;
;                   |scfifo:wfifo|                                                                                                        ; 24 (0)              ; 20 (0)                    ; 512               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo                                                                                                                                                                                                                                         ; scfifo                                        ; work         ;
;                      |scfifo_3291:auto_generated|                                                                                       ; 24 (0)              ; 20 (0)                    ; 512               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_3291:auto_generated                                                                                                                                                                                                              ; scfifo_3291                                   ; work         ;
;                         |a_dpfifo_5771:dpfifo|                                                                                          ; 24 (0)              ; 20 (0)                    ; 512               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo                                                                                                                                                                                         ; a_dpfifo_5771                                 ; work         ;
;                            |a_fefifo_7cf:fifo_state|                                                                                    ; 12 (6)              ; 8 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|a_fefifo_7cf:fifo_state                                                                                                                                                                 ; a_fefifo_7cf                                  ; work         ;
;                               |cntr_vg7:count_usedw|                                                                                    ; 6 (6)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|a_fefifo_7cf:fifo_state|cntr_vg7:count_usedw                                                                                                                                            ; cntr_vg7                                      ; work         ;
;                            |altsyncram_7pu1:FIFOram|                                                                                    ; 0 (0)               ; 0 (0)                     ; 512               ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|altsyncram_7pu1:FIFOram                                                                                                                                                                 ; altsyncram_7pu1                               ; work         ;
;                            |cntr_jgb:rd_ptr_count|                                                                                      ; 6 (6)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|cntr_jgb:rd_ptr_count                                                                                                                                                                   ; cntr_jgb                                      ; work         ;
;                            |cntr_jgb:wr_ptr|                                                                                            ; 6 (6)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|cntr_jgb:wr_ptr                                                                                                                                                                         ; cntr_jgb                                      ; work         ;
;             |nios2_mm_interconnect_0:mm_interconnect_0|                                                                                 ; 650 (0)             ; 374 (0)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0                                                                                                                                                                                                                                                                                                    ; nios2_mm_interconnect_0                       ; nios2        ;
;                |altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|                                                             ; 7 (7)               ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo                                                                                                                                                                                                                                         ; altera_avalon_sc_fifo                         ; nios2        ;
;                |altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|                                                             ; 7 (7)               ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo                                                                                                                                                                                                                                         ; altera_avalon_sc_fifo                         ; nios2        ;
;                |altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|                                                                ; 9 (9)               ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo                                                                                                                                                                                                                                            ; altera_avalon_sc_fifo                         ; nios2        ;
;                |altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|                                                   ; 19 (19)             ; 34 (34)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo                                                                                                                                                                                                                               ; altera_avalon_sc_fifo                         ; nios2        ;
;                |altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|                                                           ; 8 (8)               ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo                                                                                                                                                                                                                                       ; altera_avalon_sc_fifo                         ; nios2        ;
;                |altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|                                                          ; 7 (7)               ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo                                                                                                                                                                                                                                      ; altera_avalon_sc_fifo                         ; nios2        ;
;                |altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|                                                         ; 27 (27)             ; 25 (25)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo                                                                                                                                                                                                                                     ; altera_avalon_sc_fifo                         ; nios2        ;
;                |altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|                                                     ; 8 (8)               ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo                                                                                                                                                                                                                                 ; altera_avalon_sc_fifo                         ; nios2        ;
;                |altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|                                                             ; 11 (11)             ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo                                                                                                                                                                                                                                         ; altera_avalon_sc_fifo                         ; nios2        ;
;                |altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|                                                                     ; 10 (10)             ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo                                                                                                                                                                                                                                                 ; altera_avalon_sc_fifo                         ; nios2        ;
;                |altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|                                                                    ; 8 (8)               ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo                                                                                                                                                                                                                                                ; altera_avalon_sc_fifo                         ; nios2        ;
;                |altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|                                                                ; 9 (9)               ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo                                                                                                                                                                                                                                            ; altera_avalon_sc_fifo                         ; nios2        ;
;                |altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|                                                                        ; 7 (7)               ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo                                                                                                                                                                                                                                                    ; altera_avalon_sc_fifo                         ; nios2        ;
;                |altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|                                                                      ; 7 (7)               ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo                                                                                                                                                                                                                                                  ; altera_avalon_sc_fifo                         ; nios2        ;
;                |altera_merlin_master_agent:nios2_data_master_agent|                                                                     ; 23 (23)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_data_master_agent                                                                                                                                                                                                                                                 ; altera_merlin_master_agent                    ; nios2        ;
;                |altera_merlin_master_agent:nios2_instruction_master_agent|                                                              ; 3 (3)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_instruction_master_agent                                                                                                                                                                                                                                          ; altera_merlin_master_agent                    ; nios2        ;
;                |altera_merlin_master_translator:nios2_data_master_translator|                                                           ; 13 (13)             ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_data_master_translator                                                                                                                                                                                                                                       ; altera_merlin_master_translator               ; nios2        ;
;                |altera_merlin_master_translator:nios2_instruction_master_translator|                                                    ; 2 (2)               ; 1 (1)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_instruction_master_translator                                                                                                                                                                                                                                ; altera_merlin_master_translator               ; nios2        ;
;                |altera_merlin_slave_agent:enet_rx_msgdma_csr_agent|                                                                     ; 3 (3)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_csr_agent                                                                                                                                                                                                                                                 ; altera_merlin_slave_agent                     ; nios2        ;
;                |altera_merlin_slave_agent:eth_tse_mac_control_port_agent|                                                               ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:eth_tse_mac_control_port_agent                                                                                                                                                                                                                                           ; altera_merlin_slave_agent                     ; nios2        ;
;                |altera_merlin_slave_agent:fabric_if_if_bridge_slave_agent|                                                              ; 3 (3)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fabric_if_if_bridge_slave_agent                                                                                                                                                                                                                                          ; altera_merlin_slave_agent                     ; nios2        ;
;                |altera_merlin_slave_agent:nios2_debug_mem_slave_agent|                                                                  ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:nios2_debug_mem_slave_agent                                                                                                                                                                                                                                              ; altera_merlin_slave_agent                     ; nios2        ;
;                |altera_merlin_slave_agent:onchip_mem_s1_agent|                                                                          ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:onchip_mem_s1_agent                                                                                                                                                                                                                                                      ; altera_merlin_slave_agent                     ; nios2        ;
;                |altera_merlin_slave_agent:ser_fifo_rx_in_csr_agent|                                                                     ; 3 (3)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_csr_agent                                                                                                                                                                                                                                                 ; altera_merlin_slave_agent                     ; nios2        ;
;                |altera_merlin_slave_agent:tx_status_s1_agent|                                                                           ; 2 (2)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_status_s1_agent                                                                                                                                                                                                                                                       ; altera_merlin_slave_agent                     ; nios2        ;
;                |altera_merlin_slave_translator:enet_nios_rx_dpram_s1_translator|                                                        ; 1 (1)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_rx_dpram_s1_translator                                                                                                                                                                                                                                    ; altera_merlin_slave_translator                ; nios2        ;
;                |altera_merlin_slave_translator:enet_nios_tx_dpram_s1_translator|                                                        ; 2 (2)               ; 1 (1)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_tx_dpram_s1_translator                                                                                                                                                                                                                                    ; altera_merlin_slave_translator                ; nios2        ;
;                |altera_merlin_slave_translator:enet_rx_msgdma_csr_translator|                                                           ; 5 (5)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_csr_translator                                                                                                                                                                                                                                       ; altera_merlin_slave_translator                ; nios2        ;
;                |altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|                                              ; 1 (1)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator                                                                                                                                                                                                                          ; altera_merlin_slave_translator                ; nios2        ;
;                |altera_merlin_slave_translator:enet_rx_msgdma_response_translator|                                                      ; 1 (1)               ; 33 (33)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_response_translator                                                                                                                                                                                                                                  ; altera_merlin_slave_translator                ; nios2        ;
;                |altera_merlin_slave_translator:eth_tse_mac_control_port_translator|                                                     ; 1 (1)               ; 33 (33)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:eth_tse_mac_control_port_translator                                                                                                                                                                                                                                 ; altera_merlin_slave_translator                ; nios2        ;
;                |altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|                                                ; 2 (2)               ; 23 (23)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator                                                                                                                                                                                                                            ; altera_merlin_slave_translator                ; nios2        ;
;                |altera_merlin_slave_translator:nios2_debug_mem_slave_translator|                                                        ; 1 (1)               ; 34 (34)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:nios2_debug_mem_slave_translator                                                                                                                                                                                                                                    ; altera_merlin_slave_translator                ; nios2        ;
;                |altera_merlin_slave_translator:onchip_mem_s1_translator|                                                                ; 2 (2)               ; 1 (1)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:onchip_mem_s1_translator                                                                                                                                                                                                                                            ; altera_merlin_slave_translator                ; nios2        ;
;                |altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|                                                           ; 5 (5)               ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator                                                                                                                                                                                                                                       ; altera_merlin_slave_translator                ; nios2        ;
;                |altera_merlin_slave_translator:ser_fifo_rx_in_translator|                                                               ; 1 (1)               ; 1 (1)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator                                                                                                                                                                                                                                           ; altera_merlin_slave_translator                ; nios2        ;
;                |altera_merlin_slave_translator:tx_ctrl_s1_translator|                                                                   ; 4 (4)               ; 19 (19)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_ctrl_s1_translator                                                                                                                                                                                                                                               ; altera_merlin_slave_translator                ; nios2        ;
;                |altera_merlin_slave_translator:tx_status_s1_translator|                                                                 ; 3 (3)               ; 7 (7)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator                                                                                                                                                                                                                                             ; altera_merlin_slave_translator                ; nios2        ;
;                |altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|                                          ; 37 (37)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter                                                                                                                                                                                                                      ; altera_merlin_width_adapter                   ; nios2        ;
;                |nios2_mm_interconnect_0_cmd_demux:cmd_demux|                                                                            ; 18 (18)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux:cmd_demux                                                                                                                                                                                                                                                        ; nios2_mm_interconnect_0_cmd_demux             ; nios2        ;
;                |nios2_mm_interconnect_0_cmd_demux_001:cmd_demux_001|                                                                    ; 3 (3)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux_001:cmd_demux_001                                                                                                                                                                                                                                                ; nios2_mm_interconnect_0_cmd_demux_001         ; nios2        ;
;                |nios2_mm_interconnect_0_cmd_demux_001:rsp_demux_003|                                                                    ; 2 (2)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux_001:rsp_demux_003                                                                                                                                                                                                                                                ; nios2_mm_interconnect_0_cmd_demux_001         ; nios2        ;
;                |nios2_mm_interconnect_0_cmd_demux_001:rsp_demux_009|                                                                    ; 2 (2)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux_001:rsp_demux_009                                                                                                                                                                                                                                                ; nios2_mm_interconnect_0_cmd_demux_001         ; nios2        ;
;                |nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003|                                                                        ; 52 (48)             ; 5 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003                                                                                                                                                                                                                                                    ; nios2_mm_interconnect_0_cmd_mux_003           ; nios2        ;
;                   |altera_merlin_arbitrator:arb|                                                                                        ; 4 (4)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003|altera_merlin_arbitrator:arb                                                                                                                                                                                                                       ; altera_merlin_arbitrator                      ; nios2        ;
;                |nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_009|                                                                        ; 57 (53)             ; 5 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_009                                                                                                                                                                                                                                                    ; nios2_mm_interconnect_0_cmd_mux_003           ; nios2        ;
;                   |altera_merlin_arbitrator:arb|                                                                                        ; 4 (4)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_009|altera_merlin_arbitrator:arb                                                                                                                                                                                                                       ; altera_merlin_arbitrator                      ; nios2        ;
;                |nios2_mm_interconnect_0_router:router|                                                                                  ; 30 (30)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router:router                                                                                                                                                                                                                                                              ; nios2_mm_interconnect_0_router                ; nios2        ;
;                |nios2_mm_interconnect_0_router_001:router_001|                                                                          ; 2 (2)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_001:router_001                                                                                                                                                                                                                                                      ; nios2_mm_interconnect_0_router_001            ; nios2        ;
;                |nios2_mm_interconnect_0_rsp_mux:rsp_mux|                                                                                ; 216 (216)           ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux:rsp_mux                                                                                                                                                                                                                                                            ; nios2_mm_interconnect_0_rsp_mux               ; nios2        ;
;             |nios2_mm_interconnect_1:mm_interconnect_1|                                                                                 ; 53 (0)              ; 14 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1                                                                                                                                                                                                                                                                                                    ; nios2_mm_interconnect_1                       ; nios2        ;
;                |altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|                                                             ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo                                                                                                                                                                                                                                         ; altera_avalon_sc_fifo                         ; nios2        ;
;                |altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|                                                                 ; 4 (4)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo                                                                                                                                                                                                                                             ; altera_avalon_sc_fifo                         ; nios2        ;
;                |altera_merlin_slave_translator:enet_nios_tx_dpram_s2_translator|                                                        ; 2 (2)               ; 1 (1)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_nios_tx_dpram_s2_translator                                                                                                                                                                                                                                    ; altera_merlin_slave_translator                ; nios2        ;
;                |altera_merlin_slave_translator:enet_udp_dpram_s2_translator|                                                            ; 1 (1)               ; 1 (1)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_udp_dpram_s2_translator                                                                                                                                                                                                                                        ; altera_merlin_slave_translator                ; nios2        ;
;                |altera_merlin_traffic_limiter:enet_tx_msgdma_mm_read_limiter|                                                           ; 7 (7)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_traffic_limiter:enet_tx_msgdma_mm_read_limiter                                                                                                                                                                                                                                       ; altera_merlin_traffic_limiter                 ; nios2        ;
;                |nios2_mm_interconnect_1_cmd_demux:cmd_demux|                                                                            ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_cmd_demux:cmd_demux                                                                                                                                                                                                                                                        ; nios2_mm_interconnect_1_cmd_demux             ; nios2        ;
;                |nios2_mm_interconnect_1_router:router|                                                                                  ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router:router                                                                                                                                                                                                                                                              ; nios2_mm_interconnect_1_router                ; nios2        ;
;                |nios2_mm_interconnect_1_rsp_mux:rsp_mux|                                                                                ; 33 (33)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_rsp_mux:rsp_mux                                                                                                                                                                                                                                                            ; nios2_mm_interconnect_1_rsp_mux               ; nios2        ;
;             |nios2_nios2:nios2|                                                                                                         ; 629 (0)             ; 580 (0)                   ; 10240             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2                                                                                                                                                                                                                                                                                                                            ; nios2_nios2                                   ; nios2        ;
;                |nios2_nios2_cpu:cpu|                                                                                                    ; 629 (465)           ; 580 (310)                 ; 10240             ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu                                                                                                                                                                                                                                                                                                        ; nios2_nios2_cpu                               ; nios2        ;
;                   |nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|                                                             ; 164 (8)             ; 270 (80)                  ; 8192              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci                                                                                                                                                                                                                                                ; nios2_nios2_cpu_nios2_oci                     ; nios2        ;
;                      |nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|                                      ; 64 (0)              ; 96 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper                                                                                                                                                                    ; nios2_nios2_cpu_debug_slave_wrapper           ; nios2        ;
;                         |nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|                                     ; 6 (6)               ; 49 (45)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk                                                                                          ; nios2_nios2_cpu_debug_slave_sysclk            ; nios2        ;
;                            |altera_std_synchronizer:the_altera_std_synchronizer3|                                                       ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3                                     ; altera_std_synchronizer                       ; work         ;
;                            |altera_std_synchronizer:the_altera_std_synchronizer4|                                                       ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4                                     ; altera_std_synchronizer                       ; work         ;
;                         |nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|                                           ; 54 (54)             ; 47 (43)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck                                                                                                ; nios2_nios2_cpu_debug_slave_tck               ; nios2        ;
;                            |altera_std_synchronizer:the_altera_std_synchronizer1|                                                       ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|altera_std_synchronizer:the_altera_std_synchronizer1                                           ; altera_std_synchronizer                       ; work         ;
;                            |altera_std_synchronizer:the_altera_std_synchronizer2|                                                       ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|altera_std_synchronizer:the_altera_std_synchronizer2                                           ; altera_std_synchronizer                       ; work         ;
;                         |sld_virtual_jtag_basic:nios2_nios2_cpu_debug_slave_phy|                                                        ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:nios2_nios2_cpu_debug_slave_phy                                                                                                             ; sld_virtual_jtag_basic                        ; work         ;
;                      |nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|                                            ; 7 (7)               ; 4 (4)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg                                                                                                                                                                          ; nios2_nios2_cpu_nios2_avalon_reg              ; nios2        ;
;                      |nios2_nios2_cpu_nios2_oci_break:the_nios2_nios2_cpu_nios2_oci_break|                                              ; 2 (2)               ; 32 (32)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_break:the_nios2_nios2_cpu_nios2_oci_break                                                                                                                                                                            ; nios2_nios2_cpu_nios2_oci_break               ; nios2        ;
;                      |nios2_nios2_cpu_nios2_oci_debug:the_nios2_nios2_cpu_nios2_oci_debug|                                              ; 6 (6)               ; 9 (7)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_debug:the_nios2_nios2_cpu_nios2_oci_debug                                                                                                                                                                            ; nios2_nios2_cpu_nios2_oci_debug               ; nios2        ;
;                         |altera_std_synchronizer:the_altera_std_synchronizer|                                                           ; 0 (0)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_debug:the_nios2_nios2_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer                                                                                                                        ; altera_std_synchronizer                       ; work         ;
;                      |nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|                                                    ; 77 (77)             ; 49 (49)                   ; 8192              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem                                                                                                                                                                                  ; nios2_nios2_cpu_nios2_ocimem                  ; nios2        ;
;                         |nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram|                                            ; 0 (0)               ; 0 (0)                     ; 8192              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram                                                                                                               ; nios2_nios2_cpu_ociram_sp_ram_module          ; nios2        ;
;                            |altsyncram:the_altsyncram|                                                                                  ; 0 (0)               ; 0 (0)                     ; 8192              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram|altsyncram:the_altsyncram                                                                                     ; altsyncram                                    ; work         ;
;                               |altsyncram_qid1:auto_generated|                                                                          ; 0 (0)               ; 0 (0)                     ; 8192              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_qid1:auto_generated                                                      ; altsyncram_qid1                               ; work         ;
;                   |nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a|                                              ; 0 (0)               ; 0 (0)                     ; 1024              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a                                                                                                                                                                                                                                 ; nios2_nios2_cpu_register_bank_a_module        ; nios2        ;
;                      |altsyncram:the_altsyncram|                                                                                        ; 0 (0)               ; 0 (0)                     ; 1024              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a|altsyncram:the_altsyncram                                                                                                                                                                                                       ; altsyncram                                    ; work         ;
;                         |altsyncram_msi1:auto_generated|                                                                                ; 0 (0)               ; 0 (0)                     ; 1024              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_msi1:auto_generated                                                                                                                                                                        ; altsyncram_msi1                               ; work         ;
;                   |nios2_nios2_cpu_register_bank_b_module:nios2_nios2_cpu_register_bank_b|                                              ; 0 (0)               ; 0 (0)                     ; 1024              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_b_module:nios2_nios2_cpu_register_bank_b                                                                                                                                                                                                                                 ; nios2_nios2_cpu_register_bank_b_module        ; nios2        ;
;                      |altsyncram:the_altsyncram|                                                                                        ; 0 (0)               ; 0 (0)                     ; 1024              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_b_module:nios2_nios2_cpu_register_bank_b|altsyncram:the_altsyncram                                                                                                                                                                                                       ; altsyncram                                    ; work         ;
;                         |altsyncram_msi1:auto_generated|                                                                                ; 0 (0)               ; 0 (0)                     ; 1024              ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_b_module:nios2_nios2_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_msi1:auto_generated                                                                                                                                                                        ; altsyncram_msi1                               ; work         ;
;             |nios2_onchip_mem:onchip_mem|                                                                                               ; 38 (2)              ; 2 (0)                     ; 1048576           ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem                                                                                                                                                                                                                                                                                                                  ; nios2_onchip_mem                              ; nios2        ;
;                |altsyncram:the_altsyncram|                                                                                              ; 36 (0)              ; 2 (0)                     ; 1048576           ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram                                                                                                                                                                                                                                                                                        ; altsyncram                                    ; work         ;
;                   |altsyncram_pnr1:auto_generated|                                                                                      ; 36 (0)              ; 2 (2)                     ; 1048576           ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram|altsyncram_pnr1:auto_generated                                                                                                                                                                                                                                                         ; altsyncram_pnr1                               ; work         ;
;                      |decode_8la:decode3|                                                                                               ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram|altsyncram_pnr1:auto_generated|decode_8la:decode3                                                                                                                                                                                                                                      ; decode_8la                                    ; work         ;
;                      |mux_5hb:mux2|                                                                                                     ; 32 (32)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram|altsyncram_pnr1:auto_generated|mux_5hb:mux2                                                                                                                                                                                                                                            ; mux_5hb                                       ; work         ;
;             |nios2_pll_enet:pll_enet|                                                                                                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_pll_enet:pll_enet                                                                                                                                                                                                                                                                                                                      ; nios2_pll_enet                                ; nios2        ;
;                |altera_pll:altera_pll_i|                                                                                                ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_pll_enet:pll_enet|altera_pll:altera_pll_i                                                                                                                                                                                                                                                                                              ; altera_pll                                    ; work         ;
;       |UFP_DECODER:C_DECODER|                                                                                                           ; 210 (210)           ; 95 (95)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER                                                                                                                                                                                                                                                                                                                                                                   ; UFP_DECODER                                   ; work         ;
;       |UFP_ENCODER_UART:C_ENCODER|                                                                                                      ; 154 (154)           ; 103 (103)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER                                                                                                                                                                                                                                                                                                                                                              ; UFP_ENCODER_UART                              ; work         ;
;       |ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|                                                                                              ; 35 (9)              ; 21 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC                                                                                                                                                                                                                                                                                                                                                      ; ser_crc_pol16_DIN16_D4_1a2eb                  ; work         ;
;          |ser_crc:C_CRC|                                                                                                                ; 26 (26)             ; 21 (21)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC                                                                                                                                                                                                                                                                                                                                        ; ser_crc                                       ; work         ;
;    |FTR_CLK_WRAPPER:C_CLK_WRAPPER|                                                                                                      ; 118 (52)            ; 65 (39)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER                                                                                                                                                                                                                                                                                                                                                                                             ; FTR_CLK_WRAPPER                               ; work         ;
;       |FTR_FINE_PHASE_SM:C_PHASE_TUNE|                                                                                                  ; 31 (31)             ; 20 (20)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE                                                                                                                                                                                                                                                                                                                                                              ; FTR_FINE_PHASE_SM                             ; work         ;
;       |PLL_4K:C_PLL4|                                                                                                                   ; 35 (0)              ; 6 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4                                                                                                                                                                                                                                                                                                                                                                               ; PLL_4K                                        ; pll_4k       ;
;          |PLL_4K_0002:pll_4k_inst|                                                                                                      ; 35 (0)              ; 6 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst                                                                                                                                                                                                                                                                                                                                                       ; PLL_4K_0002                                   ; PLL_4K       ;
;             |altera_pll:altera_pll_i|                                                                                                   ; 35 (23)             ; 6 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i                                                                                                                                                                                                                                                                                                                               ; altera_pll                                    ; work         ;
;                |altera_cyclonev_pll:cyclonev_pll|                                                                                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll                                                                                                                                                                                                                                                                                              ; altera_cyclonev_pll                           ; work         ;
;                   |altera_cyclonev_pll_base:fpll_0|                                                                                     ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0                                                                                                                                                                                                                                                              ; altera_cyclonev_pll_base                      ; work         ;
;                |altera_pll_dps_lcell_comb:lcell_cntsel_int_0|                                                                           ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0                                                                                                                                                                                                                                                                                  ; altera_pll_dps_lcell_comb                     ; work         ;
;                |altera_pll_dps_lcell_comb:lcell_cntsel_int_1|                                                                           ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1                                                                                                                                                                                                                                                                                  ; altera_pll_dps_lcell_comb                     ; work         ;
;                |altera_pll_dps_lcell_comb:lcell_cntsel_int_2|                                                                           ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2                                                                                                                                                                                                                                                                                  ; altera_pll_dps_lcell_comb                     ; work         ;
;                |altera_pll_dps_lcell_comb:lcell_cntsel_int_3|                                                                           ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3                                                                                                                                                                                                                                                                                  ; altera_pll_dps_lcell_comb                     ; work         ;
;                |altera_pll_dps_lcell_comb:lcell_cntsel_int_4|                                                                           ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4                                                                                                                                                                                                                                                                                  ; altera_pll_dps_lcell_comb                     ; work         ;
;                |dps_extra_kick:dps_extra_inst|                                                                                          ; 7 (7)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst                                                                                                                                                                                                                                                                                                 ; dps_extra_kick                                ; work         ;
;       |PLL_MAIN:C_PLL|                                                                                                                  ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL                                                                                                                                                                                                                                                                                                                                                                              ; PLL_MAIN                                      ; pll_main     ;
;          |PLL_MAIN_0002:pll_main_inst|                                                                                                  ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst                                                                                                                                                                                                                                                                                                                                                  ; PLL_MAIN_0002                                 ; PLL_MAIN     ;
;             |altera_pll:altera_pll_i|                                                                                                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i                                                                                                                                                                                                                                                                                                                          ; altera_pll                                    ; work         ;
;    |FTR_FaserWrapper:C_WRAPPER|                                                                                                         ; 4249 (12)           ; 3864 (24)                 ; 851968            ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER                                                                                                                                                                                                                                                                                                                                                                                                ; FTR_FaserWrapper                              ; work         ;
;       |FTR_L2_SM:C_L2_SM|                                                                                                               ; 457 (457)           ; 226 (226)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM                                                                                                                                                                                                                                                                                                                                                                              ; FTR_L2_SM                                     ; work         ;
;       |FTR_PlaneController:C_PC|                                                                                                        ; 620 (0)             ; 638 (4)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC                                                                                                                                                                                                                                                                                                                                                                       ; FTR_PlaneController                           ; work         ;
;          |FTR_PatchPanelControllerSM:C_PP_Controller0|                                                                                  ; 263 (263)           ; 263 (263)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0                                                                                                                                                                                                                                                                                                                           ; FTR_PatchPanelControllerSM                    ; work         ;
;          |FTR_PatchPanelControllerSM:C_PP_Controller1|                                                                                  ; 258 (258)           ; 263 (263)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1                                                                                                                                                                                                                                                                                                                           ; FTR_PatchPanelControllerSM                    ; work         ;
;          |FTR_PlaneControllerSM:C_PC_SM|                                                                                                ; 99 (99)             ; 108 (108)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM                                                                                                                                                                                                                                                                                                                                         ; FTR_PlaneControllerSM                         ; work         ;
;       |FTR_RXDataPlaneManager:C_RXDPM|                                                                                                  ; 3160 (4)            ; 2976 (16)                 ; 851968            ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM                                                                                                                                                                                                                                                                                                                                                                 ; FTR_RXDataPlaneManager                        ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|                                                                                        ; 93 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED                                                                                                                                                                                                                                                                                                                           ; FTR_L1_FIFO                                   ; work         ;
;             |dcfifo:dcfifo_component|                                                                                                   ; 93 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                   ; dcfifo                                        ; work         ;
;                |dcfifo_jtr1:auto_generated|                                                                                             ; 93 (18)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                                                                                                                                                                                                        ; dcfifo_jtr1                                   ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                                                                                     ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                                                                                                                                        ; a_gray2bin_qab                                ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                                     ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                                                                                                                                        ; a_gray2bin_qab                                ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                                                                                         ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                                                                                                                                            ; a_graycounter_ldc                             ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                                                                                         ; 27 (27)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                                                                                                                                            ; a_graycounter_pv6                             ; work         ;
;                   |alt_synch_pipe_epl:rs_dgwp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp                                                                                                                                                                                                                                             ; alt_synch_pipe_epl                            ; work         ;
;                      |dffpipe_0f9:dffpipe6|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6                                                                                                                                                                                                                        ; dffpipe_0f9                                   ; work         ;
;                   |alt_synch_pipe_fpl:ws_dgrp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp                                                                                                                                                                                                                                             ; alt_synch_pipe_fpl                            ; work         ;
;                      |dffpipe_1f9:dffpipe9|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9                                                                                                                                                                                                                        ; dffpipe_1f9                                   ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                                                                                            ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                                                                                                                                                                                               ; altsyncram_t8d1                               ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                                                                                            ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                                                                                                                                               ; cmpr_b06                                      ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                                                                                             ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                                                                                                                                                ; cmpr_b06                                      ; work         ;
;                   |dffpipe_qe9:ws_brp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                                                                                                                                                                                                     ; dffpipe_qe9                                   ; work         ;
;                   |dffpipe_qe9:ws_bwp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                                                                                                                                                     ; dffpipe_qe9                                   ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|                                                                                        ; 91 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED                                                                                                                                                                                                                                                                                                                           ; FTR_L1_FIFO                                   ; work         ;
;             |dcfifo:dcfifo_component|                                                                                                   ; 91 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                   ; dcfifo                                        ; work         ;
;                |dcfifo_jtr1:auto_generated|                                                                                             ; 91 (17)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                                                                                                                                                                                                        ; dcfifo_jtr1                                   ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                                                                                     ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                                                                                                                                        ; a_gray2bin_qab                                ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                                     ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                                                                                                                                        ; a_gray2bin_qab                                ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                                                                                         ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                                                                                                                                            ; a_graycounter_ldc                             ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                                                                                         ; 26 (26)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                                                                                                                                            ; a_graycounter_pv6                             ; work         ;
;                   |alt_synch_pipe_epl:rs_dgwp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp                                                                                                                                                                                                                                             ; alt_synch_pipe_epl                            ; work         ;
;                      |dffpipe_0f9:dffpipe6|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6                                                                                                                                                                                                                        ; dffpipe_0f9                                   ; work         ;
;                   |alt_synch_pipe_fpl:ws_dgrp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp                                                                                                                                                                                                                                             ; alt_synch_pipe_fpl                            ; work         ;
;                      |dffpipe_1f9:dffpipe9|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9                                                                                                                                                                                                                        ; dffpipe_1f9                                   ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                                                                                            ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                                                                                                                                                                                               ; altsyncram_t8d1                               ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                                                                                            ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                                                                                                                                               ; cmpr_b06                                      ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                                                                                             ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                                                                                                                                                ; cmpr_b06                                      ; work         ;
;                   |dffpipe_qe9:ws_brp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                                                                                                                                                                                                     ; dffpipe_qe9                                   ; work         ;
;                   |dffpipe_qe9:ws_bwp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                                                                                                                                                     ; dffpipe_qe9                                   ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|                                                                                        ; 94 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED                                                                                                                                                                                                                                                                                                                           ; FTR_L1_FIFO                                   ; work         ;
;             |dcfifo:dcfifo_component|                                                                                                   ; 94 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                   ; dcfifo                                        ; work         ;
;                |dcfifo_jtr1:auto_generated|                                                                                             ; 94 (20)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                                                                                                                                                                                                        ; dcfifo_jtr1                                   ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                                                                                     ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                                                                                                                                        ; a_gray2bin_qab                                ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                                     ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                                                                                                                                        ; a_gray2bin_qab                                ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                                                                                         ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                                                                                                                                            ; a_graycounter_ldc                             ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                                                                                         ; 26 (26)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                                                                                                                                            ; a_graycounter_pv6                             ; work         ;
;                   |alt_synch_pipe_epl:rs_dgwp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp                                                                                                                                                                                                                                             ; alt_synch_pipe_epl                            ; work         ;
;                      |dffpipe_0f9:dffpipe6|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6                                                                                                                                                                                                                        ; dffpipe_0f9                                   ; work         ;
;                   |alt_synch_pipe_fpl:ws_dgrp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp                                                                                                                                                                                                                                             ; alt_synch_pipe_fpl                            ; work         ;
;                      |dffpipe_1f9:dffpipe9|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9                                                                                                                                                                                                                        ; dffpipe_1f9                                   ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                                                                                            ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                                                                                                                                                                                               ; altsyncram_t8d1                               ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                                                                                            ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                                                                                                                                               ; cmpr_b06                                      ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                                                                                             ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                                                                                                                                                ; cmpr_b06                                      ; work         ;
;                   |dffpipe_qe9:ws_brp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                                                                                                                                                                                                     ; dffpipe_qe9                                   ; work         ;
;                   |dffpipe_qe9:ws_bwp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                                                                                                                                                     ; dffpipe_qe9                                   ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|                                                                                        ; 94 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED                                                                                                                                                                                                                                                                                                                           ; FTR_L1_FIFO                                   ; work         ;
;             |dcfifo:dcfifo_component|                                                                                                   ; 94 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                   ; dcfifo                                        ; work         ;
;                |dcfifo_jtr1:auto_generated|                                                                                             ; 94 (19)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                                                                                                                                                                                                        ; dcfifo_jtr1                                   ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                                                                                     ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                                                                                                                                        ; a_gray2bin_qab                                ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                                     ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                                                                                                                                        ; a_gray2bin_qab                                ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                                                                                         ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                                                                                                                                            ; a_graycounter_ldc                             ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                                                                                         ; 27 (27)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                                                                                                                                            ; a_graycounter_pv6                             ; work         ;
;                   |alt_synch_pipe_epl:rs_dgwp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp                                                                                                                                                                                                                                             ; alt_synch_pipe_epl                            ; work         ;
;                      |dffpipe_0f9:dffpipe6|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6                                                                                                                                                                                                                        ; dffpipe_0f9                                   ; work         ;
;                   |alt_synch_pipe_fpl:ws_dgrp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp                                                                                                                                                                                                                                             ; alt_synch_pipe_fpl                            ; work         ;
;                      |dffpipe_1f9:dffpipe9|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9                                                                                                                                                                                                                        ; dffpipe_1f9                                   ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                                                                                            ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                                                                                                                                                                                               ; altsyncram_t8d1                               ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                                                                                            ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                                                                                                                                               ; cmpr_b06                                      ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                                                                                             ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                                                                                                                                                ; cmpr_b06                                      ; work         ;
;                   |dffpipe_qe9:ws_brp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                                                                                                                                                                                                     ; dffpipe_qe9                                   ; work         ;
;                   |dffpipe_qe9:ws_bwp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                                                                                                                                                     ; dffpipe_qe9                                   ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|                                                                                        ; 92 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED                                                                                                                                                                                                                                                                                                                           ; FTR_L1_FIFO                                   ; work         ;
;             |dcfifo:dcfifo_component|                                                                                                   ; 92 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                   ; dcfifo                                        ; work         ;
;                |dcfifo_jtr1:auto_generated|                                                                                             ; 92 (18)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                                                                                                                                                                                                        ; dcfifo_jtr1                                   ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                                                                                     ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                                                                                                                                        ; a_gray2bin_qab                                ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                                     ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                                                                                                                                        ; a_gray2bin_qab                                ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                                                                                         ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                                                                                                                                            ; a_graycounter_ldc                             ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                                                                                         ; 26 (26)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                                                                                                                                            ; a_graycounter_pv6                             ; work         ;
;                   |alt_synch_pipe_epl:rs_dgwp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp                                                                                                                                                                                                                                             ; alt_synch_pipe_epl                            ; work         ;
;                      |dffpipe_0f9:dffpipe6|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6                                                                                                                                                                                                                        ; dffpipe_0f9                                   ; work         ;
;                   |alt_synch_pipe_fpl:ws_dgrp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp                                                                                                                                                                                                                                             ; alt_synch_pipe_fpl                            ; work         ;
;                      |dffpipe_1f9:dffpipe9|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9                                                                                                                                                                                                                        ; dffpipe_1f9                                   ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                                                                                            ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                                                                                                                                                                                               ; altsyncram_t8d1                               ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                                                                                            ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                                                                                                                                               ; cmpr_b06                                      ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                                                                                             ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                                                                                                                                                ; cmpr_b06                                      ; work         ;
;                   |dffpipe_qe9:ws_brp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                                                                                                                                                                                                     ; dffpipe_qe9                                   ; work         ;
;                   |dffpipe_qe9:ws_bwp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                                                                                                                                                     ; dffpipe_qe9                                   ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|                                                                                        ; 92 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED                                                                                                                                                                                                                                                                                                                           ; FTR_L1_FIFO                                   ; work         ;
;             |dcfifo:dcfifo_component|                                                                                                   ; 92 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                   ; dcfifo                                        ; work         ;
;                |dcfifo_jtr1:auto_generated|                                                                                             ; 92 (17)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                                                                                                                                                                                                        ; dcfifo_jtr1                                   ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                                                                                     ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                                                                                                                                        ; a_gray2bin_qab                                ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                                     ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                                                                                                                                        ; a_gray2bin_qab                                ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                                                                                         ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                                                                                                                                            ; a_graycounter_ldc                             ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                                                                                         ; 27 (27)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                                                                                                                                            ; a_graycounter_pv6                             ; work         ;
;                   |alt_synch_pipe_epl:rs_dgwp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp                                                                                                                                                                                                                                             ; alt_synch_pipe_epl                            ; work         ;
;                      |dffpipe_0f9:dffpipe6|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6                                                                                                                                                                                                                        ; dffpipe_0f9                                   ; work         ;
;                   |alt_synch_pipe_fpl:ws_dgrp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp                                                                                                                                                                                                                                             ; alt_synch_pipe_fpl                            ; work         ;
;                      |dffpipe_1f9:dffpipe9|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9                                                                                                                                                                                                                        ; dffpipe_1f9                                   ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                                                                                            ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                                                                                                                                                                                               ; altsyncram_t8d1                               ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                                                                                            ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                                                                                                                                               ; cmpr_b06                                      ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                                                                                             ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                                                                                                                                                ; cmpr_b06                                      ; work         ;
;                   |dffpipe_qe9:ws_brp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                                                                                                                                                                                                     ; dffpipe_qe9                                   ; work         ;
;                   |dffpipe_qe9:ws_bwp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                                                                                                                                                     ; dffpipe_qe9                                   ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|                                                                                        ; 92 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED                                                                                                                                                                                                                                                                                                                           ; FTR_L1_FIFO                                   ; work         ;
;             |dcfifo:dcfifo_component|                                                                                                   ; 92 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                   ; dcfifo                                        ; work         ;
;                |dcfifo_jtr1:auto_generated|                                                                                             ; 92 (18)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                                                                                                                                                                                                        ; dcfifo_jtr1                                   ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                                                                                     ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                                                                                                                                        ; a_gray2bin_qab                                ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                                     ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                                                                                                                                        ; a_gray2bin_qab                                ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                                                                                         ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                                                                                                                                            ; a_graycounter_ldc                             ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                                                                                         ; 26 (26)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                                                                                                                                            ; a_graycounter_pv6                             ; work         ;
;                   |alt_synch_pipe_epl:rs_dgwp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp                                                                                                                                                                                                                                             ; alt_synch_pipe_epl                            ; work         ;
;                      |dffpipe_0f9:dffpipe6|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6                                                                                                                                                                                                                        ; dffpipe_0f9                                   ; work         ;
;                   |alt_synch_pipe_fpl:ws_dgrp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp                                                                                                                                                                                                                                             ; alt_synch_pipe_fpl                            ; work         ;
;                      |dffpipe_1f9:dffpipe9|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9                                                                                                                                                                                                                        ; dffpipe_1f9                                   ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                                                                                            ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                                                                                                                                                                                               ; altsyncram_t8d1                               ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                                                                                            ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                                                                                                                                               ; cmpr_b06                                      ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                                                                                             ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                                                                                                                                                ; cmpr_b06                                      ; work         ;
;                   |dffpipe_qe9:ws_brp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                                                                                                                                                                                                     ; dffpipe_qe9                                   ; work         ;
;                   |dffpipe_qe9:ws_bwp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                                                                                                                                                     ; dffpipe_qe9                                   ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|                                                                                        ; 92 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED                                                                                                                                                                                                                                                                                                                           ; FTR_L1_FIFO                                   ; work         ;
;             |dcfifo:dcfifo_component|                                                                                                   ; 92 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                   ; dcfifo                                        ; work         ;
;                |dcfifo_jtr1:auto_generated|                                                                                             ; 92 (17)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                                                                                                                                                                                                        ; dcfifo_jtr1                                   ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                                                                                     ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                                                                                                                                        ; a_gray2bin_qab                                ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                                     ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                                                                                                                                        ; a_gray2bin_qab                                ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                                                                                         ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                                                                                                                                            ; a_graycounter_ldc                             ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                                                                                         ; 27 (27)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                                                                                                                                            ; a_graycounter_pv6                             ; work         ;
;                   |alt_synch_pipe_epl:rs_dgwp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp                                                                                                                                                                                                                                             ; alt_synch_pipe_epl                            ; work         ;
;                      |dffpipe_0f9:dffpipe6|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6                                                                                                                                                                                                                        ; dffpipe_0f9                                   ; work         ;
;                   |alt_synch_pipe_fpl:ws_dgrp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp                                                                                                                                                                                                                                             ; alt_synch_pipe_fpl                            ; work         ;
;                      |dffpipe_1f9:dffpipe9|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9                                                                                                                                                                                                                        ; dffpipe_1f9                                   ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                                                                                            ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                                                                                                                                                                                               ; altsyncram_t8d1                               ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                                                                                            ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                                                                                                                                               ; cmpr_b06                                      ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                                                                                             ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                                                                                                                                                ; cmpr_b06                                      ; work         ;
;                   |dffpipe_qe9:ws_brp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                                                                                                                                                                                                     ; dffpipe_qe9                                   ; work         ;
;                   |dffpipe_qe9:ws_bwp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                                                                                                                                                     ; dffpipe_qe9                                   ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|                                                                                      ; 94 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX                                                                                                                                                                                                                                                                                                                         ; FTR_L1_FIFO                                   ; work         ;
;             |dcfifo:dcfifo_component|                                                                                                   ; 94 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                 ; dcfifo                                        ; work         ;
;                |dcfifo_jtr1:auto_generated|                                                                                             ; 94 (19)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                                                                                                                                                                                                      ; dcfifo_jtr1                                   ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                                                                                     ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                                                                                                                                      ; a_gray2bin_qab                                ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                                     ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                                                                                                                                      ; a_gray2bin_qab                                ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                                                                                         ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                                                                                                                                          ; a_graycounter_ldc                             ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                                                                                         ; 27 (27)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                                                                                                                                          ; a_graycounter_pv6                             ; work         ;
;                   |alt_synch_pipe_epl:rs_dgwp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp                                                                                                                                                                                                                                           ; alt_synch_pipe_epl                            ; work         ;
;                      |dffpipe_0f9:dffpipe6|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6                                                                                                                                                                                                                      ; dffpipe_0f9                                   ; work         ;
;                   |alt_synch_pipe_fpl:ws_dgrp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp                                                                                                                                                                                                                                           ; alt_synch_pipe_fpl                            ; work         ;
;                      |dffpipe_1f9:dffpipe9|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9                                                                                                                                                                                                                      ; dffpipe_1f9                                   ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                                                                                            ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                                                                                                                                                                                             ; altsyncram_t8d1                               ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                                                                                            ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                                                                                                                                             ; cmpr_b06                                      ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                                                                                             ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                                                                                                                                              ; cmpr_b06                                      ; work         ;
;                   |dffpipe_qe9:ws_brp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                                                                                                                                                                                                   ; dffpipe_qe9                                   ; work         ;
;                   |dffpipe_qe9:ws_bwp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                                                                                                                                                   ; dffpipe_qe9                                   ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|                                                                                      ; 93 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX                                                                                                                                                                                                                                                                                                                         ; FTR_L1_FIFO                                   ; work         ;
;             |dcfifo:dcfifo_component|                                                                                                   ; 93 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                 ; dcfifo                                        ; work         ;
;                |dcfifo_jtr1:auto_generated|                                                                                             ; 93 (18)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                                                                                                                                                                                                      ; dcfifo_jtr1                                   ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                                                                                     ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                                                                                                                                      ; a_gray2bin_qab                                ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                                     ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                                                                                                                                      ; a_gray2bin_qab                                ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                                                                                         ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                                                                                                                                          ; a_graycounter_ldc                             ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                                                                                         ; 27 (27)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                                                                                                                                          ; a_graycounter_pv6                             ; work         ;
;                   |alt_synch_pipe_epl:rs_dgwp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp                                                                                                                                                                                                                                           ; alt_synch_pipe_epl                            ; work         ;
;                      |dffpipe_0f9:dffpipe6|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6                                                                                                                                                                                                                      ; dffpipe_0f9                                   ; work         ;
;                   |alt_synch_pipe_fpl:ws_dgrp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp                                                                                                                                                                                                                                           ; alt_synch_pipe_fpl                            ; work         ;
;                      |dffpipe_1f9:dffpipe9|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9                                                                                                                                                                                                                      ; dffpipe_1f9                                   ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                                                                                            ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                                                                                                                                                                                             ; altsyncram_t8d1                               ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                                                                                            ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                                                                                                                                             ; cmpr_b06                                      ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                                                                                             ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                                                                                                                                              ; cmpr_b06                                      ; work         ;
;                   |dffpipe_qe9:ws_brp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                                                                                                                                                                                                   ; dffpipe_qe9                                   ; work         ;
;                   |dffpipe_qe9:ws_bwp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                                                                                                                                                   ; dffpipe_qe9                                   ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|                                                                                      ; 93 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX                                                                                                                                                                                                                                                                                                                         ; FTR_L1_FIFO                                   ; work         ;
;             |dcfifo:dcfifo_component|                                                                                                   ; 93 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                 ; dcfifo                                        ; work         ;
;                |dcfifo_jtr1:auto_generated|                                                                                             ; 93 (18)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                                                                                                                                                                                                      ; dcfifo_jtr1                                   ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                                                                                     ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                                                                                                                                      ; a_gray2bin_qab                                ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                                     ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                                                                                                                                      ; a_gray2bin_qab                                ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                                                                                         ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                                                                                                                                          ; a_graycounter_ldc                             ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                                                                                         ; 27 (27)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                                                                                                                                          ; a_graycounter_pv6                             ; work         ;
;                   |alt_synch_pipe_epl:rs_dgwp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp                                                                                                                                                                                                                                           ; alt_synch_pipe_epl                            ; work         ;
;                      |dffpipe_0f9:dffpipe6|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6                                                                                                                                                                                                                      ; dffpipe_0f9                                   ; work         ;
;                   |alt_synch_pipe_fpl:ws_dgrp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp                                                                                                                                                                                                                                           ; alt_synch_pipe_fpl                            ; work         ;
;                      |dffpipe_1f9:dffpipe9|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9                                                                                                                                                                                                                      ; dffpipe_1f9                                   ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                                                                                            ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                                                                                                                                                                                             ; altsyncram_t8d1                               ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                                                                                            ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                                                                                                                                             ; cmpr_b06                                      ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                                                                                             ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                                                                                                                                              ; cmpr_b06                                      ; work         ;
;                   |dffpipe_qe9:ws_brp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                                                                                                                                                                                                   ; dffpipe_qe9                                   ; work         ;
;                   |dffpipe_qe9:ws_bwp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                                                                                                                                                   ; dffpipe_qe9                                   ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|                                                                                      ; 93 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX                                                                                                                                                                                                                                                                                                                         ; FTR_L1_FIFO                                   ; work         ;
;             |dcfifo:dcfifo_component|                                                                                                   ; 93 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                 ; dcfifo                                        ; work         ;
;                |dcfifo_jtr1:auto_generated|                                                                                             ; 93 (18)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                                                                                                                                                                                                      ; dcfifo_jtr1                                   ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                                                                                     ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                                                                                                                                      ; a_gray2bin_qab                                ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                                     ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                                                                                                                                      ; a_gray2bin_qab                                ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                                                                                         ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                                                                                                                                          ; a_graycounter_ldc                             ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                                                                                         ; 27 (27)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                                                                                                                                          ; a_graycounter_pv6                             ; work         ;
;                   |alt_synch_pipe_epl:rs_dgwp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp                                                                                                                                                                                                                                           ; alt_synch_pipe_epl                            ; work         ;
;                      |dffpipe_0f9:dffpipe6|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6                                                                                                                                                                                                                      ; dffpipe_0f9                                   ; work         ;
;                   |alt_synch_pipe_fpl:ws_dgrp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp                                                                                                                                                                                                                                           ; alt_synch_pipe_fpl                            ; work         ;
;                      |dffpipe_1f9:dffpipe9|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9                                                                                                                                                                                                                      ; dffpipe_1f9                                   ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                                                                                            ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                                                                                                                                                                                             ; altsyncram_t8d1                               ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                                                                                            ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                                                                                                                                             ; cmpr_b06                                      ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                                                                                             ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                                                                                                                                              ; cmpr_b06                                      ; work         ;
;                   |dffpipe_qe9:ws_brp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                                                                                                                                                                                                   ; dffpipe_qe9                                   ; work         ;
;                   |dffpipe_qe9:ws_bwp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                                                                                                                                                   ; dffpipe_qe9                                   ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|                                                                                      ; 92 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX                                                                                                                                                                                                                                                                                                                         ; FTR_L1_FIFO                                   ; work         ;
;             |dcfifo:dcfifo_component|                                                                                                   ; 92 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                 ; dcfifo                                        ; work         ;
;                |dcfifo_jtr1:auto_generated|                                                                                             ; 92 (17)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                                                                                                                                                                                                      ; dcfifo_jtr1                                   ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                                                                                     ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                                                                                                                                      ; a_gray2bin_qab                                ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                                     ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                                                                                                                                      ; a_gray2bin_qab                                ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                                                                                         ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                                                                                                                                          ; a_graycounter_ldc                             ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                                                                                         ; 27 (27)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                                                                                                                                          ; a_graycounter_pv6                             ; work         ;
;                   |alt_synch_pipe_epl:rs_dgwp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp                                                                                                                                                                                                                                           ; alt_synch_pipe_epl                            ; work         ;
;                      |dffpipe_0f9:dffpipe6|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6                                                                                                                                                                                                                      ; dffpipe_0f9                                   ; work         ;
;                   |alt_synch_pipe_fpl:ws_dgrp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp                                                                                                                                                                                                                                           ; alt_synch_pipe_fpl                            ; work         ;
;                      |dffpipe_1f9:dffpipe9|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9                                                                                                                                                                                                                      ; dffpipe_1f9                                   ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                                                                                            ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                                                                                                                                                                                             ; altsyncram_t8d1                               ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                                                                                            ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                                                                                                                                             ; cmpr_b06                                      ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                                                                                             ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                                                                                                                                              ; cmpr_b06                                      ; work         ;
;                   |dffpipe_qe9:ws_brp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                                                                                                                                                                                                   ; dffpipe_qe9                                   ; work         ;
;                   |dffpipe_qe9:ws_bwp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                                                                                                                                                   ; dffpipe_qe9                                   ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|                                                                                      ; 92 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX                                                                                                                                                                                                                                                                                                                         ; FTR_L1_FIFO                                   ; work         ;
;             |dcfifo:dcfifo_component|                                                                                                   ; 92 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                 ; dcfifo                                        ; work         ;
;                |dcfifo_jtr1:auto_generated|                                                                                             ; 92 (17)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                                                                                                                                                                                                      ; dcfifo_jtr1                                   ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                                                                                     ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                                                                                                                                      ; a_gray2bin_qab                                ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                                     ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                                                                                                                                      ; a_gray2bin_qab                                ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                                                                                         ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                                                                                                                                          ; a_graycounter_ldc                             ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                                                                                         ; 27 (27)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                                                                                                                                          ; a_graycounter_pv6                             ; work         ;
;                   |alt_synch_pipe_epl:rs_dgwp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp                                                                                                                                                                                                                                           ; alt_synch_pipe_epl                            ; work         ;
;                      |dffpipe_0f9:dffpipe6|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6                                                                                                                                                                                                                      ; dffpipe_0f9                                   ; work         ;
;                   |alt_synch_pipe_fpl:ws_dgrp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp                                                                                                                                                                                                                                           ; alt_synch_pipe_fpl                            ; work         ;
;                      |dffpipe_1f9:dffpipe9|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9                                                                                                                                                                                                                      ; dffpipe_1f9                                   ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                                                                                            ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                                                                                                                                                                                             ; altsyncram_t8d1                               ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                                                                                            ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                                                                                                                                             ; cmpr_b06                                      ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                                                                                             ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                                                                                                                                              ; cmpr_b06                                      ; work         ;
;                   |dffpipe_qe9:ws_brp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                                                                                                                                                                                                   ; dffpipe_qe9                                   ; work         ;
;                   |dffpipe_qe9:ws_bwp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                                                                                                                                                   ; dffpipe_qe9                                   ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|                                                                                      ; 92 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX                                                                                                                                                                                                                                                                                                                         ; FTR_L1_FIFO                                   ; work         ;
;             |dcfifo:dcfifo_component|                                                                                                   ; 92 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                 ; dcfifo                                        ; work         ;
;                |dcfifo_jtr1:auto_generated|                                                                                             ; 92 (17)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                                                                                                                                                                                                      ; dcfifo_jtr1                                   ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                                                                                     ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                                                                                                                                      ; a_gray2bin_qab                                ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                                     ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                                                                                                                                      ; a_gray2bin_qab                                ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                                                                                         ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                                                                                                                                          ; a_graycounter_ldc                             ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                                                                                         ; 27 (27)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                                                                                                                                          ; a_graycounter_pv6                             ; work         ;
;                   |alt_synch_pipe_epl:rs_dgwp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp                                                                                                                                                                                                                                           ; alt_synch_pipe_epl                            ; work         ;
;                      |dffpipe_0f9:dffpipe6|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6                                                                                                                                                                                                                      ; dffpipe_0f9                                   ; work         ;
;                   |alt_synch_pipe_fpl:ws_dgrp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp                                                                                                                                                                                                                                           ; alt_synch_pipe_fpl                            ; work         ;
;                      |dffpipe_1f9:dffpipe9|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9                                                                                                                                                                                                                      ; dffpipe_1f9                                   ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                                                                                            ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                                                                                                                                                                                             ; altsyncram_t8d1                               ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                                                                                            ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                                                                                                                                             ; cmpr_b06                                      ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                                                                                             ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                                                                                                                                              ; cmpr_b06                                      ; work         ;
;                   |dffpipe_qe9:ws_brp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                                                                                                                                                                                                   ; dffpipe_qe9                                   ; work         ;
;                   |dffpipe_qe9:ws_bwp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                                                                                                                                                   ; dffpipe_qe9                                   ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|                                                                                      ; 92 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX                                                                                                                                                                                                                                                                                                                         ; FTR_L1_FIFO                                   ; work         ;
;             |dcfifo:dcfifo_component|                                                                                                   ; 92 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                 ; dcfifo                                        ; work         ;
;                |dcfifo_jtr1:auto_generated|                                                                                             ; 92 (17)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                                                                                                                                                                                                      ; dcfifo_jtr1                                   ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                                                                                     ; 10 (10)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                                                                                                                                                                                                      ; a_gray2bin_qab                                ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                                                                                     ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                                                                                                                                                                                                      ; a_gray2bin_qab                                ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                                                                                         ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                                                                                                                                                                                          ; a_graycounter_ldc                             ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                                                                                         ; 27 (27)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                                                                                                                                                                                          ; a_graycounter_pv6                             ; work         ;
;                   |alt_synch_pipe_epl:rs_dgwp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp                                                                                                                                                                                                                                           ; alt_synch_pipe_epl                            ; work         ;
;                      |dffpipe_0f9:dffpipe6|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6                                                                                                                                                                                                                      ; dffpipe_0f9                                   ; work         ;
;                   |alt_synch_pipe_fpl:ws_dgrp|                                                                                          ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp                                                                                                                                                                                                                                           ; alt_synch_pipe_fpl                            ; work         ;
;                      |dffpipe_1f9:dffpipe9|                                                                                             ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9                                                                                                                                                                                                                      ; dffpipe_1f9                                   ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                                                                                            ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                                                                                                                                                                                             ; altsyncram_t8d1                               ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                                                                                            ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                                                                                                                                                                                             ; cmpr_b06                                      ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                                                                                             ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                                                                                                                                                                                              ; cmpr_b06                                      ; work         ;
;                   |dffpipe_qe9:ws_brp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                                                                                                                                                                                                   ; dffpipe_qe9                                   ; work         ;
;                   |dffpipe_qe9:ws_bwp|                                                                                                  ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                                                                                                                                                                                                   ; dffpipe_qe9                                   ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED|                                                                           ; 105 (105)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED                                                                                                                                                                                                                                                                                                              ; FTR_RXDataModuleManager                       ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED|                                                                           ; 105 (105)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED                                                                                                                                                                                                                                                                                                              ; FTR_RXDataModuleManager                       ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED|                                                                           ; 106 (106)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED                                                                                                                                                                                                                                                                                                              ; FTR_RXDataModuleManager                       ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED|                                                                           ; 104 (104)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED                                                                                                                                                                                                                                                                                                              ; FTR_RXDataModuleManager                       ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED|                                                                           ; 105 (105)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED                                                                                                                                                                                                                                                                                                              ; FTR_RXDataModuleManager                       ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED|                                                                           ; 105 (105)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED                                                                                                                                                                                                                                                                                                              ; FTR_RXDataModuleManager                       ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED|                                                                           ; 105 (105)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED                                                                                                                                                                                                                                                                                                              ; FTR_RXDataModuleManager                       ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED|                                                                           ; 105 (105)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED                                                                                                                                                                                                                                                                                                              ; FTR_RXDataModuleManager                       ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX|                                                                         ; 104 (104)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX                                                                                                                                                                                                                                                                                                            ; FTR_RXDataModuleManager                       ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX|                                                                         ; 104 (104)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX                                                                                                                                                                                                                                                                                                            ; FTR_RXDataModuleManager                       ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX|                                                                         ; 104 (104)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX                                                                                                                                                                                                                                                                                                            ; FTR_RXDataModuleManager                       ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX|                                                                         ; 104 (104)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX                                                                                                                                                                                                                                                                                                            ; FTR_RXDataModuleManager                       ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX|                                                                         ; 105 (105)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX                                                                                                                                                                                                                                                                                                            ; FTR_RXDataModuleManager                       ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX|                                                                         ; 105 (105)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX                                                                                                                                                                                                                                                                                                            ; FTR_RXDataModuleManager                       ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX|                                                                         ; 106 (106)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX                                                                                                                                                                                                                                                                                                            ; FTR_RXDataModuleManager                       ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX|                                                                         ; 103 (103)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX                                                                                                                                                                                                                                                                                                            ; FTR_RXDataModuleManager                       ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|                                                                                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1                                                                                                                                                                                                                                                                                                                                                       ; USB_UC_PCLK                                   ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                                                                                            ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                                                                                                                                                                                                     ; altddio_out                                   ; work         ;
;             |ddio_out_b2j:auto_generated|                                                                                               ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                                                                                                                                                                                         ; ddio_out_b2j                                  ; work         ;
;    |FTR_L2_FIFO:C_L2_FIFO|                                                                                                              ; 202 (0)             ; 234 (0)                   ; 2097152           ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO                                                                                                                                                                                                                                                                                                                                                                                                     ; FTR_L2_FIFO                                   ; work         ;
;       |dcfifo:dcfifo_component|                                                                                                         ; 202 (0)             ; 234 (0)                   ; 2097152           ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component                                                                                                                                                                                                                                                                                                                                                                             ; dcfifo                                        ; work         ;
;          |dcfifo_kvr1:auto_generated|                                                                                                   ; 202 (37)            ; 234 (51)                  ; 2097152           ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated                                                                                                                                                                                                                                                                                                                                                  ; dcfifo_kvr1                                   ; work         ;
;             |a_gray2bin_vab:rdptr_g_gray2bin|                                                                                           ; 16 (16)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_gray2bin_vab:rdptr_g_gray2bin                                                                                                                                                                                                                                                                                                                  ; a_gray2bin_vab                                ; work         ;
;             |a_gray2bin_vab:rs_dgwp_gray2bin|                                                                                           ; 16 (16)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_gray2bin_vab:rs_dgwp_gray2bin                                                                                                                                                                                                                                                                                                                  ; a_gray2bin_vab                                ; work         ;
;             |a_gray2bin_vab:wrptr_g_gray2bin|                                                                                           ; 16 (16)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_gray2bin_vab:wrptr_g_gray2bin                                                                                                                                                                                                                                                                                                                  ; a_gray2bin_vab                                ; work         ;
;             |a_gray2bin_vab:ws_dgrp_gray2bin|                                                                                           ; 16 (16)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_gray2bin_vab:ws_dgrp_gray2bin                                                                                                                                                                                                                                                                                                                  ; a_gray2bin_vab                                ; work         ;
;             |a_graycounter_qdc:wrptr_g1p|                                                                                               ; 27 (27)             ; 21 (21)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_qdc:wrptr_g1p                                                                                                                                                                                                                                                                                                                      ; a_graycounter_qdc                             ; work         ;
;             |a_graycounter_uv6:rdptr_g1p|                                                                                               ; 35 (35)             ; 21 (21)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_uv6:rdptr_g1p                                                                                                                                                                                                                                                                                                                      ; a_graycounter_uv6                             ; work         ;
;             |alt_synch_pipe_gpl:rs_dgwp|                                                                                                ; 0 (0)               ; 34 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp                                                                                                                                                                                                                                                                                                                       ; alt_synch_pipe_gpl                            ; work         ;
;                |dffpipe_3f9:dffpipe15|                                                                                                  ; 0 (0)               ; 34 (34)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15                                                                                                                                                                                                                                                                                                 ; dffpipe_3f9                                   ; work         ;
;             |alt_synch_pipe_hpl:ws_dgrp|                                                                                                ; 0 (0)               ; 34 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp                                                                                                                                                                                                                                                                                                                       ; alt_synch_pipe_hpl                            ; work         ;
;                |dffpipe_4f9:dffpipe18|                                                                                                  ; 0 (0)               ; 34 (34)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18                                                                                                                                                                                                                                                                                                 ; dffpipe_4f9                                   ; work         ;
;             |altsyncram_29d1:fifo_ram|                                                                                                  ; 25 (3)              ; 9 (9)                     ; 2097152           ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram                                                                                                                                                                                                                                                                                                                         ; altsyncram_29d1                               ; work         ;
;                |decode_417:decode12|                                                                                                    ; 8 (8)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|decode_417:decode12                                                                                                                                                                                                                                                                                                     ; decode_417                                    ; work         ;
;                |mux_2t7:mux13|                                                                                                          ; 14 (14)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|mux_2t7:mux13                                                                                                                                                                                                                                                                                                           ; mux_2t7                                       ; work         ;
;             |cmpr_g06:rdempty_eq_comp|                                                                                                  ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|cmpr_g06:rdempty_eq_comp                                                                                                                                                                                                                                                                                                                         ; cmpr_g06                                      ; work         ;
;             |cmpr_g06:wrfull_eq_comp|                                                                                                   ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|cmpr_g06:wrfull_eq_comp                                                                                                                                                                                                                                                                                                                          ; cmpr_g06                                      ; work         ;
;             |dffpipe_2f9:rs_brp|                                                                                                        ; 0 (0)               ; 16 (16)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:rs_brp                                                                                                                                                                                                                                                                                                                               ; dffpipe_2f9                                   ; work         ;
;             |dffpipe_2f9:rs_bwp|                                                                                                        ; 0 (0)               ; 16 (16)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:rs_bwp                                                                                                                                                                                                                                                                                                                               ; dffpipe_2f9                                   ; work         ;
;             |dffpipe_2f9:ws_brp|                                                                                                        ; 0 (0)               ; 16 (16)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:ws_brp                                                                                                                                                                                                                                                                                                                               ; dffpipe_2f9                                   ; work         ;
;             |dffpipe_2f9:ws_bwp|                                                                                                        ; 0 (0)               ; 16 (16)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:ws_bwp                                                                                                                                                                                                                                                                                                                               ; dffpipe_2f9                                   ; work         ;
;    |FTR_REG_WRAPPER:C_REGS|                                                                                                             ; 118 (1)             ; 453 (0)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS                                                                                                                                                                                                                                                                                                                                                                                                    ; FTR_REG_WRAPPER                               ; work         ;
;       |UFP_USER_GET_CONFIG:C_CONFIG_USER_GET|                                                                                           ; 47 (47)             ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET                                                                                                                                                                                                                                                                                                                                                              ; UFP_USER_GET_CONFIG                           ; work         ;
;       |UFP_USER_GET_CONFIG:C_PHASE_USER_GET|                                                                                            ; 4 (4)               ; 20 (20)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET                                                                                                                                                                                                                                                                                                                                                               ; UFP_USER_GET_CONFIG                           ; work         ;
;       |UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET|                                                                                         ; 21 (21)             ; 22 (22)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET                                                                                                                                                                                                                                                                                                                                                            ; UFP_USER_GET_CONFIG                           ; work         ;
;       |UFP_USER_SETGET_ACK:C_GET_ACK|                                                                                                   ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SETGET_ACK:C_GET_ACK                                                                                                                                                                                                                                                                                                                                                                      ; UFP_USER_SETGET_ACK                           ; work         ;
;       |UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|                                                                                           ; 14 (14)             ; 124 (124)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET                                                                                                                                                                                                                                                                                                                                                              ; UFP_USER_SET_CONFIG                           ; work         ;
;       |UFP_USER_SET_CONFIG:C_PHASE_USER_SET|                                                                                            ; 4 (4)               ; 33 (33)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET                                                                                                                                                                                                                                                                                                                                                               ; UFP_USER_SET_CONFIG                           ; work         ;
;       |UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|                                                                                         ; 19 (19)             ; 184 (184)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET                                                                                                                                                                                                                                                                                                                                                            ; UFP_USER_SET_CONFIG                           ; work         ;
;       |UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|                                                                                         ; 7 (7)               ; 46 (46)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET                                                                                                                                                                                                                                                                                                                                                            ; UFP_USER_SET_CONFIG                           ; work         ;
;    |sld_hub:auto_hub|                                                                                                                   ; 112 (1)             ; 85 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|sld_hub:auto_hub                                                                                                                                                                                                                                                                                                                                                                                                          ; sld_hub                                       ; altera_sld   ;
;       |alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric| ; 111 (0)             ; 85 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric                                                                                                                                                                                                                                                                          ; alt_sld_fab_with_jtag_input                   ; altera_sld   ;
;          |alt_sld_fab:instrumentation_fabric|                                                                                           ; 111 (0)             ; 85 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric                                                                                                                                                                                                                                       ; alt_sld_fab                                   ; alt_sld_fab  ;
;             |alt_sld_fab_alt_sld_fab:alt_sld_fab|                                                                                       ; 111 (1)             ; 85 (6)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab                                                                                                                                                                                                   ; alt_sld_fab_alt_sld_fab                       ; alt_sld_fab  ;
;                |alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|                                                                            ; 110 (0)             ; 79 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric                                                                                                                                                       ; alt_sld_fab_alt_sld_fab_sldfabric             ; alt_sld_fab  ;
;                   |sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|                                                                        ; 110 (75)            ; 79 (51)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub                                                                                                          ; sld_jtag_hub                                  ; work         ;
;                      |sld_rom_sr:hub_info_reg|                                                                                          ; 16 (16)             ; 9 (9)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg                                                                                  ; sld_rom_sr                                    ; work         ;
;                      |sld_shadow_jsm:shadow_jsm|                                                                                        ; 19 (19)             ; 19 (19)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm                                                                                ; sld_shadow_jsm                                ; altera_sld   ;
+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+---------------------------------------------------------------------------+
; Name                                                                                                                                                                                                                                                                                                                                                                                                      ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size    ; MIF                                                                       ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+---------------------------------------------------------------------------+
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component|scfifo_7l91:auto_generated|a_dpfifo_er91:dpfifo|altsyncram_sqs1:FIFOram|ALTSYNCRAM                                                                                                                                                                                                                                  ; AUTO ; Simple Dual Port ; 64           ; 32           ; 64           ; 32           ; 2048    ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|altsyncram_cia1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                                                      ; AUTO ; Simple Dual Port ; 128          ; 32           ; 128          ; 32           ; 4096    ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|altsyncram_m8d1:fifo_ram|ALTSYNCRAM                                                                                             ; AUTO ; Simple Dual Port ; 2048         ; 32           ; 2048         ; 32           ; 65536   ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo|altsyncram:mem_rtl_0|altsyncram_23n1:auto_generated|ALTSYNCRAM                                                               ; AUTO ; Simple Dual Port ; 16           ; 42           ; 16           ; 42           ; 672     ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram|altsyncram:the_altsyncram|altsyncram_g572:auto_generated|ALTSYNCRAM                                                                                                                                                                                                              ; AUTO ; True Dual Port   ; 512          ; 32           ; 512          ; 32           ; 16384   ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_tx_dpram:enet_nios_tx_dpram|altsyncram:the_altsyncram|altsyncram_g572:auto_generated|ALTSYNCRAM                                                                                                                                                                                                              ; AUTO ; True Dual Port   ; 512          ; 32           ; 512          ; 32           ; 16384   ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|ALTSYNCRAM                                                                                                    ; AUTO ; Simple Dual Port ; 16           ; 128          ; 16           ; 128          ; 2048    ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated|a_dpfifo_b071:dpfifo|altsyncram_rgn1:FIFOram|ALTSYNCRAM                                                                                                             ; AUTO ; Simple Dual Port ; 32           ; 41           ; 32           ; 41           ; 1312    ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo|scfifo_p871:auto_generated|a_dpfifo_c071:dpfifo|altsyncram_tgn1:FIFOram|ALTSYNCRAM                                                                                                                                         ; AUTO ; Simple Dual Port ; 32           ; 42           ; 32           ; 42           ; 1344    ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|ALTSYNCRAM                                                                                                     ; AUTO ; Simple Dual Port ; 16           ; 128          ; 16           ; 128          ; 2048    ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo|altsyncram_3hn1:FIFOram|ALTSYNCRAM                                                                                                                                           ; AUTO ; Simple Dual Port ; 32           ; 45           ; 32           ; 45           ; 1440    ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram|altsyncram:the_altsyncram|altsyncram_dc72:auto_generated|ALTSYNCRAM                                                                                                                                                                                                                      ; AUTO ; True Dual Port   ; 1024         ; 32           ; 1024         ; 32           ; 32768   ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_sdpm_altsyncram:U_RAM|altsyncram:altsyncram_component|altsyncram_2vl1:auto_generated|ALTSYNCRAM                                                  ; AUTO ; Simple Dual Port ; 32           ; 10           ; 32           ; 10           ; 320     ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|ALTSYNCRAM                 ; AUTO ; Simple Dual Port ; 1024         ; 23           ; 1024         ; 23           ; 23552   ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_5ao1:auto_generated|ALTSYNCRAM             ; AUTO ; Simple Dual Port ; 4096         ; 40           ; 4096         ; 40           ; 163840  ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_altshifttaps:U_SHIFTTAPS|altshift_taps:shift_reg_rtl_0|shift_taps_ffv:auto_generated|altsyncram_1r91:altsyncram4|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16           ; 8            ; 16           ; 8            ; 128     ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_n0o1:auto_generated|ALTSYNCRAM                 ; AUTO ; Simple Dual Port ; 512          ; 2            ; 512          ; 2            ; 1024    ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_3ao1:auto_generated|ALTSYNCRAM             ; AUTO ; Simple Dual Port ; 2048         ; 36           ; 2048         ; 36           ; 73728   ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|altsyncram_7pu1:FIFOram|ALTSYNCRAM                                                                                                                                      ; AUTO ; Simple Dual Port ; 64           ; 8            ; 64           ; 8            ; 512     ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|altsyncram_7pu1:FIFOram|ALTSYNCRAM                                                                                                                                      ; AUTO ; Simple Dual Port ; 64           ; 8            ; 64           ; 8            ; 512     ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_qid1:auto_generated|ALTSYNCRAM                           ; AUTO ; Single Port      ; 256          ; 32           ; --           ; --           ; 8192    ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_msi1:auto_generated|ALTSYNCRAM                                                                                                                                             ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024    ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_b_module:nios2_nios2_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_msi1:auto_generated|ALTSYNCRAM                                                                                                                                             ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024    ; None                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram|altsyncram_pnr1:auto_generated|ALTSYNCRAM                                                                                                                                                                                                                              ; AUTO ; Single Port      ; 32768        ; 32           ; --           ; --           ; 1048576 ; J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                    ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None                                                                      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                    ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None                                                                      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                    ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None                                                                      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                    ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None                                                                      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                    ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None                                                                      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                    ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None                                                                      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                    ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None                                                                      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                    ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None                                                                      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                  ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None                                                                      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                  ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None                                                                      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                  ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None                                                                      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                  ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None                                                                      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                  ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None                                                                      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                  ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None                                                                      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                  ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None                                                                      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                  ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None                                                                      ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|ALTSYNCRAM                                                                                                                                                                                                                                                                                              ; AUTO ; Simple Dual Port ; 65536        ; 33           ; 65536        ; 33           ; 2162688 ; None                                                                      ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+---------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+--------+---------------------------------+---------+--------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+
; Vendor ; IP Core Name                    ; Version ; Release Date ; License Type ; Entity Instance                                                                                                                                                                                                                                                                                                                             ; IP Include File                                                  ;
+--------+---------------------------------+---------+--------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+
; Altera ; Signal Tap                      ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric                                                                                                                                                ;                                                                  ;
; Altera ; Signal Tap                      ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab                                                                                                            ;                                                                  ;
; Altera ; Signal Tap                      ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_presplit:presplit                                                                  ;                                                                  ;
; Altera ; Signal Tap                      ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric                                                                ;                                                                  ;
; Altera ; Signal Tap                      ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_splitter:splitter                                                                  ;                                                                  ;
; Altera ; altera_pll                      ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL                                                                                                                                                                                                                                                                                       ; ../src/PLL_MAIN.vhd                                              ;
; Altera ; altera_pll                      ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4                                                                                                                                                                                                                                                                                        ; ../src/PLL_4K.vhd                                                ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO                                                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/src/ETH_MSGDMA_IRQ_FIFO.vhd ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK                                                                                                                                                                                                                                                  ; ../../../lib/eth_ethernet/c_cyclone5/src/ETH_TX_CLK.vhd          ;
; N/A    ; Qsys                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS                                                                                                                                                                                                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter                                                                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; timing_adapter                  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0                                                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_onchip_memory2    ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram                                                                                                                                                                                                           ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_onchip_memory2    ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_tx_dpram:enet_nios_tx_dpram                                                                                                                                                                                                           ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_msgdma                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma                                                                                                                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; modular_sgdma_dispatcher        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal                                                                                                                                                                                    ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; dma_write_master                ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal                                                                                                                                                                                  ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_msgdma                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma                                                                                                                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; modular_sgdma_dispatcher        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal                                                                                                                                                                                    ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; dma_read_master                 ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal                                                                                                                                                                                    ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_onchip_memory2    ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram                                                                                                                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_eth_tse                  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac                                                                                                                                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac                                                                                                                                                                                            ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL                                                                                                                                                       ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL                                                                                                                        ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG                                                                                                                         ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL                                                                                   ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL                                                                                     ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP                                                                                                                                                ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT                                                                                                                    ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_gmii_io:U_GMIF                                                                                                                      ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF                                                                                                                  ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF                                                                                      ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_sdpm_altsyncram:U_RAM                                                     ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD                                                             ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT                                                            ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_read_cntl:U_LBR                                                                                    ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_wrt_cntl:U_LBW                                                                                     ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC                                                                                                                    ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH                                                                                        ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX                                                                 ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_crc328checker:U_CRC                                  ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_crc328checker:U_CRC|altera_tse_crc32galois8:U_GALS   ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_altshifttaps:U_SHIFTTAPS                             ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT                                                    ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX                                                                 ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC                                ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|altera_tse_crc32ctl8:U_CTL     ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|altera_tse_crc32galois8:U_GALS ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_tx_stat_extract:U_TXSTAT                                                    ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF                                                                                        ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA                                                     ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM                ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD                            ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT                           ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS                                                         ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM                    ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_bin_cnt:U_RD                                 ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT                               ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF                                                                                        ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA                                                     ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM                ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD                            ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT                           ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS                                                         ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM                    ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_RD                                ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT                               ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM                                                  ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_rx_if:U_MRX                                                                                                                     ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_tx_if:U_MTX                                                                                                                     ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO                                                                                                                                                                 ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_clk_gen:U_CLKGEN                                                                                                                                ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_cntl:U_CNTL                                                                                                                                     ;                                                                  ;
; Altera ; Triple-Speed Ethernet           ; N/A     ; N/A          ; Licensed     ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio:U_MDIO                                                                                                                                          ;                                                                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_daq_dest_ip_addr:daq_dest_ip_addr                                                                                                                                                                           ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_CTRL:daq_dest_mac_addr_h                                                                                                                                                                                           ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_daq_dest_ip_addr:daq_dest_mac_addr_l                                                                                                                                                                        ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_mm_bridge         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_avalon_mm_bridge:if_bridge                                                                                                                                                                                           ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_mm_interconnect          ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0                                                                                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_004                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_004|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_014                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_014|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_demux:cmd_demux                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_mux:cmd_mux                                                                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_mux:cmd_mux_001                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_mux:cmd_mux_002                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_mux:cmd_mux_003                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_mux:cmd_mux_004                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_mux:cmd_mux_005                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_mux:cmd_mux_006                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_mux:cmd_mux_007                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_mux:cmd_mux_008                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_mux:cmd_mux_009                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_mux:cmd_mux_010                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_mux:cmd_mux_011                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_mux:cmd_mux_012                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_mux:cmd_mux_013                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_mux:cmd_mux_014                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_ip_addr_s1_agent                                                                                                                     ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo                                                                                                                ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_ip_addr_s1_translator                                                                                                           ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_h_s1_agent                                                                                                                  ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_h_s1_translator                                                                                                        ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_l_s1_agent                                                                                                                  ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_l_s1_translator                                                                                                        ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_master_agent      ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:if_bridge_m0_agent                                                                                                                           ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_traffic_limiter   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:if_bridge_m0_limiter                                                                                                                      ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_master_translator ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:if_bridge_m0_translator                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_in_s1_agent                                                                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo                                                                                                                  ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_s1_agent                                                                                                                          ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo                                                                                                                     ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_s1_translator                                                                                                                ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_in_s1_agent                                                                                                                    ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator                                                                                                          ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_s1_agent                                                                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo                                                                                                                  ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_s1_translator                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_in_s1_agent                                                                                                                    ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator                                                                                                          ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_s1_agent                                                                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo                                                                                                                  ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_s1_translator                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:rot_switch_s1_agent                                                                                                                           ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo                                                                                                                      ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router:router                                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_001                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_002                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_003                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_004                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_005                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_006                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_007                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_008                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_009                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_010                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_011                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_012                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_013                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_014                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_015                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_001                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_002                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_003                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_004                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_005                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_006                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_007                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_008                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_009                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_010                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_011                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_012                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_013                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_014                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_mux:rsp_mux                                                                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_ip_addr_s1_agent                                                                                                                      ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_ip_addr_s1_translator                                                                                                            ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_h_s1_agent                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo                                                                                                              ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_h_s1_translator                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_l_s1_agent                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo                                                                                                              ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_l_s1_translator                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:testing_s1_agent                                                                                                                              ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo                                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:testing_s1_translator                                                                                                                    ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:version_s1_agent                                                                                                                              ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo                                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:version_s1_translator                                                                                                                    ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_daq_dest_ip_addr:own_ip_addr                                                                                                                                                                                ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in                                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_CTRL:own_mac_addr_h                                                                                                                                                                                                ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in                                                                                                                                                                                           ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_daq_dest_ip_addr:own_mac_addr_l                                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in                                                                                                                                                                            ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch                                                                                                                                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_reset_controller         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller                                                                                                                                                                                      ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_daq_dest_ip_addr:sc_dest_ip_addr                                                                                                                                                                            ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_CTRL:sc_dest_mac_addr_h                                                                                                                                                                                            ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_daq_dest_ip_addr:sc_dest_mac_addr_l                                                                                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_CTRL:testing                                                                                                                                                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_CTRL:version                                                                                                                                                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_irq_mapper               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_irq_mapper:irq_mapper                                                                                                                                                                                                                           ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_jtag_uart         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0                                                                                                                                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_mm_interconnect          ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0                                                                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter_004:avalon_st_adapter_004                                                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter_004:avalon_st_adapter_004|nios2_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0:error_adapter_0                                                           ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux:cmd_demux                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux_001:cmd_demux_001                                                                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux:cmd_mux                                                                                                                                                                     ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux:cmd_mux_001                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux:cmd_mux_002                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux:cmd_mux_004                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux:cmd_mux_005                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux:cmd_mux_006                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux:cmd_mux_007                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux:cmd_mux_008                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_009                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux:cmd_mux_010                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux:cmd_mux_011                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux:cmd_mux_012                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux:cmd_mux_013                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_rx_dpram_s1_agent                                                                                                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo                                                                                                                                                  ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_rx_dpram_s1_translator                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_tx_dpram_s1_agent                                                                                                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo                                                                                                                                                  ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_tx_dpram_s1_translator                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_csr_agent                                                                                                                                                          ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo                                                                                                                                                     ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_csr_translator                                                                                                                                                ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_descriptor_slave_agent                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo                                                                                                                                        ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_width_adapter     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_width_adapter     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_rsp_width_adapter                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator                                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_response_agent                                                                                                                                                     ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo                                                                                                                                                ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_response_translator                                                                                                                                           ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:eth_tse_mac_control_port_agent                                                                                                                                                    ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:eth_tse_mac_control_port_translator                                                                                                                                          ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fabric_if_if_bridge_slave_agent                                                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo                                                                                                                                              ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fabric_if_if_bridge_slave_translator                                                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo                                                                                                                                          ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator                                                                                                                                     ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_master_agent      ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_data_master_agent                                                                                                                                                          ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_master_translator ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_data_master_translator                                                                                                                                                ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:nios2_debug_mem_slave_agent                                                                                                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo                                                                                                                                                  ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:nios2_debug_mem_slave_translator                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_master_agent      ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_instruction_master_agent                                                                                                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_master_translator ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_instruction_master_translator                                                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:onchip_mem_s1_agent                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo                                                                                                                                                          ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:onchip_mem_s1_translator                                                                                                                                                     ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router:router                                                                                                                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_001:router_001                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_002                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_003                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_004                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_005:router_005                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_006:router_006                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_007                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_008                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_009                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_010                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_005:router_011                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_012                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_013                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_014                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_015                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_001                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_002                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux_001:rsp_demux_003                                                                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_004                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_005                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_006                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_007                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_008                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux_001:rsp_demux_009                                                                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_010                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_011                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_012                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_013                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux:rsp_mux                                                                                                                                                                     ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux_001:rsp_mux_001                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_agent                                                                                                                                                              ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo                                                                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_csr_agent                                                                                                                                                          ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo                                                                                                                                                     ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator                                                                                                                                                ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator                                                                                                                                                    ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_ctrl_s1_agent                                                                                                                                                                  ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_ctrl_s1_translator                                                                                                                                                        ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_status_s1_agent                                                                                                                                                                ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo                                                                                                                                                           ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator                                                                                                                                                      ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_mm_interconnect          ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1                                                                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_st_adapter        ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; error_adapter                   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0                                                                   ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_cmd_demux:cmd_demux                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_cmd_mux:cmd_mux                                                                                                                                                                     ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_cmd_mux:cmd_mux_001                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_nios_tx_dpram_s2_agent                                                                                                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo                                                                                                                                                  ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_nios_tx_dpram_s2_translator                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_master_agent      ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_agent:enet_tx_msgdma_mm_read_agent                                                                                                                                                     ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_traffic_limiter   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_traffic_limiter:enet_tx_msgdma_mm_read_limiter                                                                                                                                                ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_master_translator ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_translator:enet_tx_msgdma_mm_read_translator                                                                                                                                           ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_agent       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_udp_dpram_s2_agent                                                                                                                                                           ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_sc_fifo           ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo                                                                                                                                                      ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_udp_dpram_s2_translator                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router:router                                                                                                                                                                       ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router_001:router_001                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_router            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router_001:router_002                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_rsp_demux:rsp_demux                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_demultiplexer     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_rsp_demux:rsp_demux_001                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_multiplexer       ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_rsp_mux:rsp_mux                                                                                                                                                                     ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_mm_interconnect          ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_2:mm_interconnect_2                                                                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_slave_translator  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_2:mm_interconnect_2|altera_merlin_slave_translator:enet_nios_rx_dpram_s2_translator                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_merlin_master_translator ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_2:mm_interconnect_2|altera_merlin_master_translator:enet_rx_msgdma_mm_write_translator                                                                                                                                          ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_nios2_gen2               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2                                                                                                                                                                                                                                     ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_nios2_gen2_unit          ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu                                                                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_onchip_memory2    ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem                                                                                                                                                                                                                           ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_pll                      ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_pll_enet:pll_enet                                                                                                                                                                                                                               ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_reset_controller         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller                                                                                                                                                                                                                ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_reset_controller         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001                                                                                                                                                                                                            ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_reset_controller         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002                                                                                                                                                                                                            ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_fifo              ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx                                                                                                                                                                                                                         ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_CTRL:tx_ctrl                                                                                                                                                                                                                                 ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; altera_avalon_pio               ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status                                                                                                                                                                                                                             ; ../../../lib/eth_ethernet/c_cyclone5/nios2.qsys                  ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX                                                                                                                                                                                                                                                                      ; ../../../lib/eth_ethernet/c_cyclone5/src/ETH_SC_FIFO_RX.vhd      ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX                                                                                                                                                                                                                                                                      ; ../../../lib/eth_ethernet/c_cyclone5/src/ETH_SC_FIFO_TX.vhd      ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO                                                                                                                                                                                                                                                                                                              ; ../src/FTR_L2_FIFO.vhd                                           ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; ALTDDIO_OUT                     ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1                                                                                                                                                                                                                                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd              ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED                                                                                                                                                                                                                                    ; ../src/FTR_L1_FIFO.vhd                                           ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED                                                                                                                                                                                                                                    ; ../src/FTR_L1_FIFO.vhd                                           ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED                                                                                                                                                                                                                                    ; ../src/FTR_L1_FIFO.vhd                                           ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED                                                                                                                                                                                                                                    ; ../src/FTR_L1_FIFO.vhd                                           ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED                                                                                                                                                                                                                                    ; ../src/FTR_L1_FIFO.vhd                                           ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED                                                                                                                                                                                                                                    ; ../src/FTR_L1_FIFO.vhd                                           ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED                                                                                                                                                                                                                                    ; ../src/FTR_L1_FIFO.vhd                                           ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED                                                                                                                                                                                                                                    ; ../src/FTR_L1_FIFO.vhd                                           ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX                                                                                                                                                                                                                                  ; ../src/FTR_L1_FIFO.vhd                                           ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX                                                                                                                                                                                                                                  ; ../src/FTR_L1_FIFO.vhd                                           ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX                                                                                                                                                                                                                                  ; ../src/FTR_L1_FIFO.vhd                                           ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX                                                                                                                                                                                                                                  ; ../src/FTR_L1_FIFO.vhd                                           ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX                                                                                                                                                                                                                                  ; ../src/FTR_L1_FIFO.vhd                                           ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX                                                                                                                                                                                                                                  ; ../src/FTR_L1_FIFO.vhd                                           ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX                                                                                                                                                                                                                                  ; ../src/FTR_L1_FIFO.vhd                                           ;
; Altera ; FIFO                            ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX                                                                                                                                                                                                                                  ; ../src/FTR_L1_FIFO.vhd                                           ;
+--------+---------------------------------+---------+--------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|state     ;
+---------------------------+--------------------------+--------------------------+---------------------------+-------------------------+---------------------------+---------------------------+--------------------------+---------------------+
; Name                      ; state.STM_TYPE_STAT_READ ; state.STM_TYPE_WAIT_BUSY ; state.STM_TYPE_WAIT_CYCLE ; state.STM_TYPE_END_READ ; state.STM_TYPE_NEXT_CYCLE ; state.STM_TYPE_MDIO_WRITE ; state.STM_TYPE_MDIO_READ ; state.STM_TYPE_IDLE ;
+---------------------------+--------------------------+--------------------------+---------------------------+-------------------------+---------------------------+---------------------------+--------------------------+---------------------+
; state.STM_TYPE_IDLE       ; 0                        ; 0                        ; 0                         ; 0                       ; 0                         ; 0                         ; 0                        ; 0                   ;
; state.STM_TYPE_MDIO_READ  ; 0                        ; 0                        ; 0                         ; 0                       ; 0                         ; 0                         ; 1                        ; 1                   ;
; state.STM_TYPE_MDIO_WRITE ; 0                        ; 0                        ; 0                         ; 0                       ; 0                         ; 1                         ; 0                        ; 1                   ;
; state.STM_TYPE_NEXT_CYCLE ; 0                        ; 0                        ; 0                         ; 0                       ; 1                         ; 0                         ; 0                        ; 1                   ;
; state.STM_TYPE_END_READ   ; 0                        ; 0                        ; 0                         ; 1                       ; 0                         ; 0                         ; 0                        ; 1                   ;
; state.STM_TYPE_WAIT_CYCLE ; 0                        ; 0                        ; 1                         ; 0                       ; 0                         ; 0                         ; 0                        ; 1                   ;
; state.STM_TYPE_WAIT_BUSY  ; 0                        ; 1                        ; 0                         ; 0                       ; 0                         ; 0                         ; 0                        ; 1                   ;
; state.STM_TYPE_STAT_READ  ; 1                        ; 0                        ; 0                         ; 0                       ; 0                         ; 0                         ; 0                        ; 1                   ;
+---------------------------+--------------------------+--------------------------+---------------------------+-------------------------+---------------------------+---------------------------+--------------------------+---------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX|sl_int_state                        ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX|sl_int_state                        ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX|sl_int_state                        ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX|sl_int_state                        ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED|sl_int_state                          ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED|sl_int_state                          ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED|sl_int_state                          ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED|sl_int_state                          ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|sl_int_detect_state[1]                                                         ;
+---------------------------------+---------------------------------+---------------------------------+------------------------------+
; Name                            ; sl_int_detect_state[1].STARTED1 ; sl_int_detect_state[1].STARTED0 ; sl_int_detect_state[1].RESET ;
+---------------------------------+---------------------------------+---------------------------------+------------------------------+
; sl_int_detect_state[1].RESET    ; 0                               ; 0                               ; 0                            ;
; sl_int_detect_state[1].STARTED0 ; 0                               ; 1                               ; 1                            ;
; sl_int_detect_state[1].STARTED1 ; 1                               ; 0                               ; 1                            ;
+---------------------------------+---------------------------------+---------------------------------+------------------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|sl_int_detect_state[0]                                                         ;
+---------------------------------+---------------------------------+---------------------------------+------------------------------+
; Name                            ; sl_int_detect_state[0].STARTED1 ; sl_int_detect_state[0].STARTED0 ; sl_int_detect_state[0].RESET ;
+---------------------------------+---------------------------------+---------------------------------+------------------------------+
; sl_int_detect_state[0].RESET    ; 0                               ; 0                               ; 0                            ;
; sl_int_detect_state[0].STARTED0 ; 0                               ; 1                               ; 1                            ;
; sl_int_detect_state[0].STARTED1 ; 1                               ; 0                               ; 1                            ;
+---------------------------------+---------------------------------+---------------------------------+------------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|sl_int_state                                                                                                      ;
+-----------------------------+---------------------+--------------------+-----------------------------+--------------------------+--------------------+-------------------+
; Name                        ; sl_int_state.CLEAR2 ; sl_int_state.CLEAR ; sl_int_state.FORCED_INT_CLK ; sl_int_state.WAIT_LOCKED ; sl_int_state.RESET ; sl_int_state.IDLE ;
+-----------------------------+---------------------+--------------------+-----------------------------+--------------------------+--------------------+-------------------+
; sl_int_state.IDLE           ; 0                   ; 0                  ; 0                           ; 0                        ; 0                  ; 0                 ;
; sl_int_state.RESET          ; 0                   ; 0                  ; 0                           ; 0                        ; 1                  ; 1                 ;
; sl_int_state.WAIT_LOCKED    ; 0                   ; 0                  ; 0                           ; 1                        ; 0                  ; 1                 ;
; sl_int_state.FORCED_INT_CLK ; 0                   ; 0                  ; 1                           ; 0                        ; 0                  ; 1                 ;
; sl_int_state.CLEAR          ; 0                   ; 1                  ; 0                           ; 0                        ; 0                  ; 1                 ;
; sl_int_state.CLEAR2         ; 1                   ; 0                  ; 0                           ; 0                        ; 0                  ; 1                 ;
+-----------------------------+---------------------+--------------------+-----------------------------+--------------------------+--------------------+-------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE|sl_int_state                                                                                  ;
+------------------------------+------------------------+------------------------+------------------------+------------------------------+------------------------+-------------------+
; Name                         ; sl_int_state.PHASE_EN1 ; sl_int_state.PHASE_EN0 ; sl_int_state.PHASE_DIS ; sl_int_state.PLL_WAIT_LOCKED ; sl_int_state.PLL_RESET ; sl_int_state.IDLE ;
+------------------------------+------------------------+------------------------+------------------------+------------------------------+------------------------+-------------------+
; sl_int_state.IDLE            ; 0                      ; 0                      ; 0                      ; 0                            ; 0                      ; 0                 ;
; sl_int_state.PLL_RESET       ; 0                      ; 0                      ; 0                      ; 0                            ; 1                      ; 1                 ;
; sl_int_state.PLL_WAIT_LOCKED ; 0                      ; 0                      ; 0                      ; 1                            ; 0                      ; 1                 ;
; sl_int_state.PHASE_DIS       ; 0                      ; 0                      ; 1                      ; 0                            ; 0                      ; 1                 ;
; sl_int_state.PHASE_EN0       ; 0                      ; 1                      ; 0                      ; 0                            ; 0                      ; 1                 ;
; sl_int_state.PHASE_EN1       ; 1                      ; 0                      ; 0                      ; 0                            ; 0                      ; 1                 ;
+------------------------------+------------------------+------------------------+------------------------+------------------------------+------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state                                                                                            ;
+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+-----------------------------------+
; Name                               ; dps_current_state.PHASE_DONE_LOW_0 ; dps_current_state.PHASE_DONE_LOW_4 ; dps_current_state.PHASE_DONE_LOW_3 ; dps_current_state.PHASE_DONE_LOW_2 ; dps_current_state.PHASE_DONE_LOW_1 ; dps_current_state.PHASE_DONE_HIGH ;
+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+-----------------------------------+
; dps_current_state.PHASE_DONE_HIGH  ; 0                                  ; 0                                  ; 0                                  ; 0                                  ; 0                                  ; 0                                 ;
; dps_current_state.PHASE_DONE_LOW_1 ; 0                                  ; 0                                  ; 0                                  ; 0                                  ; 1                                  ; 1                                 ;
; dps_current_state.PHASE_DONE_LOW_2 ; 0                                  ; 0                                  ; 0                                  ; 1                                  ; 0                                  ; 1                                 ;
; dps_current_state.PHASE_DONE_LOW_3 ; 0                                  ; 0                                  ; 1                                  ; 0                                  ; 0                                  ; 1                                 ;
; dps_current_state.PHASE_DONE_LOW_4 ; 0                                  ; 1                                  ; 0                                  ; 0                                  ; 0                                  ; 1                                 ;
; dps_current_state.PHASE_DONE_LOW_0 ; 1                                  ; 0                                  ; 0                                  ; 0                                  ; 0                                  ; 1                                 ;
+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+-----------------------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX|sl_int_state                        ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX|sl_int_state                        ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX|sl_int_state                        ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX|sl_int_state                        ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED|sl_int_state                          ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED|sl_int_state                          ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED|sl_int_state                          ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED|sl_int_state                          ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_state                                                                                                                                                                                                                                                                       ;
+-----------------------------------+-------------------+--------------------------+-------------------------------+---------------------------+---------------------------------+-----------------------------------+-----------------------------------+----------------------------+-------------------------+----------------------+-------------------+
; Name                              ; sl_int_state.STOP ; sl_int_state.TRB_TRAILER ; sl_int_state.TRB_TRAILER_WAIT ; sl_int_state.READ_L1_FIFO ; sl_int_state.TRB_DATA_FIFO_FULL ; sl_int_state.TRB_DATA_TIMEOUT_END ; sl_int_state.TRB_DATA_TIMEOUT_L1A ; sl_int_state.TRB_DATA_BCID ; sl_int_state.TRB_HEADER ; sl_int_state.RECEIVE ; sl_int_state.IDLE ;
+-----------------------------------+-------------------+--------------------------+-------------------------------+---------------------------+---------------------------------+-----------------------------------+-----------------------------------+----------------------------+-------------------------+----------------------+-------------------+
; sl_int_state.IDLE                 ; 0                 ; 0                        ; 0                             ; 0                         ; 0                               ; 0                                 ; 0                                 ; 0                          ; 0                       ; 0                    ; 0                 ;
; sl_int_state.RECEIVE              ; 0                 ; 0                        ; 0                             ; 0                         ; 0                               ; 0                                 ; 0                                 ; 0                          ; 0                       ; 1                    ; 1                 ;
; sl_int_state.TRB_HEADER           ; 0                 ; 0                        ; 0                             ; 0                         ; 0                               ; 0                                 ; 0                                 ; 0                          ; 1                       ; 0                    ; 1                 ;
; sl_int_state.TRB_DATA_BCID        ; 0                 ; 0                        ; 0                             ; 0                         ; 0                               ; 0                                 ; 0                                 ; 1                          ; 0                       ; 0                    ; 1                 ;
; sl_int_state.TRB_DATA_TIMEOUT_L1A ; 0                 ; 0                        ; 0                             ; 0                         ; 0                               ; 0                                 ; 1                                 ; 0                          ; 0                       ; 0                    ; 1                 ;
; sl_int_state.TRB_DATA_TIMEOUT_END ; 0                 ; 0                        ; 0                             ; 0                         ; 0                               ; 1                                 ; 0                                 ; 0                          ; 0                       ; 0                    ; 1                 ;
; sl_int_state.TRB_DATA_FIFO_FULL   ; 0                 ; 0                        ; 0                             ; 0                         ; 1                               ; 0                                 ; 0                                 ; 0                          ; 0                       ; 0                    ; 1                 ;
; sl_int_state.READ_L1_FIFO         ; 0                 ; 0                        ; 0                             ; 1                         ; 0                               ; 0                                 ; 0                                 ; 0                          ; 0                       ; 0                    ; 1                 ;
; sl_int_state.TRB_TRAILER_WAIT     ; 0                 ; 0                        ; 1                             ; 0                         ; 0                               ; 0                                 ; 0                                 ; 0                          ; 0                       ; 0                    ; 1                 ;
; sl_int_state.TRB_TRAILER          ; 0                 ; 1                        ; 0                             ; 0                         ; 0                               ; 0                                 ; 0                                 ; 0                          ; 0                       ; 0                    ; 1                 ;
; sl_int_state.STOP                 ; 1                 ; 0                        ; 0                             ; 0                         ; 0                               ; 0                                 ; 0                                 ; 0                          ; 0                       ; 0                    ; 1                 ;
+-----------------------------------+-------------------+--------------------------+-------------------------------+---------------------------+---------------------------------+-----------------------------------+-----------------------------------+----------------------------+-------------------------+----------------------+-------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_mux                                                                                                                                                                                                                                                                 ;
+----------------------------------------+----------------------------------------+-----------------+------------------------+-------------------------+-------------------------------+---------------------------------+---------------------------------+--------------------------+-----------------------+------------------+-----------------+
; Name                                   ; sl_int_mux.TRB_DATA_L1A_FIFO_NOT_EMPTY ; sl_int_mux.STOP ; sl_int_mux.TRB_TRAILER ; sl_int_mux.READ_L1_FIFO ; sl_int_mux.TRB_DATA_FIFO_FULL ; sl_int_mux.TRB_DATA_TIMEOUT_END ; sl_int_mux.TRB_DATA_TIMEOUT_L1A ; sl_int_mux.TRB_DATA_BCID ; sl_int_mux.TRB_HEADER ; sl_int_mux.START ; sl_int_mux.NONE ;
+----------------------------------------+----------------------------------------+-----------------+------------------------+-------------------------+-------------------------------+---------------------------------+---------------------------------+--------------------------+-----------------------+------------------+-----------------+
; sl_int_mux.NONE                        ; 0                                      ; 0               ; 0                      ; 0                       ; 0                             ; 0                               ; 0                               ; 0                        ; 0                     ; 0                ; 0               ;
; sl_int_mux.START                       ; 0                                      ; 0               ; 0                      ; 0                       ; 0                             ; 0                               ; 0                               ; 0                        ; 0                     ; 1                ; 1               ;
; sl_int_mux.TRB_HEADER                  ; 0                                      ; 0               ; 0                      ; 0                       ; 0                             ; 0                               ; 0                               ; 0                        ; 1                     ; 0                ; 1               ;
; sl_int_mux.TRB_DATA_BCID               ; 0                                      ; 0               ; 0                      ; 0                       ; 0                             ; 0                               ; 0                               ; 1                        ; 0                     ; 0                ; 1               ;
; sl_int_mux.TRB_DATA_TIMEOUT_L1A        ; 0                                      ; 0               ; 0                      ; 0                       ; 0                             ; 0                               ; 1                               ; 0                        ; 0                     ; 0                ; 1               ;
; sl_int_mux.TRB_DATA_TIMEOUT_END        ; 0                                      ; 0               ; 0                      ; 0                       ; 0                             ; 1                               ; 0                               ; 0                        ; 0                     ; 0                ; 1               ;
; sl_int_mux.TRB_DATA_FIFO_FULL          ; 0                                      ; 0               ; 0                      ; 0                       ; 1                             ; 0                               ; 0                               ; 0                        ; 0                     ; 0                ; 1               ;
; sl_int_mux.READ_L1_FIFO                ; 0                                      ; 0               ; 0                      ; 1                       ; 0                             ; 0                               ; 0                               ; 0                        ; 0                     ; 0                ; 1               ;
; sl_int_mux.TRB_TRAILER                 ; 0                                      ; 0               ; 1                      ; 0                       ; 0                             ; 0                               ; 0                               ; 0                        ; 0                     ; 0                ; 1               ;
; sl_int_mux.STOP                        ; 0                                      ; 1               ; 0                      ; 0                       ; 0                             ; 0                               ; 0                               ; 0                        ; 0                     ; 0                ; 1               ;
; sl_int_mux.TRB_DATA_L1A_FIFO_NOT_EMPTY ; 1                                      ; 0               ; 0                      ; 0                       ; 0                             ; 0                               ; 0                               ; 0                        ; 0                     ; 0                ; 1               ;
+----------------------------------------+----------------------------------------+-----------------+------------------------+-------------------------+-------------------------------+---------------------------------+---------------------------------+--------------------------+-----------------------+------------------+-----------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_state ;
+-------------------------+---------------------+----------------------+---------------------------------------------------+
; Name                    ; sl_int_state.CRC_AV ; sl_int_state.COMPUTE ; sl_int_state.WAIT_START                           ;
+-------------------------+---------------------+----------------------+---------------------------------------------------+
; sl_int_state.WAIT_START ; 0                   ; 0                    ; 0                                                 ;
; sl_int_state.COMPUTE    ; 0                   ; 1                    ; 1                                                 ;
; sl_int_state.CRC_AV     ; 1                   ; 0                    ; 1                                                 ;
+-------------------------+---------------------+----------------------+---------------------------------------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_chk_state                                                                                                                                        ;
+-------------------------------------+----------------------+-------------------------------------+---------------------------------+-------------------------------+-------------------------------+---------------------------+---------------------------+----------------------------+-----------------------+
; Name                                ; sl_int_chk_state.ACK ; sl_int_chk_state.COMPUTE_LAST_CARRY ; sl_int_chk_state.COMPUTE_CARRYS ; sl_int_chk_state.COMPUTE_ADD1 ; sl_int_chk_state.COMPUTE_ADD0 ; sl_int_chk_state.COMPUTE1 ; sl_int_chk_state.COMPUTE0 ; sl_int_chk_state.WAIT_DOUT ; sl_int_chk_state.IDLE ;
+-------------------------------------+----------------------+-------------------------------------+---------------------------------+-------------------------------+-------------------------------+---------------------------+---------------------------+----------------------------+-----------------------+
; sl_int_chk_state.IDLE               ; 0                    ; 0                                   ; 0                               ; 0                             ; 0                             ; 0                         ; 0                         ; 0                          ; 0                     ;
; sl_int_chk_state.WAIT_DOUT          ; 0                    ; 0                                   ; 0                               ; 0                             ; 0                             ; 0                         ; 0                         ; 1                          ; 1                     ;
; sl_int_chk_state.COMPUTE0           ; 0                    ; 0                                   ; 0                               ; 0                             ; 0                             ; 0                         ; 1                         ; 0                          ; 1                     ;
; sl_int_chk_state.COMPUTE1           ; 0                    ; 0                                   ; 0                               ; 0                             ; 0                             ; 1                         ; 0                         ; 0                          ; 1                     ;
; sl_int_chk_state.COMPUTE_ADD0       ; 0                    ; 0                                   ; 0                               ; 0                             ; 1                             ; 0                         ; 0                         ; 0                          ; 1                     ;
; sl_int_chk_state.COMPUTE_ADD1       ; 0                    ; 0                                   ; 0                               ; 1                             ; 0                             ; 0                         ; 0                         ; 0                          ; 1                     ;
; sl_int_chk_state.COMPUTE_CARRYS     ; 0                    ; 0                                   ; 1                               ; 0                             ; 0                             ; 0                         ; 0                         ; 0                          ; 1                     ;
; sl_int_chk_state.COMPUTE_LAST_CARRY ; 0                    ; 1                                   ; 0                               ; 0                             ; 0                             ; 0                         ; 0                         ; 0                          ; 1                     ;
; sl_int_chk_state.ACK                ; 1                    ; 0                                   ; 0                               ; 0                             ; 0                             ; 0                         ; 0                         ; 0                          ; 1                     ;
+-------------------------------------+----------------------+-------------------------------------+---------------------------------+-------------------------------+-------------------------------+---------------------------+---------------------------+----------------------------+-----------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|sl_int_state[1]                                                                                                                                                                                                                      ;
+---------------------------------------+--------------------------------+---------------------------------------+-----------------------------------+------------------------------+----------------------------+---------------------+-----------------------+-------------------------------+---------------------------+----------------------+
; Name                                  ; sl_int_state[1].WAIT_COMMON_RQ ; sl_int_state[1].WAIT_END_BUSY_FROM_HW ; sl_int_state[1].WAIT_BUSY_FROM_HW ; sl_int_state[1].WAIT_RESTART ; sl_int_state[1].HARD_RESET ; sl_int_state[1].ACK ; sl_int_state[1].ERROR ; sl_int_state[1].WAIT_END_BUSY ; sl_int_state[1].WAIT_BUSY ; sl_int_state[1].IDLE ;
+---------------------------------------+--------------------------------+---------------------------------------+-----------------------------------+------------------------------+----------------------------+---------------------+-----------------------+-------------------------------+---------------------------+----------------------+
; sl_int_state[1].IDLE                  ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 0                    ;
; sl_int_state[1].WAIT_BUSY             ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 1                         ; 1                    ;
; sl_int_state[1].WAIT_END_BUSY         ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 1                             ; 0                         ; 1                    ;
; sl_int_state[1].ERROR                 ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 1                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[1].ACK                   ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 1                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[1].HARD_RESET            ; 0                              ; 0                                     ; 0                                 ; 0                            ; 1                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[1].WAIT_RESTART          ; 0                              ; 0                                     ; 0                                 ; 1                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[1].WAIT_BUSY_FROM_HW     ; 0                              ; 0                                     ; 1                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[1].WAIT_END_BUSY_FROM_HW ; 0                              ; 1                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[1].WAIT_COMMON_RQ        ; 1                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
+---------------------------------------+--------------------------------+---------------------------------------+-----------------------------------+------------------------------+----------------------------+---------------------+-----------------------+-------------------------------+---------------------------+----------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|sl_int_state[0]                                                                                                                                                                                                                      ;
+---------------------------------------+--------------------------------+---------------------------------------+-----------------------------------+------------------------------+----------------------------+---------------------+-----------------------+-------------------------------+---------------------------+----------------------+
; Name                                  ; sl_int_state[0].WAIT_COMMON_RQ ; sl_int_state[0].WAIT_END_BUSY_FROM_HW ; sl_int_state[0].WAIT_BUSY_FROM_HW ; sl_int_state[0].WAIT_RESTART ; sl_int_state[0].HARD_RESET ; sl_int_state[0].ACK ; sl_int_state[0].ERROR ; sl_int_state[0].WAIT_END_BUSY ; sl_int_state[0].WAIT_BUSY ; sl_int_state[0].IDLE ;
+---------------------------------------+--------------------------------+---------------------------------------+-----------------------------------+------------------------------+----------------------------+---------------------+-----------------------+-------------------------------+---------------------------+----------------------+
; sl_int_state[0].IDLE                  ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 0                    ;
; sl_int_state[0].WAIT_BUSY             ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 1                         ; 1                    ;
; sl_int_state[0].WAIT_END_BUSY         ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 1                             ; 0                         ; 1                    ;
; sl_int_state[0].ERROR                 ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 1                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[0].ACK                   ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 1                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[0].HARD_RESET            ; 0                              ; 0                                     ; 0                                 ; 0                            ; 1                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[0].WAIT_RESTART          ; 0                              ; 0                                     ; 0                                 ; 1                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[0].WAIT_BUSY_FROM_HW     ; 0                              ; 0                                     ; 1                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[0].WAIT_END_BUSY_FROM_HW ; 0                              ; 1                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[0].WAIT_COMMON_RQ        ; 1                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
+---------------------------------------+--------------------------------+---------------------------------------+-----------------------------------+------------------------------+----------------------------+---------------------+-----------------------+-------------------------------+---------------------------+----------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_L1A_state                                 ;
+--------------------------------+--------------------------------+------------------------+-----------------------------+
; Name                           ; sl_int_L1A_state.WAIT_NO_PULSE ; sl_int_L1A_state.COUNT ; sl_int_L1A_state.WAIT_PULSE ;
+--------------------------------+--------------------------------+------------------------+-----------------------------+
; sl_int_L1A_state.WAIT_PULSE    ; 0                              ; 0                      ; 0                           ;
; sl_int_L1A_state.COUNT         ; 0                              ; 1                      ; 1                           ;
; sl_int_L1A_state.WAIT_NO_PULSE ; 1                              ; 0                      ; 1                           ;
+--------------------------------+--------------------------------+------------------------+-----------------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_timeout_state                             ;
+------------------------------+------------------------------+------------------------------+---------------------------+
; Name                         ; sl_int_timeout_state.STARTED ; sl_int_timeout_state.TIMEOUT ; sl_int_timeout_state.NONE ;
+------------------------------+------------------------------+------------------------------+---------------------------+
; sl_int_timeout_state.NONE    ; 0                            ; 0                            ; 0                         ;
; sl_int_timeout_state.TIMEOUT ; 0                            ; 1                            ; 1                         ;
; sl_int_timeout_state.STARTED ; 1                            ; 0                            ; 1                         ;
+------------------------------+------------------------------+------------------------------+---------------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET|sl_int_state ;
+--------------------+------------------+--------------------+-----------------------------------------+
; Name               ; sl_int_state.ACK ; sl_int_state.LATCH ; sl_int_state.IDLE                       ;
+--------------------+------------------+--------------------+-----------------------------------------+
; sl_int_state.IDLE  ; 0                ; 0                  ; 0                                       ;
; sl_int_state.LATCH ; 0                ; 1                  ; 1                                       ;
; sl_int_state.ACK   ; 1                ; 0                  ; 1                                       ;
+--------------------+------------------+--------------------+-----------------------------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET|sl_int_state ;
+--------------------+------------------+--------------------+---------------------------------------+
; Name               ; sl_int_state.ACK ; sl_int_state.LATCH ; sl_int_state.IDLE                     ;
+--------------------+------------------+--------------------+---------------------------------------+
; sl_int_state.IDLE  ; 0                ; 0                  ; 0                                     ;
; sl_int_state.LATCH ; 0                ; 1                  ; 1                                     ;
; sl_int_state.ACK   ; 1                ; 0                  ; 1                                     ;
+--------------------+------------------+--------------------+---------------------------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET|sl_int_state ;
+--------------------+------------------+--------------------+--------------------------------------+
; Name               ; sl_int_state.ACK ; sl_int_state.LATCH ; sl_int_state.IDLE                    ;
+--------------------+------------------+--------------------+--------------------------------------+
; sl_int_state.IDLE  ; 0                ; 0                  ; 0                                    ;
; sl_int_state.LATCH ; 0                ; 1                  ; 1                                    ;
; sl_int_state.ACK   ; 1                ; 0                  ; 1                                    ;
+--------------------+------------------+--------------------+--------------------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_state                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+----------------------------------------------+----------------------------------------------+-----------------------------------+-----------------------+------------------+-----------------+--------------------------------+---------------------+-----------------------------+----------------------------------------+----------------------------------+-----------------------------------+-----------------------------+---------------------------+--------------------------+-------------------------+-------------------+
; Name                                         ; sl_int_state.GET_CONFIG_ARG_CHECK_FIFO_DELAY ; sl_int_state.GET_CONFIG_CMD_DELAY ; sl_int_state.WR_DELAY ; sl_int_state.ACK ; sl_int_state.WR ; sl_int_state.GET_USER_CMD_WAIT ; sl_int_state.ANSWER ; sl_int_state.GET_CONFIG_END ; sl_int_state.GET_CONFIG_ARG_CHECK_FIFO ; sl_int_state.GET_CONFIG_WAIT_CRC ; sl_int_state.GET_CONFIG_START_CRC ; sl_int_state.GET_CONFIG_CMD ; sl_int_state.GET_BOARD_ID ; sl_int_state.READ_STATUS ; sl_int_state.FW_VERSION ; sl_int_state.IDLE ;
+----------------------------------------------+----------------------------------------------+-----------------------------------+-----------------------+------------------+-----------------+--------------------------------+---------------------+-----------------------------+----------------------------------------+----------------------------------+-----------------------------------+-----------------------------+---------------------------+--------------------------+-------------------------+-------------------+
; sl_int_state.IDLE                            ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 0                 ;
; sl_int_state.FW_VERSION                      ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 1                       ; 1                 ;
; sl_int_state.READ_STATUS                     ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 1                        ; 0                       ; 1                 ;
; sl_int_state.GET_BOARD_ID                    ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 1                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_CMD                  ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 1                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_START_CRC            ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 1                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_WAIT_CRC             ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 1                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_ARG_CHECK_FIFO       ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 1                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_END                  ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 1                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.ANSWER                          ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 1                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_USER_CMD_WAIT               ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 1                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.WR                              ; 0                                            ; 0                                 ; 0                     ; 0                ; 1               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.ACK                             ; 0                                            ; 0                                 ; 0                     ; 1                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.WR_DELAY                        ; 0                                            ; 0                                 ; 1                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_CMD_DELAY            ; 0                                            ; 1                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_ARG_CHECK_FIFO_DELAY ; 1                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
+----------------------------------------------+----------------------------------------------+-----------------------------------+-----------------------+------------------+-----------------+--------------------------------+---------------------+-----------------------------+----------------------------------------+----------------------------------+-----------------------------------+-----------------------------+---------------------------+--------------------------+-------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_timeout_state            ;
+------------------------------+------------------------------+----------------------------+----------------------------+
; Name                         ; sl_int_timeout_state.TIMEOUT ; sl_int_timeout_state.COUNT ; sl_int_timeout_state.RESET ;
+------------------------------+------------------------------+----------------------------+----------------------------+
; sl_int_timeout_state.RESET   ; 0                            ; 0                          ; 0                          ;
; sl_int_timeout_state.COUNT   ; 0                            ; 1                          ; 1                          ;
; sl_int_timeout_state.TIMEOUT ; 1                            ; 0                          ; 1                          ;
+------------------------------+------------------------------+----------------------------+----------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|sl_int_state_ack                                                                            ;
+-------------------------------+-------------------------------+------------------------------+------------------------------+-----------------------+----------------------+---------------------------+
; Name                          ; sl_int_state_ack.WAIT_RESTART ; sl_int_state_ack.WAIT_ACK1_1 ; sl_int_state_ack.WAIT_ACK0_1 ; sl_int_state_ack.ACK2 ; sl_int_state_ack.ACK ; sl_int_state_ack.WAIT_ACK ;
+-------------------------------+-------------------------------+------------------------------+------------------------------+-----------------------+----------------------+---------------------------+
; sl_int_state_ack.WAIT_ACK     ; 0                             ; 0                            ; 0                            ; 0                     ; 0                    ; 0                         ;
; sl_int_state_ack.ACK          ; 0                             ; 0                            ; 0                            ; 0                     ; 1                    ; 1                         ;
; sl_int_state_ack.ACK2         ; 0                             ; 0                            ; 0                            ; 1                     ; 0                    ; 1                         ;
; sl_int_state_ack.WAIT_ACK0_1  ; 0                             ; 0                            ; 1                            ; 0                     ; 0                    ; 1                         ;
; sl_int_state_ack.WAIT_ACK1_1  ; 0                             ; 1                            ; 0                            ; 0                     ; 0                    ; 1                         ;
; sl_int_state_ack.WAIT_RESTART ; 1                             ; 0                            ; 0                            ; 0                     ; 0                    ; 1                         ;
+-------------------------------+-------------------------------+------------------------------+------------------------------+-----------------------+----------------------+---------------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_state ;
+--------------------+------------------+------------------+--------------------+----------------------+
; Name               ; sl_int_state.ERR ; sl_int_state.ACK ; sl_int_state.STORE ; sl_int_state.IDLE    ;
+--------------------+------------------+------------------+--------------------+----------------------+
; sl_int_state.IDLE  ; 0                ; 0                ; 0                  ; 0                    ;
; sl_int_state.STORE ; 0                ; 0                ; 1                  ; 1                    ;
; sl_int_state.ACK   ; 0                ; 1                ; 0                  ; 1                    ;
; sl_int_state.ERR   ; 1                ; 0                ; 0                  ; 1                    ;
+--------------------+------------------+------------------+--------------------+----------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_state ;
+--------------------+------------------+------------------+--------------------+----------------------+
; Name               ; sl_int_state.ERR ; sl_int_state.ACK ; sl_int_state.STORE ; sl_int_state.IDLE    ;
+--------------------+------------------+------------------+--------------------+----------------------+
; sl_int_state.IDLE  ; 0                ; 0                ; 0                  ; 0                    ;
; sl_int_state.STORE ; 0                ; 0                ; 1                  ; 1                    ;
; sl_int_state.ACK   ; 0                ; 1                ; 0                  ; 1                    ;
; sl_int_state.ERR   ; 1                ; 0                ; 0                  ; 1                    ;
+--------------------+------------------+------------------+--------------------+----------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_state ;
+--------------------+------------------+------------------+--------------------+--------------------+
; Name               ; sl_int_state.ERR ; sl_int_state.ACK ; sl_int_state.STORE ; sl_int_state.IDLE  ;
+--------------------+------------------+------------------+--------------------+--------------------+
; sl_int_state.IDLE  ; 0                ; 0                ; 0                  ; 0                  ;
; sl_int_state.STORE ; 0                ; 0                ; 1                  ; 1                  ;
; sl_int_state.ACK   ; 0                ; 1                ; 0                  ; 1                  ;
; sl_int_state.ERR   ; 1                ; 0                ; 0                  ; 1                  ;
+--------------------+------------------+------------------+--------------------+--------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_state ;
+--------------------+------------------+------------------+--------------------+-------------------+
; Name               ; sl_int_state.ERR ; sl_int_state.ACK ; sl_int_state.STORE ; sl_int_state.IDLE ;
+--------------------+------------------+------------------+--------------------+-------------------+
; sl_int_state.IDLE  ; 0                ; 0                ; 0                  ; 0                 ;
; sl_int_state.STORE ; 0                ; 0                ; 1                  ; 1                 ;
; sl_int_state.ACK   ; 0                ; 1                ; 0                  ; 1                 ;
; sl_int_state.ERR   ; 1                ; 0                ; 0                  ; 1                 ;
+--------------------+------------------+------------------+--------------------+-------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_state                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-----------------------------------------------+-------------------------------------+-------------------------------+--------------------------------------+-----------------------------------------------+--------------------------+-------------------------+--------------------------------------+------------------------+--------------------------------------+---------------------------------------+-----------------------------------------+-----------------------------------------+-----------------------------------+-----------------------------------+-------------------------------------+-------------------------------+-------------------------------+-------------------------+-------------------------+--------------------------------+-----------------+-------------------+
; Name                                          ; sl_int_state.CMD_2FRM_PROCESS_DELAY ; sl_int_state.CMD_DECODE_DELAY ; sl_int_state.CMD_NOT_ADRRESSED_DELAY ; sl_int_state.CMD_SET_CONFIG_CMD_PROCESS_DELAY ; sl_int_state.CHECK_VALID ; sl_int_state.CMD_ANSWER ; sl_int_state.WAIT_FIFO_PROCESS_DELAY ; sl_int_state.WAIT_FIFO ; sl_int_state.CMD_SET_CONFIG_WAIT_CRC ; sl_int_state.CMD_SET_CONFIG_START_CRC ; sl_int_state.CMD_SET_CONFIG_ARG_PROCESS ; sl_int_state.CMD_SET_CONFIG_CMD_PROCESS ; sl_int_state.CMD_SET_CONFIG_VALID ; sl_int_state.CMD_2FRM_PROCESS_END ; sl_int_state.CMD_2FRM_PROCESS_CHECK ; sl_int_state.CMD_2FRM_PROCESS ; sl_int_state.CMD_1FRM_PROCESS ; sl_int_state.CMD_DECODE ; sl_int_state.ADD_DECODE ; sl_int_state.CMD_NOT_ADRRESSED ; sl_int_state.RD ; sl_int_state.IDLE ;
+-----------------------------------------------+-------------------------------------+-------------------------------+--------------------------------------+-----------------------------------------------+--------------------------+-------------------------+--------------------------------------+------------------------+--------------------------------------+---------------------------------------+-----------------------------------------+-----------------------------------------+-----------------------------------+-----------------------------------+-------------------------------------+-------------------------------+-------------------------------+-------------------------+-------------------------+--------------------------------+-----------------+-------------------+
; sl_int_state.IDLE                             ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 0                 ;
; sl_int_state.RD                               ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 1               ; 1                 ;
; sl_int_state.CMD_NOT_ADRRESSED                ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 1                              ; 0               ; 1                 ;
; sl_int_state.ADD_DECODE                       ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 1                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_DECODE                       ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 1                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_1FRM_PROCESS                 ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 1                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_2FRM_PROCESS                 ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 1                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_2FRM_PROCESS_CHECK           ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 1                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_2FRM_PROCESS_END             ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 1                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_VALID             ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 1                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_CMD_PROCESS       ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 1                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_ARG_PROCESS       ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 1                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_START_CRC         ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 1                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_WAIT_CRC          ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 1                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.WAIT_FIFO                        ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 1                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.WAIT_FIFO_PROCESS_DELAY          ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 1                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_ANSWER                       ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 1                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CHECK_VALID                      ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 1                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_CMD_PROCESS_DELAY ; 0                                   ; 0                             ; 0                                    ; 1                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_NOT_ADRRESSED_DELAY          ; 0                                   ; 0                             ; 1                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_DECODE_DELAY                 ; 0                                   ; 1                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_2FRM_PROCESS_DELAY           ; 1                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
+-----------------------------------------------+-------------------------------------+-------------------------------+--------------------------------------+-----------------------------------------------+--------------------------+-------------------------+--------------------------------------+------------------------+--------------------------------------+---------------------------------------+-----------------------------------------+-----------------------------------------+-----------------------------------+-----------------------------------+-------------------------------------+-------------------------------+-------------------------------+-------------------------+-------------------------+--------------------------------+-----------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_process_state                                                                                                                                                                                                                                                                             ;
+-----------------------------------------+--------------------------+---------------------------------------+-----------------------------------+---------------------------------------+-----------------------------------+-----------------------------------------+----------------------------------------+---------------------------------------+---------------------------+
; Name                                    ; sl_int_process_state.ACK ; sl_int_process_state.SET_USER_SET_CMD ; sl_int_process_state.SET_USER_SET ; sl_int_process_state.APPLY_CONFIG_END ; sl_int_process_state.APPLY_CONFIG ; sl_int_process_state.APPLY_CONFIG_START ; sl_int_process_state.SET_READOUT_PARAM ; sl_int_process_state.SET_DIRECT_PARAM ; sl_int_process_state.IDLE ;
+-----------------------------------------+--------------------------+---------------------------------------+-----------------------------------+---------------------------------------+-----------------------------------+-----------------------------------------+----------------------------------------+---------------------------------------+---------------------------+
; sl_int_process_state.IDLE               ; 0                        ; 0                                     ; 0                                 ; 0                                     ; 0                                 ; 0                                       ; 0                                      ; 0                                     ; 0                         ;
; sl_int_process_state.SET_DIRECT_PARAM   ; 0                        ; 0                                     ; 0                                 ; 0                                     ; 0                                 ; 0                                       ; 0                                      ; 1                                     ; 1                         ;
; sl_int_process_state.SET_READOUT_PARAM  ; 0                        ; 0                                     ; 0                                 ; 0                                     ; 0                                 ; 0                                       ; 1                                      ; 0                                     ; 1                         ;
; sl_int_process_state.APPLY_CONFIG_START ; 0                        ; 0                                     ; 0                                 ; 0                                     ; 0                                 ; 1                                       ; 0                                      ; 0                                     ; 1                         ;
; sl_int_process_state.APPLY_CONFIG       ; 0                        ; 0                                     ; 0                                 ; 0                                     ; 1                                 ; 0                                       ; 0                                      ; 0                                     ; 1                         ;
; sl_int_process_state.APPLY_CONFIG_END   ; 0                        ; 0                                     ; 0                                 ; 1                                     ; 0                                 ; 0                                       ; 0                                      ; 0                                     ; 1                         ;
; sl_int_process_state.SET_USER_SET       ; 0                        ; 0                                     ; 1                                 ; 0                                     ; 0                                 ; 0                                       ; 0                                      ; 0                                     ; 1                         ;
; sl_int_process_state.SET_USER_SET_CMD   ; 0                        ; 1                                     ; 0                                 ; 0                                     ; 0                                 ; 0                                       ; 0                                      ; 0                                     ; 1                         ;
; sl_int_process_state.ACK                ; 1                        ; 0                                     ; 0                                 ; 0                                     ; 0                                 ; 0                                       ; 0                                      ; 0                                     ; 1                         ;
+-----------------------------------------+--------------------------+---------------------------------------+-----------------------------------+---------------------------------------+-----------------------------------+-----------------------------------------+----------------------------------------+---------------------------------------+---------------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_timeout_state                 ;
+------------------------------+------------------------------+----------------------------+----------------------------+
; Name                         ; sl_int_timeout_state.TIMEOUT ; sl_int_timeout_state.COUNT ; sl_int_timeout_state.RESET ;
+------------------------------+------------------------------+----------------------------+----------------------------+
; sl_int_timeout_state.RESET   ; 0                            ; 0                          ; 0                          ;
; sl_int_timeout_state.COUNT   ; 0                            ; 1                          ; 1                          ;
; sl_int_timeout_state.TIMEOUT ; 1                            ; 0                          ; 1                          ;
+------------------------------+------------------------------+----------------------------+----------------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|state ;
+-----------------------+-----------------------+-------------------+-------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name                  ; state.stm_typ_end_frm ; state.stm_typ_frm ; state.stm_typ_sfd ; state.stm_typ_idle                                                                                                                                                                                                     ;
+-----------------------+-----------------------+-------------------+-------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; state.stm_typ_idle    ; 0                     ; 0                 ; 0                 ; 0                                                                                                                                                                                                                      ;
; state.stm_typ_sfd     ; 0                     ; 0                 ; 1                 ; 1                                                                                                                                                                                                                      ;
; state.stm_typ_frm     ; 0                     ; 1                 ; 0                 ; 1                                                                                                                                                                                                                      ;
; state.stm_typ_end_frm ; 1                     ; 0                 ; 0                 ; 1                                                                                                                                                                                                                      ;
+-----------------------+-----------------------+-------------------+-------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_read_cntl:U_LBR|state ;
+-------------------------+---------------------+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name                    ; state.STM_TYPE_IDLE ; state.STM_TYPE_NEXT_FRM ; state.STM_TYPE_FRM_READ                                                                                                                                                                              ;
+-------------------------+---------------------+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; state.STM_TYPE_IDLE     ; 0                   ; 0                       ; 0                                                                                                                                                                                                    ;
; state.STM_TYPE_FRM_READ ; 1                   ; 0                       ; 1                                                                                                                                                                                                    ;
; state.STM_TYPE_NEXT_FRM ; 1                   ; 1                       ; 0                                                                                                                                                                                                    ;
+-------------------------+---------------------+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_wrt_cntl:U_LBW|state ;
+-------------------------+-------------------------+------------------------+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name                    ; state.STM_TYPE_NEXT_FRM ; state.STM_TYPE_FRM_WRT ; state.STM_TYPE_LOOP_ENA ; state.STM_TYPE_IDLE                                                                                                                                                    ;
+-------------------------+-------------------------+------------------------+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; state.STM_TYPE_IDLE     ; 0                       ; 0                      ; 0                       ; 0                                                                                                                                                                      ;
; state.STM_TYPE_LOOP_ENA ; 0                       ; 0                      ; 1                       ; 1                                                                                                                                                                      ;
; state.STM_TYPE_FRM_WRT  ; 0                       ; 1                      ; 0                       ; 1                                                                                                                                                                      ;
; state.STM_TYPE_NEXT_FRM ; 1                       ; 0                      ; 0                       ; 1                                                                                                                                                                      ;
+-------------------------+-------------------------+------------------------+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_state                                                                                                                                                                                                                                                                                                                                                                         ;
+----------------------------------+------------------+----------------------------+------------------------+-------------------------+-------------------------+----------------------------------+---------------------------------+-------------------------+--------------------------+--------------------------+---------------------------+------------------------------+-----------------------+---------------------------------+-------------------------+-----------------------+-------------------+
; Name                             ; sl_int_state.ACK ; sl_int_state.SERIALIZE_CAL ; sl_int_state.SERIALIZE ; sl_int_state.SLOW_CMD_2 ; sl_int_state.SLOW_CMD_1 ; sl_int_state.SLOW_CMD_WRITE_MASK ; sl_int_state.SLOW_CMD_CAL_PULSE ; sl_int_state.LOOP_READY ; sl_int_state.RESET_READY ; sl_int_state.CHECK_READY ; sl_int_state.LOOP_RESTART ; sl_int_state.RESET_CAL_PULSE ; sl_int_state.SLOW_CMD ; sl_int_state.SOFT_RESET_DELAYED ; sl_int_state.SOFT_RESET ; sl_int_state.SOFT_L1A ; sl_int_state.IDLE ;
+----------------------------------+------------------+----------------------------+------------------------+-------------------------+-------------------------+----------------------------------+---------------------------------+-------------------------+--------------------------+--------------------------+---------------------------+------------------------------+-----------------------+---------------------------------+-------------------------+-----------------------+-------------------+
; sl_int_state.IDLE                ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 0                 ;
; sl_int_state.SOFT_L1A            ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 1                     ; 1                 ;
; sl_int_state.SOFT_RESET          ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 1                       ; 0                     ; 1                 ;
; sl_int_state.SOFT_RESET_DELAYED  ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 1                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD            ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 1                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.RESET_CAL_PULSE     ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 1                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.LOOP_RESTART        ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 1                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.CHECK_READY         ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 1                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.RESET_READY         ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 1                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.LOOP_READY          ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 1                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD_CAL_PULSE  ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 1                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD_WRITE_MASK ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 1                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD_1          ; 0                ; 0                          ; 0                      ; 0                       ; 1                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD_2          ; 0                ; 0                          ; 0                      ; 1                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SERIALIZE           ; 0                ; 0                          ; 1                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SERIALIZE_CAL       ; 0                ; 1                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.ACK                 ; 1                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
+----------------------------------+------------------+----------------------------+------------------------+-------------------------+-------------------------+----------------------------------+---------------------------------+-------------------------+--------------------------+--------------------------+---------------------------+------------------------------+-----------------------+---------------------------------+-------------------------+-----------------------+-------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_state                                                                                                                                                                                                                                                                                                                                                                         ;
+----------------------------------+------------------+----------------------------+------------------------+-------------------------+-------------------------+----------------------------------+---------------------------------+-------------------------+--------------------------+--------------------------+---------------------------+------------------------------+-----------------------+---------------------------------+-------------------------+-----------------------+-------------------+
; Name                             ; sl_int_state.ACK ; sl_int_state.SERIALIZE_CAL ; sl_int_state.SERIALIZE ; sl_int_state.SLOW_CMD_2 ; sl_int_state.SLOW_CMD_1 ; sl_int_state.SLOW_CMD_WRITE_MASK ; sl_int_state.SLOW_CMD_CAL_PULSE ; sl_int_state.LOOP_READY ; sl_int_state.RESET_READY ; sl_int_state.CHECK_READY ; sl_int_state.LOOP_RESTART ; sl_int_state.RESET_CAL_PULSE ; sl_int_state.SLOW_CMD ; sl_int_state.SOFT_RESET_DELAYED ; sl_int_state.SOFT_RESET ; sl_int_state.SOFT_L1A ; sl_int_state.IDLE ;
+----------------------------------+------------------+----------------------------+------------------------+-------------------------+-------------------------+----------------------------------+---------------------------------+-------------------------+--------------------------+--------------------------+---------------------------+------------------------------+-----------------------+---------------------------------+-------------------------+-----------------------+-------------------+
; sl_int_state.IDLE                ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 0                 ;
; sl_int_state.SOFT_L1A            ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 1                     ; 1                 ;
; sl_int_state.SOFT_RESET          ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 1                       ; 0                     ; 1                 ;
; sl_int_state.SOFT_RESET_DELAYED  ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 1                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD            ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 1                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.RESET_CAL_PULSE     ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 1                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.LOOP_RESTART        ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 1                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.CHECK_READY         ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 1                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.RESET_READY         ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 1                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.LOOP_READY          ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 1                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD_CAL_PULSE  ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 1                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD_WRITE_MASK ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 1                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD_1          ; 0                ; 0                          ; 0                      ; 0                       ; 1                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD_2          ; 0                ; 0                          ; 0                      ; 1                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SERIALIZE           ; 0                ; 0                          ; 1                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SERIALIZE_CAL       ; 0                ; 1                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.ACK                 ; 1                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
+----------------------------------+------------------+----------------------------+------------------------+-------------------------+-------------------------+----------------------------------+---------------------------------+-------------------------+--------------------------+--------------------------+---------------------------+------------------------------+-----------------------+---------------------------------+-------------------------+-----------------------+-------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|state                                             ;
+------------------------------------+------------------------------------+--------------------------+----------------------------+-------------------------------+-------------------------------+-------------------------+-----------------------+----------------------+----------------------+----------------------+
; Name                               ; state.LOC_STATE_FF_DATA_FLUSH_WAIT ; state.LOC_STATE_RST_DONE ; state.LOC_STATE_SHIFT_WAIT ; state.LOC_STATE_FF_FLUSH_WAIT ; state.LOC_STATE_FF_DATA_FLUSH ; state.LOC_STATE_END_FRM ; state.LOC_STATE_SHIFT ; state.LOC_STATE_WAIT ; state.LOC_STATE_DATA ; state.LOC_STATE_IDLE ;
+------------------------------------+------------------------------------+--------------------------+----------------------------+-------------------------------+-------------------------------+-------------------------+-----------------------+----------------------+----------------------+----------------------+
; state.LOC_STATE_IDLE               ; 0                                  ; 0                        ; 0                          ; 0                             ; 0                             ; 0                       ; 0                     ; 0                    ; 0                    ; 0                    ;
; state.LOC_STATE_DATA               ; 0                                  ; 0                        ; 0                          ; 0                             ; 0                             ; 0                       ; 0                     ; 0                    ; 1                    ; 1                    ;
; state.LOC_STATE_WAIT               ; 0                                  ; 0                        ; 0                          ; 0                             ; 0                             ; 0                       ; 0                     ; 1                    ; 0                    ; 1                    ;
; state.LOC_STATE_SHIFT              ; 0                                  ; 0                        ; 0                          ; 0                             ; 0                             ; 0                       ; 1                     ; 0                    ; 0                    ; 1                    ;
; state.LOC_STATE_END_FRM            ; 0                                  ; 0                        ; 0                          ; 0                             ; 0                             ; 1                       ; 0                     ; 0                    ; 0                    ; 1                    ;
; state.LOC_STATE_FF_DATA_FLUSH      ; 0                                  ; 0                        ; 0                          ; 0                             ; 1                             ; 0                       ; 0                     ; 0                    ; 0                    ; 1                    ;
; state.LOC_STATE_FF_FLUSH_WAIT      ; 0                                  ; 0                        ; 0                          ; 1                             ; 0                             ; 0                       ; 0                     ; 0                    ; 0                    ; 1                    ;
; state.LOC_STATE_SHIFT_WAIT         ; 0                                  ; 0                        ; 1                          ; 0                             ; 0                             ; 0                       ; 0                     ; 0                    ; 0                    ; 1                    ;
; state.LOC_STATE_RST_DONE           ; 0                                  ; 1                        ; 0                          ; 0                             ; 0                             ; 0                       ; 0                     ; 0                    ; 0                    ; 1                    ;
; state.LOC_STATE_FF_DATA_FLUSH_WAIT ; 1                                  ; 0                        ; 0                          ; 0                             ; 0                             ; 0                       ; 0                     ; 0                    ; 0                    ; 1                    ;
+------------------------------------+------------------------------------+--------------------------+----------------------------+-------------------------------+-------------------------------+-------------------------+-----------------------+----------------------+----------------------+----------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFO_CHECK:C_DAQ_FIFO_CHECK|sl_int_state ;
+--------------------------+----------------------+--------------------+----------------------------------------------------------------------------------------------------+
; Name                     ; sl_int_state.XFER_RQ ; sl_int_state.COUNT ; sl_int_state.CHECK_EMPTY                                                                           ;
+--------------------------+----------------------+--------------------+----------------------------------------------------------------------------------------------------+
; sl_int_state.CHECK_EMPTY ; 0                    ; 0                  ; 0                                                                                                  ;
; sl_int_state.COUNT       ; 0                    ; 1                  ; 1                                                                                                  ;
; sl_int_state.XFER_RQ     ; 1                    ; 0                  ; 1                                                                                                  ;
+--------------------------+----------------------+--------------------+----------------------------------------------------------------------------------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFO_CHECK:C_SC_FIFO_CHECK|sl_int_state ;
+--------------------------+----------------------+--------------------+---------------------------------------------------------------------------------------------------+
; Name                     ; sl_int_state.XFER_RQ ; sl_int_state.COUNT ; sl_int_state.CHECK_EMPTY                                                                          ;
+--------------------------+----------------------+--------------------+---------------------------------------------------------------------------------------------------+
; sl_int_state.CHECK_EMPTY ; 0                    ; 0                  ; 0                                                                                                 ;
; sl_int_state.COUNT       ; 0                    ; 1                  ; 1                                                                                                 ;
; sl_int_state.XFER_RQ     ; 1                    ; 0                  ; 1                                                                                                 ;
+--------------------------+----------------------+--------------------+---------------------------------------------------------------------------------------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|a_fefifo:fifo_state|sm_emptyfull ;
+--------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name         ; state_middle ; state_full ; state_empty                                                                                                                                                                                ;
+--------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; state_empty  ; 0            ; 0          ; 0                                                                                                                                                                                          ;
; state_middle ; 1            ; 0          ; 1                                                                                                                                                                                          ;
; state_full   ; 0            ; 1          ; 1                                                                                                                                                                                          ;
+--------------+--------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DISPATCHER:C_MSGDMA_DISPATCHER|sl_int_state_rq             ;
+------------------------------+-------------------------+--------------------------+-----------------------------+----------------------------+------------------------------+----------------------+
; Name                         ; sl_int_state_rq.ACK_UDP ; sl_int_state_rq.ACK_NIOS ; sl_int_state_rq.UDP_XFER_RQ ; sl_int_state_rq.DPRAM_FILL ; sl_int_state_rq.NIOS_XFER_RQ ; sl_int_state_rq.IDLE ;
+------------------------------+-------------------------+--------------------------+-----------------------------+----------------------------+------------------------------+----------------------+
; sl_int_state_rq.IDLE         ; 0                       ; 0                        ; 0                           ; 0                          ; 0                            ; 0                    ;
; sl_int_state_rq.NIOS_XFER_RQ ; 0                       ; 0                        ; 0                           ; 0                          ; 1                            ; 1                    ;
; sl_int_state_rq.DPRAM_FILL   ; 0                       ; 0                        ; 0                           ; 1                          ; 0                            ; 1                    ;
; sl_int_state_rq.UDP_XFER_RQ  ; 0                       ; 0                        ; 1                           ; 0                          ; 0                            ; 1                    ;
; sl_int_state_rq.ACK_NIOS     ; 0                       ; 1                        ; 0                           ; 0                          ; 0                            ; 1                    ;
; sl_int_state_rq.ACK_UDP      ; 1                       ; 0                        ; 0                           ; 0                          ; 0                            ; 1                    ;
+------------------------------+-------------------------+--------------------------+-----------------------------+----------------------------+------------------------------+----------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DISPATCHER:C_MSGDMA_DISPATCHER|sl_int_state_irq ;
+--------------------------------+--------------------------+----------------------------+--------------------------------+---------------------------------------------------------------+
; Name                           ; sl_int_state_irq.ACK_IRQ ; sl_int_state_irq.CLEAR_IRQ ; sl_int_state_irq.READ_FIFO_IRQ ; sl_int_state_irq.IDLE                                         ;
+--------------------------------+--------------------------+----------------------------+--------------------------------+---------------------------------------------------------------+
; sl_int_state_irq.IDLE          ; 0                        ; 0                          ; 0                              ; 0                                                             ;
; sl_int_state_irq.READ_FIFO_IRQ ; 0                        ; 0                          ; 1                              ; 1                                                             ;
; sl_int_state_irq.CLEAR_IRQ     ; 0                        ; 1                          ; 0                              ; 1                                                             ;
; sl_int_state_irq.ACK_IRQ       ; 1                        ; 0                          ; 0                              ; 1                                                             ;
+--------------------------------+--------------------------+----------------------------+--------------------------------+---------------------------------------------------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_state                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------------------------------------+-------------------------+-----------------------------+------------------------------+---------------------------------+-----------------------+------------------------+----------------------------------+-------------------------------+-------------------------+---------------------------+-------------------------+---------------------------+---------------------------+-------------------------------------+--------------------------------------+------------------------------------+-------------------------------------+----------------------------+----------------------------+--------------------------+----------------------------+-------------------+
; Name                                 ; sl_int_state.XFER_READY ; sl_int_state.WR_IP_CHECKSUM ; sl_int_state.START_IP_CHKSUM ; sl_int_state.WR_IP_TTL_PROTOCOL ; sl_int_state.WR_IP_ID ; sl_int_state.WR_IP_LEN ; sl_int_state.WR_UDP_LEN_CHECKSUM ; sl_int_state.START_UDP_CHKSUM ; sl_int_state.WR_UDP_LEN ; sl_int_state.WR_UDP_PORTS ; sl_int_state.WR_DEST_IP ; sl_int_state.WR_DEST_MAC1 ; sl_int_state.WR_DEST_MAC0 ; sl_int_state.COPY_DAQ_FIFO_TO_DPRAM ; sl_int_state.COPY_DAQ_FIFO_TO_DPRAM0 ; sl_int_state.COPY_SC_FIFO_TO_DPRAM ; sl_int_state.COPY_SC_FIFO_TO_DPRAM0 ; sl_int_state.INIT_SRC_MAC0 ; sl_int_state.WAIT_INIT_RQ0 ; sl_int_state.INIT_SRC_IP ; sl_int_state.INIT_SRC_MAC1 ; sl_int_state.IDLE ;
+--------------------------------------+-------------------------+-----------------------------+------------------------------+---------------------------------+-----------------------+------------------------+----------------------------------+-------------------------------+-------------------------+---------------------------+-------------------------+---------------------------+---------------------------+-------------------------------------+--------------------------------------+------------------------------------+-------------------------------------+----------------------------+----------------------------+--------------------------+----------------------------+-------------------+
; sl_int_state.IDLE                    ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 0                 ;
; sl_int_state.INIT_SRC_MAC1           ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 1                          ; 1                 ;
; sl_int_state.INIT_SRC_IP             ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 1                        ; 0                          ; 1                 ;
; sl_int_state.WAIT_INIT_RQ0           ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 1                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.INIT_SRC_MAC0           ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 1                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.COPY_SC_FIFO_TO_DPRAM0  ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 1                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.COPY_SC_FIFO_TO_DPRAM   ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 1                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.COPY_DAQ_FIFO_TO_DPRAM0 ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 1                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.COPY_DAQ_FIFO_TO_DPRAM  ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 1                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.WR_DEST_MAC0            ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 1                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.WR_DEST_MAC1            ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 1                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.WR_DEST_IP              ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 1                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.WR_UDP_PORTS            ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 1                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.WR_UDP_LEN              ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 1                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.START_UDP_CHKSUM        ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 1                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.WR_UDP_LEN_CHECKSUM     ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 1                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.WR_IP_LEN               ; 0                       ; 0                           ; 0                            ; 0                               ; 0                     ; 1                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.WR_IP_ID                ; 0                       ; 0                           ; 0                            ; 0                               ; 1                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.WR_IP_TTL_PROTOCOL      ; 0                       ; 0                           ; 0                            ; 1                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.START_IP_CHKSUM         ; 0                       ; 0                           ; 1                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.WR_IP_CHECKSUM          ; 0                       ; 1                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
; sl_int_state.XFER_READY              ; 1                       ; 0                           ; 0                            ; 0                               ; 0                     ; 0                      ; 0                                ; 0                             ; 0                       ; 0                         ; 0                       ; 0                         ; 0                         ; 0                                   ; 0                                    ; 0                                  ; 0                                   ; 0                          ; 0                          ; 0                        ; 0                          ; 1                 ;
+--------------------------------------+-------------------------+-----------------------------+------------------------------+---------------------------------+-----------------------+------------------------+----------------------------------+-------------------------------+-------------------------+---------------------------+-------------------------+---------------------------+---------------------------+-------------------------------------+--------------------------------------+------------------------------------+-------------------------------------+----------------------------+----------------------------+--------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_state                                                        ;
+----------------------------------+------------------+------------------------+------------------------------+---------------------------------+-------------------------------+----------------------------------+-------------------+
; Name                             ; sl_int_state.ACK ; sl_int_state.DESC_CTRL ; sl_int_state.UDP_DESC_LENGTH ; sl_int_state.UDP_DESC_READ_ADDR ; sl_int_state.NIOS_DESC_LENGTH ; sl_int_state.NIOS_DESC_READ_ADDR ; sl_int_state.IDLE ;
+----------------------------------+------------------+------------------------+------------------------------+---------------------------------+-------------------------------+----------------------------------+-------------------+
; sl_int_state.IDLE                ; 0                ; 0                      ; 0                            ; 0                               ; 0                             ; 0                                ; 0                 ;
; sl_int_state.NIOS_DESC_READ_ADDR ; 0                ; 0                      ; 0                            ; 0                               ; 0                             ; 1                                ; 1                 ;
; sl_int_state.NIOS_DESC_LENGTH    ; 0                ; 0                      ; 0                            ; 0                               ; 1                             ; 0                                ; 1                 ;
; sl_int_state.UDP_DESC_READ_ADDR  ; 0                ; 0                      ; 0                            ; 1                               ; 0                             ; 0                                ; 1                 ;
; sl_int_state.UDP_DESC_LENGTH     ; 0                ; 0                      ; 1                            ; 0                               ; 0                             ; 0                                ; 1                 ;
; sl_int_state.DESC_CTRL           ; 0                ; 1                      ; 0                            ; 0                               ; 0                             ; 0                                ; 1                 ;
; sl_int_state.ACK                 ; 1                ; 0                      ; 0                            ; 0                               ; 0                             ; 0                                ; 1                 ;
+----------------------------------+------------------+------------------------+------------------------------+---------------------------------+-------------------------------+----------------------------------+-------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_CSR_SM:C_MSGDMA_CSR_SM|sl_int_state                                                                                      ;
+-----------------------------+----------------------------+------------------+---------------------+------------------------+-----------------------------+----------------------------+-----------------------------+------------------------+-------------------+
; Name                        ; sl_int_state.WAIT_INIT_RQ0 ; sl_int_state.ACK ; sl_int_state.EN_IRQ ; sl_int_state.CLEAR_IRQ ; sl_int_state.CLEAR_IRQ_INIT ; sl_int_state.WAIT_RESETTED ; sl_int_state.WAIT_RESETTING ; sl_int_state.RESET_DMA ; sl_int_state.IDLE ;
+-----------------------------+----------------------------+------------------+---------------------+------------------------+-----------------------------+----------------------------+-----------------------------+------------------------+-------------------+
; sl_int_state.IDLE           ; 0                          ; 0                ; 0                   ; 0                      ; 0                           ; 0                          ; 0                           ; 0                      ; 0                 ;
; sl_int_state.RESET_DMA      ; 0                          ; 0                ; 0                   ; 0                      ; 0                           ; 0                          ; 0                           ; 1                      ; 1                 ;
; sl_int_state.WAIT_RESETTING ; 0                          ; 0                ; 0                   ; 0                      ; 0                           ; 0                          ; 1                           ; 0                      ; 1                 ;
; sl_int_state.WAIT_RESETTED  ; 0                          ; 0                ; 0                   ; 0                      ; 0                           ; 1                          ; 0                           ; 0                      ; 1                 ;
; sl_int_state.CLEAR_IRQ_INIT ; 0                          ; 0                ; 0                   ; 0                      ; 1                           ; 0                          ; 0                           ; 0                      ; 1                 ;
; sl_int_state.CLEAR_IRQ      ; 0                          ; 0                ; 0                   ; 1                      ; 0                           ; 0                          ; 0                           ; 0                      ; 1                 ;
; sl_int_state.EN_IRQ         ; 0                          ; 0                ; 1                   ; 0                      ; 0                           ; 0                          ; 0                           ; 0                      ; 1                 ;
; sl_int_state.ACK            ; 0                          ; 1                ; 0                   ; 0                      ; 0                           ; 0                          ; 0                           ; 0                      ; 1                 ;
; sl_int_state.WAIT_INIT_RQ0  ; 1                          ; 0                ; 0                   ; 0                      ; 0                           ; 0                          ; 0                           ; 0                      ; 1                 ;
+-----------------------------+----------------------------+------------------+---------------------+------------------------+-----------------------------+----------------------------+-----------------------------+------------------------+-------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_cntl:U_CNTL|state                                                                                                                                                                                                                              ;
+--------------------------------+---------------------------+--------------------------------+---------------------------+-----------------------------+-----------------------------+----------------------------+-------------------------------+---------------------------+----------------------------+-----------------------------+-----------------------------+-------------------------------+-------------------------------+--------------------+
; Name                           ; state.STM_TYP_HOST_RD_END ; state.STM_TYP_HOST_RD_REG_WAIT ; state.STM_TYP_HOST_RD_REG ; state.STM_TYP_HOST_RD_WAIT2 ; state.STM_TYP_HOST_RD_WAIT1 ; state.STM_TYP_HOST_RD_WAIT ; state.STM_TYP_HOST_RD_WR_ADDR ; state.STM_TYP_HOST_WR_END ; state.STM_TYP_HOST_WR_WAIT ; state.STM_TYP_HOST_WR_WAIT2 ; state.STM_TYP_HOST_WR_WAIT1 ; state.STM_TYP_HOST_WR_WR_DATA ; state.STM_TYP_HOST_WR_WR_ADDR ; state.STM_TYP_IDLE ;
+--------------------------------+---------------------------+--------------------------------+---------------------------+-----------------------------+-----------------------------+----------------------------+-------------------------------+---------------------------+----------------------------+-----------------------------+-----------------------------+-------------------------------+-------------------------------+--------------------+
; state.STM_TYP_IDLE             ; 0                         ; 0                              ; 0                         ; 0                           ; 0                           ; 0                          ; 0                             ; 0                         ; 0                          ; 0                           ; 0                           ; 0                             ; 0                             ; 0                  ;
; state.STM_TYP_HOST_WR_WR_ADDR  ; 0                         ; 0                              ; 0                         ; 0                           ; 0                           ; 0                          ; 0                             ; 0                         ; 0                          ; 0                           ; 0                           ; 0                             ; 1                             ; 1                  ;
; state.STM_TYP_HOST_WR_WR_DATA  ; 0                         ; 0                              ; 0                         ; 0                           ; 0                           ; 0                          ; 0                             ; 0                         ; 0                          ; 0                           ; 0                           ; 1                             ; 0                             ; 1                  ;
; state.STM_TYP_HOST_WR_WAIT1    ; 0                         ; 0                              ; 0                         ; 0                           ; 0                           ; 0                          ; 0                             ; 0                         ; 0                          ; 0                           ; 1                           ; 0                             ; 0                             ; 1                  ;
; state.STM_TYP_HOST_WR_WAIT2    ; 0                         ; 0                              ; 0                         ; 0                           ; 0                           ; 0                          ; 0                             ; 0                         ; 0                          ; 1                           ; 0                           ; 0                             ; 0                             ; 1                  ;
; state.STM_TYP_HOST_WR_WAIT     ; 0                         ; 0                              ; 0                         ; 0                           ; 0                           ; 0                          ; 0                             ; 0                         ; 1                          ; 0                           ; 0                           ; 0                             ; 0                             ; 1                  ;
; state.STM_TYP_HOST_WR_END      ; 0                         ; 0                              ; 0                         ; 0                           ; 0                           ; 0                          ; 0                             ; 1                         ; 0                          ; 0                           ; 0                           ; 0                             ; 0                             ; 1                  ;
; state.STM_TYP_HOST_RD_WR_ADDR  ; 0                         ; 0                              ; 0                         ; 0                           ; 0                           ; 0                          ; 1                             ; 0                         ; 0                          ; 0                           ; 0                           ; 0                             ; 0                             ; 1                  ;
; state.STM_TYP_HOST_RD_WAIT     ; 0                         ; 0                              ; 0                         ; 0                           ; 0                           ; 1                          ; 0                             ; 0                         ; 0                          ; 0                           ; 0                           ; 0                             ; 0                             ; 1                  ;
; state.STM_TYP_HOST_RD_WAIT1    ; 0                         ; 0                              ; 0                         ; 0                           ; 1                           ; 0                          ; 0                             ; 0                         ; 0                          ; 0                           ; 0                           ; 0                             ; 0                             ; 1                  ;
; state.STM_TYP_HOST_RD_WAIT2    ; 0                         ; 0                              ; 0                         ; 1                           ; 0                           ; 0                          ; 0                             ; 0                         ; 0                          ; 0                           ; 0                           ; 0                             ; 0                             ; 1                  ;
; state.STM_TYP_HOST_RD_REG      ; 0                         ; 0                              ; 1                         ; 0                           ; 0                           ; 0                          ; 0                             ; 0                         ; 0                          ; 0                           ; 0                           ; 0                             ; 0                             ; 1                  ;
; state.STM_TYP_HOST_RD_REG_WAIT ; 0                         ; 1                              ; 0                         ; 0                           ; 0                           ; 0                          ; 0                             ; 0                         ; 0                          ; 0                           ; 0                           ; 0                             ; 0                             ; 1                  ;
; state.STM_TYP_HOST_RD_END      ; 1                         ; 0                              ; 0                         ; 0                           ; 0                           ; 0                          ; 0                             ; 0                         ; 0                          ; 0                           ; 0                           ; 0                             ; 0                             ; 1                  ;
+--------------------------------+---------------------------+--------------------------------+---------------------------+-----------------------------+-----------------------------+----------------------------+-------------------------------+---------------------------+----------------------------+-----------------------------+-----------------------------+-------------------------------+-------------------------------+--------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|DRsize ;
+------------+------------+------------+------------+------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name       ; DRsize.101 ; DRsize.100 ; DRsize.011 ; DRsize.010 ; DRsize.001 ; DRsize.000                                                                                                                                                                                                                                                                   ;
+------------+------------+------------+------------+------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DRsize.000 ; 0          ; 0          ; 0          ; 0          ; 0          ; 0                                                                                                                                                                                                                                                                            ;
; DRsize.001 ; 0          ; 0          ; 0          ; 0          ; 1          ; 1                                                                                                                                                                                                                                                                            ;
; DRsize.010 ; 0          ; 0          ; 0          ; 1          ; 0          ; 1                                                                                                                                                                                                                                                                            ;
; DRsize.011 ; 0          ; 0          ; 1          ; 0          ; 0          ; 1                                                                                                                                                                                                                                                                            ;
; DRsize.100 ; 0          ; 1          ; 0          ; 0          ; 0          ; 1                                                                                                                                                                                                                                                                            ;
; DRsize.101 ; 1          ; 0          ; 0          ; 0          ; 0          ; 1                                                                                                                                                                                                                                                                            ;
+------------+------------+------------+------------+------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by Synthesis                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; Register Name                                                                                                                                                                                                                                                                                                                                                                                                                     ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][5]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][7]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][4]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][6]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][9]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][11]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][8]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][10]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0]                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0]                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1                                            ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1                                            ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][0]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][8]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_tx_if:U_MTX|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_gmii_io:U_GMIF|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                                                                                            ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_1|altera_tse_reset_synchronizer_chain[0]                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][0]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][6]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][12]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][3]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][1]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][7]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][13]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][4]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][2]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][8]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][14]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][5]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][3]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][9]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][0]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][6]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][4]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][10]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][1]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][7]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][5]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][11]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][2]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][8]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[16]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[14]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[15]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[12]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[13]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[10]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[11]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[8]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[9]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[6]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[7]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[4]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[5]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[2]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[3]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[0]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe20a[1]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][8]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[10]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[11]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[8]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[9]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[6]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[7]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[4]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[5]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[2]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[3]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[0]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[1]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[10]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[11]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[8]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[9]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[6]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[7]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[4]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[5]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[2]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[3]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[0]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[1]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[10]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[11]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[8]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[9]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[6]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[7]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[4]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[5]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[2]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[3]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[0]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[1]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[10]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[11]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[8]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[9]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[6]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[7]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[4]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[5]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[2]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[3]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[0]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[1]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[10]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[11]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[8]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[9]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[6]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[7]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[4]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[5]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[2]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[3]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[0]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[1]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[10]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[11]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[8]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[9]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[6]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[7]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[4]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[5]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[2]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[3]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[0]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[1]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[10]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[11]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[8]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[9]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[6]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[7]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[4]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[5]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[2]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[3]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[0]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[1]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[10]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[11]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[8]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[9]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[6]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[7]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[4]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[5]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[2]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[3]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[0]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[1]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[10]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[11]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[8]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[9]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[6]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[7]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[4]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[5]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[2]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[3]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[0]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[1]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[10]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[11]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[8]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[9]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[6]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[7]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[4]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[5]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[2]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[3]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[0]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[1]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[10]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[11]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[8]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[9]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[6]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[7]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[4]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[5]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[2]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[3]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[0]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[1]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[10]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[11]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[8]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[9]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[6]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[7]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[4]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[5]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[2]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[3]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[0]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[1]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[10]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[11]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[8]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[9]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[6]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[7]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[4]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[5]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[2]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[3]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[0]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[1]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[10]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[11]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[8]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[9]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[6]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[7]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[4]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[5]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[2]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[3]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[0]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[1]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[10]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[11]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[8]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[9]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[6]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[7]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[4]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[5]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[2]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[3]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[0]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[1]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[10]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[11]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[8]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[9]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[6]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[7]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[4]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[5]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[2]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[3]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[0]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe8a[1]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][0]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][1]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][2]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][3]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][4]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][5]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][6]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][7]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][8]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][9]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][10]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][11]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][0]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][1]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][2]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][3]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][2]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][10]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][3]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][11]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][1]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][9]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][7]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][6]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][5]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][4]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][0]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][1]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][2]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][3]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_4|altera_tse_reset_synchronizer_chain[0]                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0]                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|dreg[0]                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|rvalid                                                                                                                                                                                                                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|tck_t_dav                                                                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_tx_if:U_MTX|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_gmii_io:U_GMIF|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_1|altera_tse_reset_synchronizer_chain[1]                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[4]                                                                                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[16]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[14]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[15]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[12]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[13]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[10]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[11]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[8]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[9]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[6]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[7]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[4]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[5]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[2]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[3]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[0]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18|dffe19a[1]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[10]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[11]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[8]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[9]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[6]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[7]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[4]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[5]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[2]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[3]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[0]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[1]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[10]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[11]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[8]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[9]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[6]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[7]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[4]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[5]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[2]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[3]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[0]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[1]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[10]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[11]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[8]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[9]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[6]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[7]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[4]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[5]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[2]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[3]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[0]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[1]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[10]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[11]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[8]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[9]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[6]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[7]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[4]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[5]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[2]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[3]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[0]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[1]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[10]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[11]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[8]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[9]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[6]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[7]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[4]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[5]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[2]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[3]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[0]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[1]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[10]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[11]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[8]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[9]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[6]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[7]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[4]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[5]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[2]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[3]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[0]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[1]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[10]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[11]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[8]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[9]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[6]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[7]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[4]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[5]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[2]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[3]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[0]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[1]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[10]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[11]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[8]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[9]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[6]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[7]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[4]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[5]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[2]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[3]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[0]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[1]                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[10]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[11]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[8]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[9]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[6]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[7]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[4]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[5]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[2]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[3]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[0]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[1]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[10]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[11]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[8]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[9]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[6]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[7]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[4]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[5]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[2]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[3]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[0]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[1]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[10]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[11]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[8]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[9]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[6]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[7]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[4]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[5]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[2]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[3]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[0]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[1]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[10]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[11]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[8]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[9]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[6]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[7]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[4]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[5]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[2]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[3]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[0]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[1]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[10]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[11]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[8]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[9]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[6]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[7]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[4]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[5]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[2]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[3]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[0]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[1]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[10]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[11]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[8]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[9]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[6]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[7]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[4]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[5]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[2]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[3]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[0]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[1]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[10]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[11]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[8]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[9]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[6]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[7]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[4]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[5]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[2]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[3]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[0]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[1]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[10]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[11]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[8]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[9]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[6]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[7]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[4]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[5]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[2]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[3]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[0]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6|dffe7a[1]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][10]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][11]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][0]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][11]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][10]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][9]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][8]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][7]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][6]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][5]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][4]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][3]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][2]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][1]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][0]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][11]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][10]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][9]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][8]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][7]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][6]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][5]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][4]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][3]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][2]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][1]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][0]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][11]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][10]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][9]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][8]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][7]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][6]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][5]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][0]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][7]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][6]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][5]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][4]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][3]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][2]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][11]                                                                                                                                                                                                                                                                                                                                                 ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][9]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][7]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][6]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][5]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][4]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][3]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][2]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][1]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][0]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][11]                                                                                                                                                                                                                                                                                                                                                 ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][10]                                                                                                                                                                                                                                                                                                                                                 ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][9]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][8]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][7]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][6]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][5]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][10]                                                                                                                                                                                                                                                                                                                                                 ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][11]                                                                                                                                                                                                                                                                                                                                                 ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][10]                                                                                                                                                                                                                                                                                                                                                 ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][6]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][4]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][8]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][9]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][8]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][7]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][0]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][5]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][4]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][3]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][2]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][1]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][1]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][0]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][11]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][10]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][9]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][8]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][4]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][5]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][6]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][7]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][8]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][9]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][10]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][11]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][11]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][10]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][9]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][8]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][0]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][7]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][6]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][5]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][4]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][3]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][2]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][1]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][0]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][1]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][2]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][3]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][4]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][5]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][6]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][7]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][8]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][9]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][10]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][11]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][3]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][2]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][1]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][0]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][11]                                                                                                                                                                                                                                                                                                                                                 ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][10]                                                                                                                                                                                                                                                                                                                                                 ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][9]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][8]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][7]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][6]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][5]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][4]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][3]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][2]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][1]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][0]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][11]                                                                                                                                                                                                                                                                                                                                                 ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][10]                                                                                                                                                                                                                                                                                                                                                 ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][9]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][8]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][7]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][6]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][5]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][4]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][3]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][2]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][1]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][0]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][11]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][10]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][9]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][8]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][7]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][6]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][5]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][4]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][3]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][2]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][1]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][0]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][0]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][11]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][10]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][9]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][8]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][7]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][6]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][5]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][4]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][3]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][2]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][1]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][0]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][11]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][10]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][9]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][8]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][7]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][6]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][5]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][4]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][3]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][2]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][1]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][0]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][1]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][2]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][3]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][4]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][5]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][6]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][7]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][8]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][9]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][10]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][11]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][0]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][1]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][2]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][3]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][8]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][11]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][10]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][9]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][8]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][7]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][6]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][5]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][4]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][3]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][2]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][1]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][0]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][11]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][10]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][9]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_4|altera_tse_reset_synchronizer_chain[1]                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|din_s1                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|write_stalled                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|rdata[7]                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_tx_if:U_MTX|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_gmii_io:U_GMIF|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[3]                                                                                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[2]                                                                                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][4]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][0]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][6]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][2]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][7]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][3]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][5]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][1]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][7]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][6]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][5]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][4]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][3]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][2]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][1]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][0]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][1]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][2]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][3]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|rdata[0]                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|read_req                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[1]                                                                                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][9]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|rdata[1]                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|read                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[0]                                                                                                                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[10]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[11]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[8]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[9]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[6]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[7]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[4]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[5]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[2]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[3]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[10]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[11]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[8]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[9]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[6]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[7]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[4]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[5]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[2]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[3]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[10]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[11]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[8]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[9]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[6]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[7]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[4]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[5]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[2]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[3]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[10]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[11]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[8]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[9]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[6]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[7]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[4]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[5]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[2]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[3]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[10]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[11]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[8]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[9]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[6]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[7]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[4]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[5]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[2]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[3]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[10]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[11]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[8]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[9]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[6]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[7]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[4]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[5]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[2]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[3]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[10]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[11]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[8]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[9]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[6]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[7]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[4]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[5]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[2]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[3]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[10]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[11]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[8]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[9]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[6]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[7]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[4]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[5]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[2]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[3]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[0]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[1]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[10]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[11]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[8]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[9]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[6]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[7]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[4]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[5]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[2]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[3]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[0]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[1]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[10]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[11]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[8]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[9]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[6]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[7]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[4]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[5]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[2]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[3]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[0]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[1]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[10]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[11]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[8]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[9]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[6]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[7]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[4]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[5]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[2]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[3]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[0]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[1]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer_int_chain[2]                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_req_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|rdata[2]                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|write_valid                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe20a[10]                                                                                            ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe20a[11]                                                                                            ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe20a[8]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe20a[9]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe20a[6]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe20a[7]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe20a[4]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe20a[5]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe20a[2]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe20a[3]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe20a[0]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe20a[1]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe16a[10]                                                                                            ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe16a[11]                                                                                            ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe16a[8]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe16a[9]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe16a[6]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe16a[7]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe16a[4]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe16a[5]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe16a[2]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe16a[3]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe16a[0]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe16a[1]                                                                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[10]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[11]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[8]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[9]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[6]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[7]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[4]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[5]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[2]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[3]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[10]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[11]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[8]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[9]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[6]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[7]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[4]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[5]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[2]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[3]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[10]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[11]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[8]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[9]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[6]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[7]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[4]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[5]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[2]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[3]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[10]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[11]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[8]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[9]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[6]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[7]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[4]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[5]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[2]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[3]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[10]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[11]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[8]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[9]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[6]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[7]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[4]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[5]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[2]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[3]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[10]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[11]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[8]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[9]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[6]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[7]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[4]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[5]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[2]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[3]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[10]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[11]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[8]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[9]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[6]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[7]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[4]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[5]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[2]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[3]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[10]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[11]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[8]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[9]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[6]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[7]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[4]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[5]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[2]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[3]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[0]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[1]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[10]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[11]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[8]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[9]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[6]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[7]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[4]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[5]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[2]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[3]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[0]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[1]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[10]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[11]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[8]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[9]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[6]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[7]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[4]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[5]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[2]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[3]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[0]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[1]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][4]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][11]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][10]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][9]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][8]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][7]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][6]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][5]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][4]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][11]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][10]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][9]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][8]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][7]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][6]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][5]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][4]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][3]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][2]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][1]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][0]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[10]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[11]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[8]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[9]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[6]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[7]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[4]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[5]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[2]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[3]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[0]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[1]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer_int_chain[1]                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_req_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer_int_chain[4]                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|rdata[3]                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|write                                                                                                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT|altera_eth_tse_std_synchronizer:U_SYNC_TX_ETH_MODE|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                                          ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe19a[10]                                                                                            ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe19a[11]                                                                                            ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe19a[8]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe19a[9]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe19a[6]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe19a[7]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe19a[4]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe19a[5]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe19a[2]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe19a[3]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe19a[0]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18|dffe19a[1]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe15a[10]                                                                                            ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe15a[11]                                                                                            ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe15a[8]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe15a[9]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe15a[6]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe15a[7]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe15a[4]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe15a[5]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe15a[2]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe15a[3]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe15a[0]                                                                                             ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14|dffe15a[1]                                                                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[10]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[11]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[8]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[9]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[6]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[7]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[4]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[5]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[2]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[3]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[0]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[1]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[10]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[11]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[8]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[9]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[6]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[7]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[4]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[5]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[2]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[3]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[0]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[1]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[10]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[11]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[8]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[9]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[6]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[7]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[4]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[5]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[2]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[3]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[10]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[11]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[8]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[9]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[6]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[7]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[4]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[5]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[2]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[3]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[0]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[1]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[10]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[11]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[8]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[9]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[6]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[7]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[4]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[5]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[2]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[3]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[0]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe11a[1]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer_int_chain[0]                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_debug:the_nios2_nios2_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0]                                                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer_int_chain[3]                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16|dffe18a[6]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16|dffe18a[7]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16|dffe18a[4]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16|dffe18a[5]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16|dffe18a[2]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16|dffe18a[3]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16|dffe18a[0]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16|dffe18a[1]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|rdata[4]                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT|altera_eth_tse_std_synchronizer:U_SYNC_TX_ETH_MODE|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                                          ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[16]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[14]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[15]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[12]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[13]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[10]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[11]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[8]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[9]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[6]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[7]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[4]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[5]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[2]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[3]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[0]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe17a[1]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[10]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[11]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[8]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[9]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[6]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[7]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[4]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[5]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[2]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[3]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[0]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[1]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[10]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[11]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[8]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[9]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[6]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[7]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[4]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[5]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[2]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[3]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[0]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[1]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[10]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[11]                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[8]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[9]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[6]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[7]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[4]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[5]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[2]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[3]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[10]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[11]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[8]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[9]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[6]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[7]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[4]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[5]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[2]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[3]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[0]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[1]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[10]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[11]                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[8]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[9]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[6]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[7]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[4]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[5]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[2]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[3]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[0]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9|dffe10a[1]                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_debug:the_nios2_nios2_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16|dffe17a[6]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16|dffe17a[7]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16|dffe17a[4]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16|dffe17a[5]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16|dffe17a[2]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16|dffe17a[3]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16|dffe17a[0]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16|dffe17a[1]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|rdata[5]                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT|altera_eth_tse_std_synchronizer:U_SYNC_TX_ETH_MODE|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                                           ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[16]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[14]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[15]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[12]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[13]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[10]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[11]                                                                                                                                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[8]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[9]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[6]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[7]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[4]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[5]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[2]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[3]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[0]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15|dffe16a[1]                                                                                                                                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13|dffe15a[6]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13|dffe15a[7]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13|dffe15a[4]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13|dffe15a[5]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13|dffe15a[2]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13|dffe15a[3]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13|dffe15a[0]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13|dffe15a[1]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|rdata[6]                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_RD|b_out[0]                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_RD|b_out[1]                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_RD|b_out[2]                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_RD|b_out[3]                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_RD|b_out[4]                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_RD|b_out[5]                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_RD|b_out[6]                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_RD|b_out[7]                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_RD|b_out[8]                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13|dffe14a[6]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13|dffe14a[7]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13|dffe14a[4]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13|dffe14a[5]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13|dffe14a[2]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13|dffe14a[3]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13|dffe14a[0]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13|dffe14a[1]                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer_int_chain[4]                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer_int_chain[3]                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer_int_chain[2]                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer:U_SYNC_TX_SHIFT16|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                               ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                                                                                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[0]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[1]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[2]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[3]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[4]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[5]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[6]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[7]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[8]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer_int_chain[1]                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|b_out[0]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|b_out[1]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|b_out[2]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|b_out[3]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|b_out[4]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|b_out[5]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|b_out[6]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|b_out[7]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|b_out[8]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|b_out[9]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|b_out[10]                                                                                                                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|b_out[0]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|b_out[1]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|b_out[2]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|b_out[3]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|b_out[4]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|b_out[5]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|b_out[6]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|b_out[7]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|b_out[8]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|b_out[9]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|b_out[10]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer:U_SYNC_TX_SHIFT16|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                               ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                                                                                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer_int_chain[0]                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_3|altera_tse_reset_synchronizer_chain[0]                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer:U_SYNC_TX_SHIFT16|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[0]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[1]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[2]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[3]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[4]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[5]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[6]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[7]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[8]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|jupdate                                                                                                                                                                                                                                                          ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_3|altera_tse_reset_synchronizer_chain[1]                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|wdata[5]                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|wdata[4]                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_MAGIC_DETECT|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|wdata[6]                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|wdata[7]                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|wdata[1]                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|wdata[3]                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|wdata[0]                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|wdata[2]                                                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|altera_std_synchronizer:rdreq_sync_i|dreg[2]                                                                                                                                                                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[0]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[1]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[2]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[3]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[4]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[5]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[6]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[7]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[8]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|b_out[9]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_SYNC_5|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_MAGIC_DETECT|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|g_out[10]                                                                                                                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|g_out[9]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|g_out[8]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|g_out[7]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|g_out[6]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|g_out[5]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|g_out[4]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|g_out[3]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|g_out[2]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|g_out[1]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT|g_out[0]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|altera_std_synchronizer:rdreq_sync_i|dreg[1]                                                                                                                                                                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|wr_b_rptr[0]                                                                                                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|wr_b_rptr[1]                                                                                                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|wr_b_rptr[2]                                                                                                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|wr_b_rptr[3]                                                                                                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|wr_b_rptr[4]                                                                                                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|wr_b_rptr[5]                                                                                                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|wr_b_rptr[6]                                                                                                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|wr_b_rptr[7]                                                                                                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|wr_b_rptr[8]                                                                                                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|wr_b_rptr[9]                                                                                                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_5|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|b_out[0]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|b_out[1]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|b_out[2]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|b_out[3]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|b_out[4]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|b_out[5]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|b_out[6]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|b_out[7]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|b_out[8]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|b_out[9]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|b_out[10]                                                                                                                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|b_out[11]                                                                                                                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|b_out[0]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|b_out[1]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|b_out[2]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|b_out[3]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|b_out[4]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|b_out[5]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|b_out[6]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|b_out[7]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|b_out[8]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|b_out[9]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|b_out[10]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|b_out[11]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_SYNC_5|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_MAGIC_DETECT|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                                                    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                      ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|altera_std_synchronizer:rdreq_sync_i|dreg[0]                                                                                                                                                                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                       ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0] ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0] ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0] ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0] ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0] ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0] ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0] ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0] ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0] ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0] ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_4|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_6|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_4|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_5|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_2|altera_tse_reset_synchronizer_chain[0]                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                                                          ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_SYNC_5|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                                                          ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|g_out[10]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|g_out[9]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|g_out[8]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|g_out[7]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|g_out[6]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|g_out[5]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|g_out[4]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|g_out[3]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|g_out[2]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|altera_std_synchronizer:rdreq_sync_i|din_s1                                                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_6|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_4|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_5|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_0|altera_tse_reset_synchronizer_chain[0]                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_2|altera_tse_reset_synchronizer_chain[1]                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|g_out[1]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD|g_out[0]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_6|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer:U_SYNC_4|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_0|altera_tse_reset_synchronizer_chain[1]                                                                                                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT|altera_eth_tse_std_synchronizer:U_SYNC_RX_ETH_MODE|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                                          ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[0]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[1]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[2]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[3]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[4]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[5]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[6]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[7]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[8]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT|g_out[9]                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT|altera_eth_tse_std_synchronizer:U_SYNC_RX_ETH_MODE|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                                          ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT|altera_eth_tse_std_synchronizer:U_SYNC_RX_ETH_MODE|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|altera_eth_tse_std_synchronizer:U_SYNC_2|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                                                         ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_7|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|g_out[11]                                                                                                                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|g_out[10]                                                                                                                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|g_out[9]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|g_out[8]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|g_out[7]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|g_out[6]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|g_out[5]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|g_out[4]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|g_out[3]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|g_out[2]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|g_out[1]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT|g_out[0]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_7|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_11|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_7|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_11|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                                                                                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_11|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_PAD_ENA|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                                                                                ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_PAD_ENA|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                           ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_6|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_4|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT|b_out[0]                                                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT|b_out[1]                                                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT|b_out[2]                                                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT|b_out[3]                                                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT|b_out[4]                                                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD|b_out[0]                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD|b_out[1]                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD|b_out[2]                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD|b_out[3]                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD|b_out[4]                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|wr_b_rptr[0]                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|wr_b_rptr[1]                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|wr_b_rptr[2]                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|wr_b_rptr[3]                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|wr_b_rptr[4]                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_PAD_ENA|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                            ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_6|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[11].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[10].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[9].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[8].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[7].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[6].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[5].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_4|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                              ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                              ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                              ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                              ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                              ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_6|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|g_out[11]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|g_out[10]                                                                                                                 ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|g_out[9]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|g_out[8]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|g_out[7]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|g_out[6]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|g_out[5]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|g_out[4]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|g_out[3]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|g_out[2]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|g_out[1]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD|g_out[0]                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_4|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                               ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                               ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                               ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                               ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                               ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_wrt_cntl:U_LBW|altera_eth_tse_std_synchronizer:U_SYNC_LOOPBACK_ENA|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                          ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT|g_out[0]                                                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT|g_out[1]                                                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT|g_out[2]                                                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT|g_out[3]                                                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT|g_out[4]                                                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_wrt_cntl:U_LBW|altera_eth_tse_std_synchronizer:U_SYNC_LOOPBACK_ENA|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                          ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_wrt_cntl:U_LBW|altera_eth_tse_std_synchronizer:U_SYNC_LOOPBACK_ENA|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                           ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][0]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][0]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][0]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][4]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][4]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][4]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][1]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][1]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][1]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][5]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][5]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][5]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][2]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][2]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][2]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][6]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][6]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][6]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][3]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][3]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][3]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][7]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][7]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][7]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|rd_b_wptr[4]                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|rd_b_wptr[3]                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|rd_b_wptr[2]                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|rd_b_wptr[1]                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|rd_b_wptr[0]                                                                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][8]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][8]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][8]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][12]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][12]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][12]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][12]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][13]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][9]                                                                                                                                                                                                                                                                                                                                                      ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][9]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][9]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][9]                                                                                                                                                                                                                                                                                                                                                   ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][13]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][13]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][13]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][10]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][10]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][10]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][10]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][14]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][11]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][11]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][11]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][11]                                                                                                                                                                                                                                                                                                                                                  ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                              ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                              ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                              ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                              ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                              ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_9|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                                                                 ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][4]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][1]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][5]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][2]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][6]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][3]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][7]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[4].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                               ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[3].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                               ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[2].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                               ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[1].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                               ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                               ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_9|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0]                                                                 ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][8]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][9]                                                                                                                                                                                                                                                                                                                                                     ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][10]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][11]                                                                                                                                                                                                                                                                                                                                                    ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD|g_out[4]                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD|g_out[3]                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD|g_out[2]                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD|g_out[1]                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD|g_out[0]                                                                                                                                                   ; yes                                                              ; yes                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_9|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                                                                  ; yes                                                              ; yes                                        ;
; Total number of protected registers is 2062                                                                                                                                                                                                                                                                                                                                                                                       ;                                                                  ;                                            ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                                                                                                                                                                                                                                    ; Reason for Removal                                                                                                                                                                                                                                                                                                                                    ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; sl_int_macAddr[0]                                                                                                                                                                                                                                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; sl_int_ipAddr[0,2,4..7,10,12..15,17..21,23,29..31]                                                                                                                                                                                                                                                                                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; sl_int_macAddr[1..6,10,11,13,16,19,22..32,34,36,37,39,45..47]                                                                                                                                                                                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_fifo_pkend                                                                                                                                                                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_word_id[2]                                                                                                                                                                                                                                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[30]                                                                                                                                                                                                                                                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_counter[0,1]                                                                                                                                                                                                                                                                           ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_chksum_add0[0..7,9..11,13..15]                                                                                                                                                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_chksum_add1[3..9]                                                                                                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_data[0,1,12,15..30]                                                                                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_byteen[4..7]                                                                                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_2:mm_interconnect_2|altera_merlin_slave_translator:enet_nios_rx_dpram_s2_translator|av_chipselect_pre                                                                                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_udp_dpram_s2_translator|av_chipselect_pre                                                                                                                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_nios_tx_dpram_s2_translator|av_chipselect_pre                                                                                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_009|locked[0,1]                                                                                                                                                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003|locked[0,1]                                                                                                                                                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_rx_dpram_s1_translator|av_chipselect_pre                                                                                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_ctrl_s1_translator|av_readdata_pre[16..31]                                                                                                                                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_ctrl_s1_translator|av_chipselect_pre                                                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_tx_dpram_s1_translator|av_chipselect_pre                                                                                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:onchip_mem_s1_translator|av_chipselect_pre                                                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[1,4,6,8,13,17,20,22,24,29]                                                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[1,4,6,8,13,17,20,22,24,29,32..127]                                                                                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|av_readdata_pre[11,23..31]                                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|av_chipselect_pre                                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_rf_ecc_recoverable_valid                                                                                                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W1_rf_ecc_recoverable_valid                                                                                                                                                                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_rf_ecc_unrecoverable_valid                                                                                                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[1,3..31]                                                                                                                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ipending_reg[1,3..31]                                                                                                                                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_cdsr_reg[0..31]                                                                                                                                                                                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|R_ctrl_custom                                                                                                                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|R_ctrl_crst                                                                                                                                                                                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|R_ctrl_ld_ex                                                                                                                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|R_ctrl_st_ex                                                                                                                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_im:the_nios2_nios2_cpu_nios2_oci_im|trc_wrap                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_im:the_nios2_nios2_cpu_nios2_oci_im|trc_im_addr[0..6]                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_dbrk:the_nios2_nios2_cpu_nios2_oci_dbrk|dbrk_goto1                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_dbrk:the_nios2_nios2_cpu_nios2_oci_dbrk|dbrk_break_pulse                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_dbrk:the_nios2_nios2_cpu_nios2_oci_dbrk|dbrk_goto0                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_xbrk:the_nios2_nios2_cpu_nios2_oci_xbrk|xbrk_break                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:version_s1_translator|av_readdata_pre[16..31]                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:version_s1_translator|av_chipselect_pre                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:testing_s1_translator|av_readdata_pre[16..31]                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:testing_s1_translator|av_chipselect_pre                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_h_s1_translator|av_readdata_pre[16..31]                                                                                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_h_s1_translator|av_chipselect_pre                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_l_s1_translator|av_chipselect_pre                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_h_s1_translator|av_readdata_pre[16..31]                                                                                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_h_s1_translator|av_chipselect_pre                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_l_s1_translator|av_chipselect_pre                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_ip_addr_s1_translator|av_chipselect_pre                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_ip_addr_s1_translator|av_chipselect_pre                                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_s1_translator|av_chipselect_pre                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_s1_translator|av_readdata_pre[16..31]                                                                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_s1_translator|av_chipselect_pre                                                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_s1_translator|av_chipselect_pre                                                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[1..31]                                                                                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[1..6,10,11,13,16,19,22..31]                                                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[2,4,5,7,13..31]                                                                                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[2,4..7,10,12..15,17..21,23,29..31]                                                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|pause_wait                                                                                                    ; Stuck at VCC due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|quant_avb_reg1                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|quant_avb_reg2                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|gen_pause_wait                                                                                                ; Stuck at VCC due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|col_int                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|pause_add                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|pause_frm[0]                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_type[0]                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|stack_vlan_type[0]                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio:U_MDIO|mdio_run[19]                                                                                                                                                                           ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|pause_quant_reg[0..31]                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|holdoff_quant[0..15]                                                                                                                                                  ; Stuck at VCC due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|etherStatsFragments[0..31]                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|etherStatsJabbers[0..31]                                                                                                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|apausemacctrlframesreceived[0..31]                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|aalignmenterrors[0..31]                                                                                                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|aframechecksequenceerrors[0..31]                                                                                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|aframesreceivedok[0..31]                                                                                                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|msb_aOctetsTransmittedOK[0..31]                                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|msb_aOctetsReceivedOK[0..31]                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|msb_etherstatsoctets[0..31]                                                                                                                                           ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0,1]                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                       ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0,1]                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|early_done_enable_d1                                                                                                                                                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|done_d1                                                                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|read_sequence_number_d1[6]                                                                                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_byteen[2,3,10,11]                                                                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|write_error_IRQ_mask_d1[6,7]                                                                                                                                                           ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|write_sequence_number_d1[0..15]                                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[3..12,16..31]                                                                                                                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[12..31]                                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|init_done_forever                                                                                                                                                                                                                                         ; Stuck at VCC due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[0][53]                                                                                                                                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[0][69]                                                                                                                                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[0][53]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[0][69]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][82]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][82]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][82]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][81]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][81]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][80]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][80]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][79]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][79]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][190]                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][189]                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][188]                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][187]                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][82]                                                                                                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][81]                                                                                                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][80]                                                                                                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][79]                                                                                                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[3..12,16..31]                                                                                                                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[12..31]                                                                                                                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[1,3..31]                                                                                                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[2,4,5,7,13..31]                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[1..6,10,11,13,16,19,22..31]                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[2,4..7,10,12..15,17..21,23,29..31]                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[1..31]                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[0]                                                                                                                                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[0]                                                                                                                                                                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[0]                                                                                                                                                                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[0]                                                                                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_12|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0,1]             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_12|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|pause_frm[1]                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_type[1]                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|stack_vlan_type[1]                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|start_byte_address[0,1]                                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[0]                                                                                                                                                                                                                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|count[0..6]                                                                                                                                                                                                                                               ; Stuck at GND due to stuck port clock_enable                                                                                                                                                                                                                                                                                                           ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|rst_n[0,1]                                                                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[0]                                                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[0]                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[0]                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[0]                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[0]                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_frm                                                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_frm_s                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|ser_shift_load                                                                                                                                                                                                                                            ; Stuck at VCC due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_byteen[12]                                                                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[1][69]                                                                                                                                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[1][53]                                                                                                                                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[1][69]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[1][53]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_last_field[43..46]                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[0..31,43..63,76..95]                                                                                                                                               ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][82]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][82]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][82]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][82]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][82]                                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][82]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][82]                                                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][82]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][81]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][80]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][79]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][190]                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][189]                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][188]                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][187]                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][82]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][82]                                                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][82]                                                                                                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][81]                                                                                                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][80]                                                                                                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][79]                                                                                                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_up_ex_mon_state                                                                                                                                                                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|frm_type32[0..3]                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|broad_add_reg                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|rx_bcast                                                                                                      ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[0..16]                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|rx_ucast                                                                                                      ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|multicast_add_reg[0..14]                                                                                      ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|rx_mcast                                                                                                      ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|rx_vlan                                                                                                       ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|rx_stat_data_s[4,6]                                                                                           ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|payload_length[0..15]                                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|channel_d1[0..7]                                                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block|control[3]                                                                                                                                                                                               ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|write_address[0..3]                                                                                                                       ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|read_address[0..3]                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_frm_s2                                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[0..15]                                                                                            ; Stuck at VCC due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_status                                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|stack_vlan_status                                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_res_vlan                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|pause_frm_l                                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|rx_stat_data_s[5]                                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio:U_MDIO|read_error                                                                                                                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|write_address[0..3]                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|read_address[0..3]                                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|internal_used[0..4]                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|p_sup_64                                                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:ws_bwp|dffe14a[16]                                                                                                                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:ws_brp|dffe14a[16]                                                                                                                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:rs_bwp|dffe14a[16]                                                                                                                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:rs_brp|dffe14a[16]                                                                                                                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:ws_bwp|dffe12a[7]                                                                                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:ws_brp|dffe12a[7]                                                                                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:rs_bwp|dffe12a[7]                                                                                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:rs_brp|dffe12a[7]                                                                                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|dffpipe_qe9:ws_bwp|dffe17a[11]                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|dffpipe_qe9:ws_brp|dffe17a[11]                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|waitrequest_reset_override                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:testing_s1_translator|waitrequest_reset_override                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:testing_s1_translator|waitrequest_reset_override                                                                                                                                       ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:version_s1_translator|waitrequest_reset_override                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:version_s1_translator|waitrequest_reset_override                                                                                                                                       ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|waitrequest_reset_override                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|waitrequest_reset_override                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|waitrequest_reset_override                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|waitrequest_reset_override                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_s1_translator|waitrequest_reset_override                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_s1_translator|waitrequest_reset_override                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_s1_translator|waitrequest_reset_override                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_s1_translator|waitrequest_reset_override                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_s1_translator|waitrequest_reset_override                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_s1_translator|waitrequest_reset_override                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_ip_addr_s1_translator|waitrequest_reset_override                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_ip_addr_s1_translator|waitrequest_reset_override                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_ip_addr_s1_translator|waitrequest_reset_override                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_ip_addr_s1_translator|waitrequest_reset_override                                                                                                                               ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|waitrequest_reset_override                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|waitrequest_reset_override                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_l_s1_translator|waitrequest_reset_override                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_l_s1_translator|waitrequest_reset_override                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_h_s1_translator|waitrequest_reset_override                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_h_s1_translator|waitrequest_reset_override                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_l_s1_translator|waitrequest_reset_override                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_l_s1_translator|waitrequest_reset_override                                                                                                                           ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_h_s1_translator|waitrequest_reset_override                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_h_s1_translator|waitrequest_reset_override                                                                                                                           ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:if_bridge_m0_agent|hold_waitrequest                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_nios_tx_dpram_s2_translator|waitrequest_reset_override                                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|rst1                                                                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|rst1                                                                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_udp_dpram_s2_translator|waitrequest_reset_override                                                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_udp_dpram_s2_translator|waitrequest_reset_override                                                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|waitrequest_reset_override                                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|waitrequest_reset_override                                                                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_tx_dpram_s1_translator|waitrequest_reset_override                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_tx_dpram_s1_translator|waitrequest_reset_override                                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:onchip_mem_s1_translator|waitrequest_reset_override                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:onchip_mem_s1_translator|waitrequest_reset_override                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_response_translator|waitrequest_reset_override                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_response_translator|waitrequest_reset_override                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|waitrequest_reset_override                                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|waitrequest_reset_override                                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|waitrequest_reset_override                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|waitrequest_reset_override                                                                                                                                                                       ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|waitrequest_reset_override                                                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|waitrequest_reset_override                                                                                                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_agent:enet_tx_msgdma_mm_read_agent|hold_waitrequest                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_agent:enet_tx_msgdma_mm_read_agent|hold_waitrequest                                                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|waitrequest_reset_override                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|waitrequest_reset_override                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:eth_tse_mac_control_port_translator|waitrequest_reset_override                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:eth_tse_mac_control_port_translator|waitrequest_reset_override                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_csr_translator|waitrequest_reset_override                                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_2:mm_interconnect_2|altera_merlin_slave_translator:enet_nios_rx_dpram_s2_translator|waitrequest_reset_override                                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_ctrl_s1_translator|waitrequest_reset_override                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_ctrl_s1_translator|waitrequest_reset_override                                                                                                                                                                           ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_rx_dpram_s1_translator|waitrequest_reset_override                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_instruction_master_agent|hold_waitrequest                                                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_data_master_agent|hold_waitrequest                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_data_master_agent|hold_waitrequest                                                                                                                                                                                       ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:nios2_debug_mem_slave_translator|waitrequest_reset_override                                                                                                                         ;
; sl_int_macAddr[38]                                                                                                                                                                                                                                                                                                                                                               ; Merged with sl_int_macAddr[44]                                                                                                                                                                                                                                                                                                                        ;
; sl_int_macAddr[44]                                                                                                                                                                                                                                                                                                                                                               ; Merged with sl_int_ipAddr[1]                                                                                                                                                                                                                                                                                                                          ;
; sl_int_ipAddr[1]                                                                                                                                                                                                                                                                                                                                                                 ; Merged with sl_int_ipAddr[3]                                                                                                                                                                                                                                                                                                                          ;
; sl_int_ipAddr[3]                                                                                                                                                                                                                                                                                                                                                                 ; Merged with sl_int_ipAddr[8]                                                                                                                                                                                                                                                                                                                          ;
; sl_int_ipAddr[8]                                                                                                                                                                                                                                                                                                                                                                 ; Merged with sl_int_ipAddr[9]                                                                                                                                                                                                                                                                                                                          ;
; sl_int_ipAddr[9]                                                                                                                                                                                                                                                                                                                                                                 ; Merged with sl_int_ipAddr[11]                                                                                                                                                                                                                                                                                                                         ;
; sl_int_ipAddr[11]                                                                                                                                                                                                                                                                                                                                                                ; Merged with sl_int_ipAddr[16]                                                                                                                                                                                                                                                                                                                         ;
; sl_int_ipAddr[16]                                                                                                                                                                                                                                                                                                                                                                ; Merged with sl_int_ipAddr[22]                                                                                                                                                                                                                                                                                                                         ;
; sl_int_ipAddr[22]                                                                                                                                                                                                                                                                                                                                                                ; Merged with sl_int_ipAddr[28]                                                                                                                                                                                                                                                                                                                         ;
; sl_int_ipAddr[28]                                                                                                                                                                                                                                                                                                                                                                ; Merged with sl_int_macAddr[14]                                                                                                                                                                                                                                                                                                                        ;
; sl_int_macAddr[14]                                                                                                                                                                                                                                                                                                                                                               ; Merged with sl_int_macAddr[7]                                                                                                                                                                                                                                                                                                                         ;
; sl_int_macAddr[7]                                                                                                                                                                                                                                                                                                                                                                ; Merged with sl_int_macAddr[8]                                                                                                                                                                                                                                                                                                                         ;
; sl_int_macAddr[8]                                                                                                                                                                                                                                                                                                                                                                ; Merged with sl_int_macAddr[9]                                                                                                                                                                                                                                                                                                                         ;
; sl_int_macAddr[9]                                                                                                                                                                                                                                                                                                                                                                ; Merged with sl_int_macAddr[12]                                                                                                                                                                                                                                                                                                                        ;
; sl_int_macAddr[12]                                                                                                                                                                                                                                                                                                                                                               ; Merged with sl_int_macAddr[15]                                                                                                                                                                                                                                                                                                                        ;
; sl_int_macAddr[15]                                                                                                                                                                                                                                                                                                                                                               ; Merged with sl_int_macAddr[17]                                                                                                                                                                                                                                                                                                                        ;
; sl_int_macAddr[17]                                                                                                                                                                                                                                                                                                                                                               ; Merged with sl_int_macAddr[18]                                                                                                                                                                                                                                                                                                                        ;
; sl_int_macAddr[18]                                                                                                                                                                                                                                                                                                                                                               ; Merged with sl_int_macAddr[20]                                                                                                                                                                                                                                                                                                                        ;
; sl_int_macAddr[20]                                                                                                                                                                                                                                                                                                                                                               ; Merged with sl_int_macAddr[21]                                                                                                                                                                                                                                                                                                                        ;
; sl_int_macAddr[21]                                                                                                                                                                                                                                                                                                                                                               ; Merged with sl_int_macAddr[33]                                                                                                                                                                                                                                                                                                                        ;
; sl_int_macAddr[33]                                                                                                                                                                                                                                                                                                                                                               ; Merged with sl_int_macAddr[35]                                                                                                                                                                                                                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|eth_mode                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|ethernet_mode                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[3]                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[2]                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[2]                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[0]                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[0]                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[21]                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[21]                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[23]                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[23]                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[25]                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[25]                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[7]                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[7]                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[26]                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[26]                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[19]                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[19]                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[27]                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[27]                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[28]                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[28]                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[30]                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[30]                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[31]                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[31]                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[18]                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[18]                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[0]                                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[0]                                                                                                                                                                               ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[3]                                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[3]                                                                                                                                                                               ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[5]                                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[5]                                                                                                                                                                               ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[7]                                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[7]                                                                                                                                                                               ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[9]                                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[9]                                                                                                                                                                               ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[10]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[10]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[11]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[11]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[12]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[12]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[14]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[14]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[15]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[15]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[16]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[16]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[28]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[28]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[18]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[18]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[19]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[19]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[21]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[21]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[23]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[23]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[25]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[25]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[26]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[26]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[27]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[27]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[2]                                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[2]                                                                                                                                                                               ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[30]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[30]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[31]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator|av_readdata_pre[31]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[16]                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[16]                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[15]                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[15]                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[14]                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[14]                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[12]                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[12]                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[11]                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[11]                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[10]                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[10]                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[9]                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[9]                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[5]                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[1]                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[3]                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[3]                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[4]                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[4]                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[5]                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[5]                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[6]                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[6]                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[7]                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[7]                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[9]                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[9]                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[10]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[10]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[11]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[11]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[12]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[12]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[13]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[13]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[14]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[14]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[15]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[15]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[16]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[16]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[17]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[17]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[18]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[18]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[19]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[19]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[20]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[20]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[21]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[21]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[22]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[22]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[23]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[23]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[24]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[24]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[25]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[25]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[26]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[26]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[27]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[27]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[8]                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[8]                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[31]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[31]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[30]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[30]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[29]                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[29]                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg|oci_ienable[28]                                                                          ;
; sl_int_ipAddr[27]                                                                                                                                                                                                                                                                                                                                                                ; Merged with sl_int_brdAddr[3]                                                                                                                                                                                                                                                                                                                         ;
; sl_int_macAddr[43]                                                                                                                                                                                                                                                                                                                                                               ; Merged with sl_int_brdAddr[3]                                                                                                                                                                                                                                                                                                                         ;
; sl_int_ipAddr[26]                                                                                                                                                                                                                                                                                                                                                                ; Merged with sl_int_brdAddr[2]                                                                                                                                                                                                                                                                                                                         ;
; sl_int_macAddr[42]                                                                                                                                                                                                                                                                                                                                                               ; Merged with sl_int_brdAddr[2]                                                                                                                                                                                                                                                                                                                         ;
; sl_int_ipAddr[25]                                                                                                                                                                                                                                                                                                                                                                ; Merged with sl_int_brdAddr[1]                                                                                                                                                                                                                                                                                                                         ;
; sl_int_macAddr[41]                                                                                                                                                                                                                                                                                                                                                               ; Merged with sl_int_brdAddr[1]                                                                                                                                                                                                                                                                                                                         ;
; sl_int_ipAddr[24]                                                                                                                                                                                                                                                                                                                                                                ; Merged with sl_int_brdAddr[0]                                                                                                                                                                                                                                                                                                                         ;
; sl_int_macAddr[40]                                                                                                                                                                                                                                                                                                                                                               ; Merged with sl_int_brdAddr[0]                                                                                                                                                                                                                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_byteen[13..15]                                                                                                                                                                                                               ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_data[31]                                                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_data[14]                                                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_data[31]                                                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_byteen[0]                                                                                                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_byteen[1]                                                                                                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_traffic_limiter:enet_tx_msgdma_mm_read_limiter|last_channel[1]                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_traffic_limiter:enet_tx_msgdma_mm_read_limiter|last_dest_id[0]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[1][58]                                                                                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[1][85]                                                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[1][57]                                                                                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[1][84]                                                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[1][50]                                                                                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[1][56]                                                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[1][58]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[1][85]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[1][50]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[1][84]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[1][56]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[1][57]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_bwrap_field[0..2]                                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_endofpacket                                                                                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_byte_cnt_field[2]                                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_endofpacket                                                                                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_byte_cnt_field[1,3,4]                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[1]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[0]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[1]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_byte_cnt_field[0]                                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[1]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_last_field[21]                                                                                                                                                       ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_last_field[22]                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][62]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][56]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][62]                                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][56]                                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][56]                                                                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][62]                                                                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][62]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][56]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][82]                                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][82]                                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][56]                                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][81]                                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][81]                                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][62]                                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][81]                                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][81]                                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][65]                                                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][66]                                                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][63]                                                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][66]                                                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][62]                                                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][66]                                                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][56]                                                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][66]                                                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][62]                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][66]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][56]                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][66]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][65]                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][66]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][63]                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][66]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][63]                                                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][66]                                                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][65]                                                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][66]                                                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][56]                                                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][62]                                                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][56]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][66]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][63]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][65]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][62]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][65]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][171]                                                                                                                                                                          ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][173]                                                                                                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][172]                                                                                                                                                                          ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][173]                                                                                                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][56]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][82]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][82]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][82]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][62]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][82]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][65]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][82]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][82]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][63]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][82]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][62]                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][65]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][56]                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][65]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][63]                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][65]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][56]                                                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][66]                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][65]                                                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][66]                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][63]                                                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][66]                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][62]                                                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][66]                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][65]                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][66]                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][56]                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][66]                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][63]                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][66]                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][52]                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][85]                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][50]                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][51]                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][44]                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][51]                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][52]                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][85]                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][44]                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][51]                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][50]                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][51]                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][52]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][85]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][50]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][51]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][44]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][51]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][52]                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][85]                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][50]                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][51]                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][44]                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][51]                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][52]                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][85]                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][50]                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][51]                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][44]                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][51]                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][52]                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][85]                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][44]                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][51]                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][50]                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][51]                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][52]                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][85]                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][50]                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][51]                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][44]                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][51]                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][52]                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][85]                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][50]                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][51]                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][44]                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][51]                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][52]                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][85]                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][50]                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][51]                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][44]                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][51]                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][52]                                                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][85]                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][44]                                                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][51]                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][50]                                                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][51]                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][52]                                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][85]                                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][50]                                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][51]                                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][44]                                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][51]                                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][52]                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][85]                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][50]                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][51]                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][44]                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][51]                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][52]                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][85]                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][44]                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][51]                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][50]                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][51]                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][52]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][85]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][44]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][51]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][50]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][51]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][52]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][85]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][50]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][51]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][44]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][51]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|tx_rden                                                                                                       ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|frm_rd[0]                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|data_i[7]                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|rd_5[7]                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|data_i[6]                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|rd_5[6]                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|data_i[5]                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|rd_5[5]                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|data_i[4]                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|rd_5[4]                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|data_i[3]                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|rd_5[3]                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|data_i[2]                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|rd_5[2]                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|data_i[1]                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|rd_5[1]                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|data_i[0]                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|rd_5[0]                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|altera_tse_crc32ctl8:U_CTL|eof_dly[0]                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|eop[5]                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|eop[6]                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|altera_tse_crc32ctl8:U_CTL|eof_dly[1] ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_crc328checker:U_CRC|data_i[7]                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|rxd_25[7]                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_crc328checker:U_CRC|data_i[6]                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|rxd_25[6]                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_crc328checker:U_CRC|data_i[5]                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|rxd_25[5]                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_crc328checker:U_CRC|data_i[4]                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|rxd_25[4]                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_crc328checker:U_CRC|data_i[3]                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|rxd_25[3]                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_crc328checker:U_CRC|data_i[2]                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|rxd_25[2]                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_crc328checker:U_CRC|data_i[1]                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|rxd_25[1]                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_crc328checker:U_CRC|data_i[0]                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|rxd_25[0]                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_rx_if:U_MRX|mii_rxdv_reg_0                                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_gmii_io:U_GMIF|gm_rx_en_i_reg                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_rx_if:U_MRX|mii_rxd_reg_0[3]                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_gmii_io:U_GMIF|gm_rx_d_i_reg[3]                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_rx_if:U_MRX|mii_rxd_reg_0[2]                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_gmii_io:U_GMIF|gm_rx_d_i_reg[2]                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_rx_if:U_MRX|mii_rxd_reg_0[1]                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_gmii_io:U_GMIF|gm_rx_d_i_reg[1]                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_rx_if:U_MRX|mii_rxd_reg_0[0]                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_gmii_io:U_GMIF|gm_rx_d_i_reg[0]                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT|rxclk_ena_i                                                                                                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_rx_if:U_MRX|mii_clk_ena                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_rx_if:U_MRX|mii_rxdv_o                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_rx_if:U_MRX|packet_in_progress                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|in_data_toggle                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|in_data_toggle                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block|control[2]                                                                                                                                                                                               ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block|control[6]                                                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block|control[1]                                                                                                                                                                                               ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block|control[5]                                                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[1]                                                                                                                                                                                                                                                               ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[2]                                                                                                                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[1][56]                                                                                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[1][84]                                                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[1][57]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[1][84]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[1]                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[0]                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][82]                                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][62]                                                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][66]                                                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][65]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][66]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][170]                                                                                                                                                                          ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][173]                                                                                                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][65]                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][66]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][62]                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][66]                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[1]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[2]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|altera_tse_crc32ctl8:U_CTL|eof_dly[2]                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|eop[7]                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|eop[8]                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|altera_tse_crc32ctl8:U_CTL|eof_dly[3] ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|altera_tse_crc32ctl8:U_CTL|eof_dly[4]                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|eop[9]                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|eop[10]                                                                                                       ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|altera_tse_crc32ctl8:U_CTL|eof_dly[5] ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_res_vlan_wait                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][62]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][63]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][65]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][66]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][62]                                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][62]                                                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][56]                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][63]                                                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][56]                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][65]                                                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][56]                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][66]                                                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][56]                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][62]                                                                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][62]                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][63]                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][65]                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][66]                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][62]                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][56]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][63]                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][56]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][65]                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][56]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][66]                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][56]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][171]                                                                                                                                                                          ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][170]                                                                                                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][172]                                                                                                                                                                          ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][170]                                                                                                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][173]                                                                                                                                                                          ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][170]                                                                                                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][62]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][63]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][65]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][66]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][85]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][52]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][50]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][44]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][51]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][44]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][85]                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][52]                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][50]                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][44]                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][51]                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][44]                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][85]                                                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][52]                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][50]                                                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][44]                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][51]                                                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][44]                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][85]                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][52]                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][50]                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][44]                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][51]                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][44]                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][85]                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][52]                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][50]                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][44]                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][51]                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][44]                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][85]                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][52]                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][50]                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][44]                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][51]                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][44]                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][85]                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][52]                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][50]                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][44]                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][51]                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][44]                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][85]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][52]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][50]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][44]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][51]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][44]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][85]                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][52]                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][50]                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][44]                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][51]                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][44]                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][85]                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][52]                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][50]                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][44]                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][51]                                                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][44]                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][62]                                                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][56]                                                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][63]                                                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][56]                                                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][65]                                                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][56]                                                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][66]                                                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][56]                                                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][62]                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][56]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][63]                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][56]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][65]                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][56]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][66]                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][56]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][62]                                                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][56]                                                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][63]                                                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][56]                                                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][65]                                                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][56]                                                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][66]                                                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][56]                                                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][62]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][62]                                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][62]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[0][50]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[0][57]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[0][50]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[0][84]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[0][50]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[0][50]                                                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[0][57]                                                                                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[0][50]                                                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[0][84]                                                                                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[0][50]                                                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[0][85]                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[0][58]                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[0][85]                                                                                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[0][58]                                                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_base[1]                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_base[0]                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][62]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][56]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][63]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][56]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][65]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][56]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][56]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_byteen[9]                                                                                                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_byteen[8]                                                                                                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[1,3,8,9,16,22,28]                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[11]                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[1,3,6,12]                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[11]                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[7..9,12,14,15,17,18,20,21]                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[11]                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][62]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][56]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][63]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][56]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][65]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][56]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][66]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][56]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[8]                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[24]                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[9]                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[25]                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[10]                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[26]                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[11]                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[27]                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[1,3,6]                                                                                                                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[12]                                                                                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[1,3,8,9,11,16,22,28]                                                                                                                                                                                               ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[12]                                                                                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[7..9,12,14,15,17,18,20,21]                                                                                                                                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[12]                                                                                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][62]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][56]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][63]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][56]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][65]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][56]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][66]                                                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][56]                                                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[24]                                                                                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[8]                                                                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[25]                                                                                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[9]                                                                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[26]                                                                                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[10]                                                                                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[27]                                                                                                                                                                                                                ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[11]                                                                                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_chksum_add0[8]                                                                                                                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_chksum_add0[12]                                                                                                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[26,27]                                                                                                                                                                                                                                                                                           ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[25]                                                                                                                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[9,11]                                                                                                                                                                                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[10]                                                                                                                                                                                                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_rx_if:U_MRX|mii_rxerr_reg_0                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_gmii_io:U_GMIF|gm_rx_err_i_reg                                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][85]                                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][52]                                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][50]                                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][44]                                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][51]                                                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][44]                                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][85]                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][52]                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][50]                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][44]                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][51]                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][44]                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][85]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][52]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][50]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][44]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][51]                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][44]                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][85]                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][52]                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][50]                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][44]                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][51]                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][44]                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][85]                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][52]                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][50]                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][44]                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][51]                                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][44]                                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_cmpr_read                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][82]                                                                                                                                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][173]                                                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][82]                                                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][66]                                                                                                                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[0..31]                                                                                                                                                    ; Stuck at GND due to stuck port clock_enable                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_byteen_field[0..3]                                                                                                                                                   ; Stuck at GND due to stuck port clock_enable                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[1..19]                                                                                                                                                 ; Stuck at GND due to stuck port clock_enable                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_last_field[22,23]                                                                                                                                                    ; Stuck at GND due to stuck port clock_enable                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_base[0,2,3]                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][170]                                                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_use_reg                                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[0]                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][164]                                                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[32..42,64..75]                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[0..15]                                                                                                                                                           ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][164]                                                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[2..19]                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                           ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][208]                                                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][100]                                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                           ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][208]                                                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][100]                                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_009|share_count_zero_flag                                                                                                                                                                                     ; Stuck at VCC due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003|share_count_zero_flag                                                                                                                                                                                     ; Stuck at VCC due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_009|share_count[0]                                                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003|share_count[0]                                                                                                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|address_counter[0,1]                                                                                                                                                                                                           ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:nios2_debug_mem_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:nios2_debug_mem_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][66]                                                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][56]                                                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][56]                                                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][56]                                                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_dbrk:the_nios2_nios2_cpu_nios2_oci_dbrk|dbrk_break                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][100]                                                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][100]                                                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][100]                                                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                                                               ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_tx_dpram_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_tx_dpram_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:onchip_mem_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:onchip_mem_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:version_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:version_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:testing_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:testing_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:rot_switch_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                          ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:rot_switch_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|in_data_toggle                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:version_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:version_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:testing_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:testing_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:rot_switch_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                          ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:rot_switch_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_rx_dpram_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_rx_dpram_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_ctrl_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                                                                 ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_ctrl_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                                                          ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_response_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                                                    ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_response_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_csr_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_csr_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                                                             ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fabric_if_if_bridge_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                                                  ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fabric_if_if_bridge_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_descriptor_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0..2]                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_descriptor_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_csr_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                                                         ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_csr_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:eth_tse_mac_control_port_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:eth_tse_mac_control_port_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                                              ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_csr_translator|waitrequest_reset_override                                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator|av_readdata_pre[5]                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[1][84]                                                                                                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[1][84]                                                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[0][50]                                                                                                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[0][50]                                                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_descriptor_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[5]                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_descriptor_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[4]                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[10]                                                                                                                                                                                                                                                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[25]                                                                                                                                                                                                                                                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET|sl_int_addr[1]                                                                                                                                                                                                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_error[2]                                                                                                                                                                                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_cmd_process_error[3]                                                                                                                                                                                                                                                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_error[7]                                                                                                                                                                                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_p_lgth_inf_42_reg[0]                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[0..17]                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_p_lgth_inf_42_reg[1]                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_udp_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                                                          ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_udp_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_nios_tx_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]                                                                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_nios_tx_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block|control[0,6]                                                                                                                                                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_udp_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                                                          ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_udp_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_nios_tx_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]                                                                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_nios_tx_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|address_counter[0,1]                                                                                                                                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_break:the_nios2_nios2_cpu_nios2_oci_break|trigger_state                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][64]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:nios2_debug_mem_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:nios2_debug_mem_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1..5]                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:version_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:version_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                                           ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:testing_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:testing_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                                           ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                               ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                               ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:rot_switch_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:rot_switch_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                               ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                                       ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1..5]                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_tx_dpram_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_tx_dpram_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1..5]                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:onchip_mem_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:onchip_mem_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1..5]                                                                                                                           ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][174]                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_descriptor_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                       ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_descriptor_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3,4]                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_rx_dpram_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_rx_dpram_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1..5]                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_ctrl_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_ctrl_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1..5]                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][64]                                                                                                                                                                                   ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_response_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                               ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_response_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1..5]                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][64]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_csr_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_csr_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1..5]                                                                                                                      ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][64]                                                                                                                                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1..5]                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][64]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][64]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][64]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][64]                                                                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fabric_if_if_bridge_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fabric_if_if_bridge_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1..5]                                                                                                               ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][64]                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_csr_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_csr_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1..5]                                                                                                                      ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][64]                                                                                                                                                                                  ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:eth_tse_mac_control_port_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:eth_tse_mac_control_port_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1..5]                                                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][64]                                                                                                                                                                             ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1..5]                                                                                                           ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_udp_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_udp_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                                                                        ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_nios_tx_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                 ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_nios_tx_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1,2]                                                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_endofpacket                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_error[2,7]                                                                                                                                                                                                                                                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2..5]                                                                                           ; Stuck at GND due to stuck port clock_enable                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                         ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_state.ERR                                                                                                                                                                                                                                                                                                     ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|state~4                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|state~5                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|state~6                                                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state~2                                                                                                                                                                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state~3                                                                                                                                                                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state~4                                                                                                                                                                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state~5                                                                                                                                                                                                                                    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|state~8                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|state~9                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_wrt_cntl:U_LBW|state~8                                                                                                                           ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_wrt_cntl:U_LBW|state~9                                                                                                                           ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|state~4                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|state~5                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|state~6                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|state~7                                                                                                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_cntl:U_CNTL|state~18                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_cntl:U_CNTL|state~19                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_cntl:U_CNTL|state~20                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_cntl:U_CNTL|state~21                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|DRsize~3                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|DRsize~4                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|DRsize~5                                              ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_almostfull_threshold_register[11]                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_almostempty_threshold_register[11]                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[11]                                                                                                                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[11]                                                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|state.stm_typ_idle                                                                               ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|state.stm_typ_sfd                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|state.stm_typ_frm                                                                                ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|state.stm_typ_end_frm                                                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_state.GET_CONFIG_ARG_CHECK_FIFO_DELAY                                                                                                                                                                                                                                                                        ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_state.WR_DELAY                                                                                                                                                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_state.GET_CONFIG_CMD_DELAY                                                                                                                                                                                                                                                                                   ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_state.WR_DELAY                                                                                                                                                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_state.WR_DELAY                                                                                                                                                                                                                                                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_state.CMD_SET_CONFIG_CMD_PROCESS_DELAY                                                                                                                                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_state.WAIT_FIFO_PROCESS_DELAY                                                                                                                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_state.CMD_DECODE_DELAY                                                                                                                                                                                                                                                                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_state.WAIT_FIFO_PROCESS_DELAY                                                                                                                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_state.CMD_2FRM_PROCESS_DELAY                                                                                                                                                                                                                                                                                      ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_state.WAIT_FIFO_PROCESS_DELAY                                                                                                                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_state.CMD_NOT_ADRRESSED_DELAY                                                                                                                                                                                                                                                                                     ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_state.WAIT_FIFO_PROCESS_DELAY                                                                                                                                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_state.WAIT_FIFO_PROCESS_DELAY                                                                                                                                                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_state.CMD_NOT_ADRRESSED                                                                                                                                                                                                                                                                                           ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|DRsize.101                                            ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|DRsize.001                                            ; Merged with ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|DRsize.011     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_break:the_nios2_nios2_cpu_nios2_oci_break|trigbrktype                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|DRsize.011                                            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0,1] ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1    ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_wr_cnt[0,1]                                                                                                                                                                                                                                                                                          ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_RX_fifo_rd_cnt[0,1]                                                                                                                                                                                                                                                                                               ; Lost fanout                                                                                                                                                                                                                                                                                                                                           ;
; Total Number of Removed Registers = 2677                                                                                                                                                                                                                                                                                                                                         ;                                                                                                                                                                                                                                                                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                                                                                                                                                                                                                                  ; Reason for Removal             ; Registers Removed due to This Register                                                                                                                                                                                                                                                                                                                                          ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_cmpr_read                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[31],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[30],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[29],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[28],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[27],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[26],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[25],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[24],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[23],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[22],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[21],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[20],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[19],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[18],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[17],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[16],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[15],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[14],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[13],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[12],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[11],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[10],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[9],                                                                                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[8],                                                                                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[7],                                                                                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[6],                                                                                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[5],                                                                                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[4],                                                                                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[3],                                                                                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[2],                                                                                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[1],                                                                                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_data_field[0],                                                                                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_byteen_field[3],                                                                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_byteen_field[2],                                                                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_byteen_field[1],                                                                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_byteen_field[0],                                                                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[19],                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[18],                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[17],                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[16],                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[15],                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[14],                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[13],                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[12],                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[11],                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[10],                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[9],                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[8],                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[7],                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[6],                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[5],                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[4],                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[3],                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[2],                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_address_field[1],                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_last_field[23],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_last_field[22],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_base[3],                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_base[2],                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_base[0],                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[73],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[72],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[71],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[70],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[69],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[68],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[67],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[66],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[65],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[64],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[42],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[41],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[40],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[39],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[38],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[37],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[36],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[35],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[34],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[33],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[32],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[15],                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[13],                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[12],                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[11],                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[10],                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[9],                                                                                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[8],                                                                                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[7],                                                                                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[6],                                                                                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[5],                                                                                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[4],                                                                                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[3],                                                                                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[2],                                                                                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[1],                                                                                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[0],                                                                                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[16],                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[15],                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[14],                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[13],                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[12],                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[11],                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[10],                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[9],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[8],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[7],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[6],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[5],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[4],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[3],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[2],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][208],                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][208],                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[5],                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_type[0]                                                                                                ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_type[1],                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_frm,                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_frm_s,                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_frm_s2,                                                                                                 ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[15],                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[14],                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[13],                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[12],                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[11],                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[10],                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[9],                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[8],                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[7],                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[6],                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[5],                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[4],                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[3],                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[2],                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[1],                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_length[0],                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_status,                                                                                                 ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_p_lgth_inf_42_reg[0],                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[0],                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[1],                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[2],                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[3],                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[4],                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[5],                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[6],                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[7],                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[8],                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[9],                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[10],                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[11],                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[12],                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[13],                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[14],                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[15],                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[16],                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_end_64_vlan_reg[17],                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|vlan_p_lgth_inf_42_reg[1]                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[16]                                                                                         ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[15],                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[14],                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[13],                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[12],                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[11],                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[10],                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[9],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[8],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[7],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[6],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[5],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[4],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[3],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[2],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[1],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|unicast_add_reg[0]                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|multicast_add_reg[14]                                                                                       ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|multicast_add_reg[13],                                                                                       ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|multicast_add_reg[12],                                                                                       ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|multicast_add_reg[11],                                                                                       ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|multicast_add_reg[10],                                                                                       ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|multicast_add_reg[9],                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|multicast_add_reg[8],                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|multicast_add_reg[7],                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|multicast_add_reg[6],                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|multicast_add_reg[5],                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|multicast_add_reg[4],                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|multicast_add_reg[3],                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|multicast_add_reg[2],                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|multicast_add_reg[1],                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|multicast_add_reg[0]                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_data[30]                                                                                                                                                                                                                   ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_byteen[3],                                                                                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_byteen[11],                                                                                                                                                                                                                 ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|write_address[3],                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|write_address[2],                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|write_address[1],                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|write_address[0]                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|pause_frm[0]                                                                                                ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_12|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1],             ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_12|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0],             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_eth_tse_std_synchronizer:U_SYNC_12|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1,              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|pause_frm[1],                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|pause_frm_l,                                                                                                 ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|p_sup_64                                                                                                     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_use_reg                                                                                                                                                                ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[75],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|data_reg[74],                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|byteen_reg[14],                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[4],                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3],                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][82]                                                                                                                                                                               ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][82],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][82],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][82],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][82],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fabric_if_if_bridge_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                            ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|init_done_forever                                                                                                                                                                                                                                       ; Stuck at VCC                   ; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|count[5],                                                                                                                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|count[4],                                                                                                                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|count[3],                                                                                                                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|count[2]                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|stack_vlan_type[0]                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|stack_vlan_type[1],                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|stack_vlan_status,                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_res_vlan,                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|cnt_res_vlan_wait                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][81]                                                                                                                                                                               ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][81],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][81],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][81],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][81]                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][80]                                                                                                                                                                               ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][80],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][80],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][80],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][80]                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][79]                                                                                                                                                                               ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][79],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][79],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][79],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][79]                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][66]                                                                                                                                                                               ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][56],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][56],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][56],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[4][100]                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][100],                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][100],                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][100],                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][100]                                                                                                                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|state~8                                                                                        ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|state.stm_typ_idle,                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|state.stm_typ_sfd,                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|state.stm_typ_frm,                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|state.stm_typ_end_frm                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][190]                                                                                                                                                                        ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_last_field[46],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][190],                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_descriptor_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                      ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|count[6]                                                                                                                                                                                                                                                ; Stuck at GND                   ; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|rst_n[1],                                                                                                                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port clock_enable ; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|rst_n[0],                                                                                                                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|ser_shift_load                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[0][64]                                                                                                                                                                               ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[1][64],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[2][64],                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem[3][64]                                                                                                                                                                                ;
; sl_int_ipAddr[5]                                                                                                                                                                                                                                                                                                                                                               ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[5],                                                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[5]                                                                                                                                       ;
; sl_int_ipAddr[4]                                                                                                                                                                                                                                                                                                                                                               ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[4],                                                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[4]                                                                                                                                       ;
; sl_int_ipAddr[2]                                                                                                                                                                                                                                                                                                                                                               ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[2],                                                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[2]                                                                                                                                       ;
; sl_int_ipAddr[0]                                                                                                                                                                                                                                                                                                                                                               ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[0],                                                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[0]                                                                                                                                       ;
; sl_int_macAddr[47]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[15],                                                                                                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[15]                                                                                                                                   ;
; sl_int_macAddr[46]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[14],                                                                                                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[14]                                                                                                                                   ;
; sl_int_macAddr[45]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[13],                                                                                                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[13]                                                                                                                                   ;
; sl_int_macAddr[39]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[7],                                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[7]                                                                                                                                    ;
; sl_int_macAddr[37]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[5],                                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[5]                                                                                                                                    ;
; sl_int_macAddr[36]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[4],                                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[4]                                                                                                                                    ;
; sl_int_macAddr[34]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[2],                                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[2]                                                                                                                                    ;
; sl_int_macAddr[32]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[0],                                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[0]                                                                                                                                    ;
; sl_int_macAddr[31]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[31],                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[31]                                                                                                                                   ;
; sl_int_macAddr[30]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[30],                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[30]                                                                                                                                   ;
; sl_int_macAddr[29]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[29],                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[29]                                                                                                                                   ;
; sl_int_macAddr[28]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[28],                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[28]                                                                                                                                   ;
; sl_int_macAddr[27]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[27],                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[27]                                                                                                                                   ;
; sl_int_macAddr[26]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[26],                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[26]                                                                                                                                   ;
; sl_int_macAddr[25]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[25],                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[25]                                                                                                                                   ;
; sl_int_macAddr[24]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[24],                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[24]                                                                                                                                   ;
; sl_int_macAddr[23]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[23],                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[23]                                                                                                                                   ;
; sl_int_macAddr[22]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[22],                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[22]                                                                                                                                   ;
; sl_int_macAddr[19]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[19],                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[19]                                                                                                                                   ;
; sl_int_macAddr[16]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[16],                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[16]                                                                                                                                   ;
; sl_int_macAddr[13]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[13],                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[13]                                                                                                                                   ;
; sl_int_macAddr[11]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[11],                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[11]                                                                                                                                   ;
; sl_int_macAddr[10]                                                                                                                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[10],                                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[10]                                                                                                                                   ;
; sl_int_macAddr[6]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[6],                                                                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[6]                                                                                                                                    ;
; sl_int_macAddr[5]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[5],                                                                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[5]                                                                                                                                    ;
; sl_int_macAddr[4]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[4],                                                                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[4]                                                                                                                                    ;
; sl_int_macAddr[3]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[3],                                                                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[3]                                                                                                                                    ;
; sl_int_macAddr[2]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[2],                                                                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[2]                                                                                                                                    ;
; sl_int_macAddr[1]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[1],                                                                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[1]                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_data[23]                                                                                                                                                                                                                   ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_byteen[2],                                                                                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_byteen[10]                                                                                                                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[0][53]                                                                                                                                                                                       ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[1][53],                                                                                                                                                                                       ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_udp_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                    ;
; sl_int_macAddr[0]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_mac_addr_l_in|readdata[0],                                                                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|av_readdata_pre[0]                                                                                                                                    ;
; sl_int_ipAddr[31]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[31],                                                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[31]                                                                                                                                      ;
; sl_int_ipAddr[30]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[30],                                                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[30]                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][82]                                                                                                                                                                           ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][82],                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                    ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0],                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_LATE_COL|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1]                  ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0],                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL|altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[0][53]                                                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[1][53],                                                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_nios_tx_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][82],                                                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_rx_dpram_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                            ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][82],                                                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                              ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][82],                                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_ctrl_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][82],                                                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_tx_dpram_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                 ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][82],                                                                                                                                                                                 ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_response_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                      ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][82],                                                                                                                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_csr_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                          ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][82],                                                                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                       ;
; sl_int_ipAddr[29]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[29],                                                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[29]                                                                                                                                      ;
; sl_int_ipAddr[23]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[23],                                                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[23]                                                                                                                                      ;
; sl_int_ipAddr[21]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[21],                                                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[21]                                                                                                                                      ;
; sl_int_ipAddr[20]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[20],                                                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[20]                                                                                                                                      ;
; sl_int_ipAddr[19]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[19],                                                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[19]                                                                                                                                      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][189]                                                                                                                                                                        ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_last_field[45],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][189]                                                                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][188]                                                                                                                                                                        ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_last_field[44],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][188]                                                                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][187]                                                                                                                                                                        ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|p0_reg_last_field[43],                                                                                                                                                     ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][187]                                                                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                      ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][82],                                                                                                                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_csr_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][82]                                                                                                                                                                                ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][82],                                                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:eth_tse_mac_control_port_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][66],                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][66],                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][66],                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                          ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][66],                                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:version_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                          ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][66],                                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:testing_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                              ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][66],                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                              ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][66],                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                               ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][66],                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                               ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][66],                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                       ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][66],                                                                                                                                                       ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:rot_switch_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                  ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][66],                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                 ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][66],                                                                                                                                                 ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                              ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                      ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][66],                                                                                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][66],                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][66]                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][66],                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy                                                                                                ;
; sl_int_ipAddr[18]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[18],                                                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[18]                                                                                                                                      ;
; sl_int_ipAddr[17]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[17],                                                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[17]                                                                                                                                      ;
; sl_int_ipAddr[15]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[15],                                                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[15]                                                                                                                                      ;
; sl_int_ipAddr[14]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[14],                                                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[14]                                                                                                                                      ;
; sl_int_ipAddr[13]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[13],                                                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[13]                                                                                                                                      ;
; sl_int_ipAddr[12]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[12],                                                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[12]                                                                                                                                      ;
; sl_int_ipAddr[10]                                                                                                                                                                                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[10],                                                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[10]                                                                                                                                      ;
; sl_int_ipAddr[7]                                                                                                                                                                                                                                                                                                                                                               ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[7],                                                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[7]                                                                                                                                       ;
; sl_int_ipAddr[6]                                                                                                                                                                                                                                                                                                                                                               ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in|readdata[6],                                                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|av_readdata_pre[6]                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_almostfull_threshold_register[11]                                                                                                                                               ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[11],                                                                                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[11]                                                                                                                                                                         ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[1] ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|dreg[0], ;
;                                                                                                                                                                                                                                                                                                                                                                                ;                                ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut|din_s1   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[22]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[22]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[21]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[21]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[20]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[20]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[19]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[19]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[18]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[18]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[17]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[17]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[16]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[16]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[15]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[15]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[14]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[14]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[13]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[13]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[12]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[12]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[11]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[11]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[10]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[10]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[9]                                                                                                                                                                                                                       ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[9]                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[8]                                                                                                                                                                                                                       ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[8]                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[7]                                                                                                                                                                                                                       ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[7]                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[6]                                                                                                                                                                                                                       ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[6]                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[5]                                                                                                                                                                                                                       ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[5]                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[4]                                                                                                                                                                                                                       ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[4]                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[3]                                                                                                                                                                                                                       ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[3]                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[2]                                                                                                                                                                                                                       ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[2]                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[1]                                                                                                                                                                                                                       ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[1]                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[31]                                                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[31]                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[30]                                                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[30]                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[29]                                                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[29]                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[28]                                                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[28]                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[27]                                                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[27]                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[26]                                                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[26]                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[25]                                                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[25]                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[24]                                                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[24]                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[23]                                                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[23]                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[22]                                                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[22]                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[21]                                                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[21]                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[20]                                                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[20]                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[19]                                                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[19]                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[18]                                                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[18]                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[17]                                                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[17]                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_TX_STATUS:own_mac_addr_h_in|readdata[16]                                                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|av_readdata_pre[16]                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio:U_MDIO|mdio_run[19]                                                                                                                                                                         ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio:U_MDIO|read_error                                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|early_done_enable_d1                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|done_d1                                                                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[31]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[31]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[29]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[29]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[28]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[28]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[27]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[27]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[26]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[26]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[25]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[25]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[24]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[24]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[23]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[23]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[22]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[22]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[21]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[21]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[20]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[20]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[19]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[19]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[18]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[18]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[17]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[17]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[16]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[16]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[12]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[12]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[11]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[11]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[10]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[10]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[9]                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[9]                                                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[8]                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[8]                                                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[7]                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[7]                                                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[6]                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[6]                                                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[5]                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[5]                                                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[4]                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[4]                                                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[3]                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[3]                                                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[31]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[31]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[30]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[30]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[29]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[29]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[28]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[28]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[27]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[27]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[26]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[26]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[25]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[25]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[24]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[24]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[23]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[23]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[22]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[22]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[21]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[21]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[20]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[20]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[19]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[19]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[18]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[18]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[17]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[17]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[16]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[16]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[15]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[15]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[14]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[14]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[13]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[13]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_readdata[12]                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|av_readdata_pre[12]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[30]                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[30]                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_word_id[2]                                                                                                                                                                                                                                                                                                 ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[30]                                                                                                                                                                                                                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[0][69]                                                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[1][69]                                                                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_data[1]                                                                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_byteen[12]                                                                                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W1_rf_ecc_recoverable_valid                                                                                                                                                                                                                                 ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_up_ex_mon_state                                                                                                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                            ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                            ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                            ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                             ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[31]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[31]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                              ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                              ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                              ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[30]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[30]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[29]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[29]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                 ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                 ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                 ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[28]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[28]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                      ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                      ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                      ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[27]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[27]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                          ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                          ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                          ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[26]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[26]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[25]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[25]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[24]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[24]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[23]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[23]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[22]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[22]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[21]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[21]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[20]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[20]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[19]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[19]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[18]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[18]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                      ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                      ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                      ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[17]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[17]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][81]                                                                                                                                                                                ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][81]                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][80]                                                                                                                                                                                ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][80]                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][79]                                                                                                                                                                                ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][79]                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[0][69]                                                                                                                                                                                       ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[1][69]                                                                                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][81]                                                                                                                                                                           ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][81]                                                                                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][80]                                                                                                                                                                           ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][80]                                                                                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][79]                                                                                                                                                                           ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][79]                                                                                                                                                                            ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[16]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[16]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[15]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[15]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[14]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[14]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[13]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[13]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                          ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                          ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                          ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[12]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[12]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                          ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                          ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                          ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[11]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[11]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                              ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                              ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                              ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[10]                                                                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[10]                                                                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                              ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                              ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                              ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                               ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[9]                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[9]                                                                                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                               ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                               ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                               ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[8]                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[8]                                                                                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                               ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                               ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                               ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[7]                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[7]                                                                                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                       ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                       ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                       ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[6]                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[6]                                                                                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                  ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                  ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                  ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                   ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[5]                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[5]                                                                                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                 ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                 ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                 ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                  ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[4]                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[4]                                                                                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                      ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                      ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                      ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[3]                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[3]                                                                                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_ienable_reg[1]                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_control_rd_data[1]                                                                                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][65]                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][65]                                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][64]                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][64]                                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][63]                                                                                                                                                   ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][63]                                                                                                                                                    ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[0]                                                                                                                                                                                                                       ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[0]                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status|readdata[0]                                                                                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|av_readdata_pre[0]                                                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_dbrk:the_nios2_nios2_cpu_nios2_oci_dbrk|dbrk_goto1                                                                                                                        ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_break:the_nios2_nios2_cpu_nios2_oci_break|trigger_state                                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_dbrk:the_nios2_nios2_cpu_nios2_oci_dbrk|dbrk_break_pulse                                                                                                                  ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_dbrk:the_nios2_nios2_cpu_nios2_oci_dbrk|dbrk_break                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[31]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[31]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[30]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[30]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                   ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                   ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][82]                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                 ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                       ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][173]                                                                                                                                                                        ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][170]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][82]                                                                                                                                                                                   ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                       ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][66]                                                                                                                                                                                ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][56]                                                                                                                                                                                 ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][66]                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][56]                                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                 ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                 ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                   ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                               ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                               ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                       ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                  ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                 ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                       ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                   ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][51]                                                                                                                                                   ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][44]                                                                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[29]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[29]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[1][164]                                                                                                                                                                        ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem[0][164]                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                 ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                  ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                           ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                            ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                             ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                              ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                  ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                     ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                         ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                  ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[1][100]                                                                                                                                                                                     ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                      ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[1][100]                                                                                                                                                                               ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo|mem[0][100]                                                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[1][100]                                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo|mem[0][100]                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                 ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                 ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                   ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                          ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                              ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                               ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                               ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                               ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                       ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                  ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                   ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                 ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                  ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                       ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                   ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[1][84]                                                                                                                                                   ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo|mem[0][84]                                                                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_009|share_count_zero_flag                                                                                                                                                                                   ; Stuck at VCC                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_009|share_count[0]                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003|share_count_zero_flag                                                                                                                                                                                   ; Stuck at VCC                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003|share_count[0]                                                                                                                                                                                           ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[28]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[28]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[27]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[27]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[1][84]                                                                                                                                                                                       ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo|mem[0][50]                                                                                                                                                                                        ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[1][84]                                                                                                                                                                                   ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo|mem[0][50]                                                                                                                                                                                    ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[10]                                                                                                                                                                                                                                                                                                    ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[25]                                                                                                                                                                                                                                                                                             ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_cmd_process_error[3]                                                                                                                                                                                                                                                                                            ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_error[7]                                                                                                                                                                                                                                                                                                         ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[26]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[26]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[25]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[25]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|DRsize~3                                            ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|DRsize.101                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[24]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[24]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch|readdata[23]                                                                                                                                                                                                                      ; Stuck at GND                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|av_readdata_pre[23]                                                                                                                                          ;
;                                                                                                                                                                                                                                                                                                                                                                                ; due to stuck port data_in      ;                                                                                                                                                                                                                                                                                                                                                                                 ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_wr_cnt[1]                                                                                                                                                                                                                                                                                          ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_wr_cnt[0]                                                                                                                                                                                                                                                                                           ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_RX_fifo_rd_cnt[1]                                                                                                                                                                                                                                                                                               ; Lost Fanouts                   ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_RX_fifo_rd_cnt[0]                                                                                                                                                                                                                                                                                                ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 9976  ;
; Number of registers using Synchronous Clear  ; 1458  ;
; Number of registers using Synchronous Load   ; 779   ;
; Number of registers using Asynchronous Clear ; 9335  ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 4155  ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                                                                                                                                                                                               ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                                                                                                                                                                                                ; Fan out ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[9]                                ; 3       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[10]                               ; 3       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[5]                                ; 3       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[6]                                ; 3       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[7]                                ; 3       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[8]                                ; 3       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[0]                                ; 2       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[1]                                ; 3       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[2]                                ; 3       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[3]                                ; 3       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[4]                                ; 3       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[11]                               ; 1       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[12]                               ; 1       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[13]                               ; 1       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[14]                               ; 1       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[15]                               ; 1       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_1|altera_tse_reset_synchronizer_chain_out                                                                                       ; 593     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_4|altera_tse_reset_synchronizer_chain_out                                                                                       ; 490     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_1|altera_tse_reset_synchronizer_chain[0]                                                                                        ; 1       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_4|altera_tse_reset_synchronizer_chain[0]                                                                                        ; 1       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|mdio_oen                                                                                                                                      ; 1       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:nios2_debug_mem_slave_translator|waitrequest_reset_override                                                                                                ; 14      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0 ; 8       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|count[9]                                                                                                                                        ; 11      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_1|altera_tse_reset_synchronizer_chain[1]                                                                                        ; 1       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|r_sync_rst_chain[1]                                                                                                                                                                          ; 1       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                                                                                      ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                                                                                      ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                                                                                      ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                                                                                      ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                                                                                        ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                                                                                        ; 10      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                                                                                        ; 10      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                                                                                        ; 12      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                                                                                        ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                                                                                        ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                                                                                      ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                                                                                        ; 10      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                                                                                      ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                                                                                      ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                                                                                        ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                                                                                      ; 11      ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_qdc:wrptr_g1p|counter8a0                                                                                                                                                                                                  ; 7       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_4|altera_tse_reset_synchronizer_chain[1]                                                                                        ; 1       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|mdio_oen_int_reg1                                                                                                                             ; 1       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|hbreak_enabled                                                                                                                                                                                ; 6       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:if_bridge_m0_agent|hold_waitrequest                                                                                        ; 23      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_rx_dpram_s1_translator|waitrequest_reset_override                                                                                                ; 15      ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|av_waitrequest                                                                                                                                                                                        ; 5       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0 ; 7       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6    ; 5       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|t_dav                                                                                                                                                                                                 ; 3       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|preamb_wait                                   ; 6       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[3]                                                                                                                                                       ; 1       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|r_sync_rst_chain[2]                                                                                                                                                                          ; 2       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[2]                                                                                                                                                       ; 4       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                                                                                         ; 8       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                                                                                         ; 8       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                                                                                         ; 8       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                                                                                         ; 8       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                                                                                           ; 8       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                                                                                           ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                                                                                           ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                                                                                           ; 8       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                                                                                           ; 8       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                                                                                           ; 8       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                                                                                         ; 8       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                                                                                           ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                                                                                         ; 8       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                                                                                         ; 8       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                                                                                           ; 8       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                                                                                         ; 8       ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_qdc:wrptr_g1p|parity9                                                                                                                                                                                                     ; 5       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio:U_MDIO|mux_out                                                                                                                ; 1       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio:U_MDIO|cd_oe                                                                                                                  ; 1       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|a_graycounter_8ub:wrptr_g1p|counter8a0                                                                                                                                                          ; 7       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|r_sync_rst_chain[1]                                                                                                                                                                      ; 1       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out                                                                                 ; 681     ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|i_read                                                                                                                                                                                        ; 6       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|F_pc[15]                                                                                                                                                                                      ; 2       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_009|altera_merlin_arbitrator:arb|top_priority_reg[0]                                                                                          ; 2       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|snk_command_ready                                                                                                                                              ; 8       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003|altera_merlin_arbitrator:arb|top_priority_reg[0]                                                                                          ; 2       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_cntl:U_CNTL|host_busy_int                                                                                                     ; 4       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9    ; 5       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|rst2                                                                                                                                            ; 3       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|gap_wait                                      ; 6       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|empty_flag                            ; 7       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|r_sync_rst_chain[3]                                                                                                                                                                          ; 1       ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[1]                                                                                                                                                       ; 1       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                                                                                        ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                                                                                        ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                                                                                        ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                                                                                        ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                                                                                      ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                                                                                      ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                                                                                      ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                                                                                      ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                                                                                        ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                                                                                        ; 7       ;
; Total number of inverted registers = 243*                                                                                                                                                                                                                                                                        ;         ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
* Table truncated at 100 items. To change the number of inverted registers reported, set the "Number of Inverted Registers Reported" option under Assignments->Settings->Analysis and Synthesis Settings->More Settings


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Packed Into Inferred Megafunctions                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+
; Register Name                                                                                                                                                                                                                                                                                                                 ; Megafunction                                                                                                                                                                                                                                                                                                           ; Type       ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo|out_data[0..41]                                  ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo|mem_rtl_0                                 ; RAM        ;
; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_altshifttaps:U_SHIFTTAPS|shift_reg[0..15][0..7] ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_altshifttaps:U_SHIFTTAPS|shift_reg_rtl_0 ; SHIFT_TAPS ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                                                                                                                                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                                                                                                                                                                                                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_l_s1_translator|wait_latency_counter[0]                                                                                ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_h_s1_translator|wait_latency_counter[1]                                                                                ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_ip_addr_s1_translator|wait_latency_counter[1]                                                                                   ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_s1_translator|wait_latency_counter[1]                                                                                    ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_s1_translator|wait_latency_counter[1]                                                                                    ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_s1_translator|wait_latency_counter[0]                                                                                       ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_l_s1_translator|wait_latency_counter[1]                                                                               ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_h_s1_translator|wait_latency_counter[0]                                                                               ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_ip_addr_s1_translator|wait_latency_counter[1]                                                                                  ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:version_s1_translator|wait_latency_counter[1]                                                                                           ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:testing_s1_translator|wait_latency_counter[1]                                                                                           ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_ctrl_s1_translator|wait_latency_counter[0]                                                                                                                               ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo|mem_used[3]                                                                                                                                 ;
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block|control[1]                                                                                                                                                ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|read_address[3]                                                                            ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|write_address[0]                                                                           ;
; 3:1                ; 9 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|address_counter[4]                                                                                                                                                              ;
; 3:1                ; 13 bits   ; 26 LEs        ; 0 LEs                ; 26 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|actual_bytes_transferred_counter[0]                                                                                                                                             ;
; 3:1                ; 8 bits    ; 16 LEs        ; 0 LEs                ; 16 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block|control[29]                                                                                                                                               ;
; 3:1                ; 8 bits    ; 16 LEs        ; 0 LEs                ; 16 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block|control[21]                                                                                                                                               ;
; 3:1                ; 8 bits    ; 16 LEs        ; 0 LEs                ; 16 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block|control[12]                                                                                                                                               ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator|wait_latency_counter[1]                                                                                                                       ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_csr_translator|wait_latency_counter[0]                                                                                                                       ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator|wait_latency_counter[1]                                                                                        ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator|wait_latency_counter[1]                                                                                    ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator|wait_latency_counter[1]                                                                                 ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator|wait_latency_counter[1]                                                                                 ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator|wait_latency_counter[1]                                                                                                                             ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|packet_bytes_buffered_d1[1]                                                                                                                                                     ;
; 4:1                ; 12 bits   ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|length_counter[11]                                                                                                                                                              ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|Mux1                                                                                                                                                                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|Mux3                                                                                                                                                                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem                                                                                                                                   ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem                                                                                                                                   ;
; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo|mem                                                                                                                                   ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router:router|src_channel[10]                                                                                                        ;
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|nextstate                                                                                                             ;
; 7:1                ; 8 bits    ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router:router|src_channel[7]                                                                                                         ;
; 13:1               ; 2 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router:router|src_channel[3]                                                                                                                                                       ;
; 3:1                ; 27 bits   ; 54 LEs        ; 0 LEs                ; 54 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|dout_reg_sft[14]                                                                      ;
; 3:1                ; 12 bits   ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|D_iw[20]                                                                                                                                                                                                       ;
; 3:1                ; 20 bits   ; 40 LEs        ; 20 LEs               ; 20 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|D_iw[2]                                                                                                                                                                                                        ;
; 3:1                ; 8 bits    ; 16 LEs        ; 0 LEs                ; 16 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|av_ld_byte0_data[6]                                                                                                                                                                                            ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|av_ld_byte2_data[6]                                                                                                                                                                                            ;
; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|crc_fwd_tmp                                                                           ;
; 9:1                ; 15 bits   ; 90 LEs        ; 30 LEs               ; 60 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_checksum[31]                                                                                                                                                                                ;
; 10:1               ; 8 bits    ; 48 LEs        ; 16 LEs               ; 32 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_checksum[0]                                                                                                                                                                                 ;
; 10:1               ; 9 bits    ; 54 LEs        ; 36 LEs               ; 18 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_checksum[16]                                                                                                                                                                                ;
; 4:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram|altsyncram_pnr1:auto_generated|mux_5hb:mux2|l2_w29_n0_mux_dataout                                                                                                                              ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|fifo_write_data[32]                                                                                                                                                               ;
; 3:1                ; 32 bits   ; 64 LEs        ; 0 LEs                ; 64 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_checksumH[11]                                                                                                                                                                                                                                                                 ;
; 20:1               ; 9 bits    ; 117 LEs       ; 108 LEs              ; 9 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_fifo_data[19]                                                                                                                                                                                                                                                                 ;
; 20:1               ; 3 bits    ; 39 LEs        ; 39 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_fifo_data[22]                                                                                                                                                                                                                                                                 ;
; 21:1               ; 2 bits    ; 28 LEs        ; 28 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_fifo_data[8]                                                                                                                                                                                                                                                                  ;
; 22:1               ; 6 bits    ; 84 LEs        ; 84 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_fifo_data[11]                                                                                                                                                                                                                                                                 ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_next_checksumL[31]                                                                                                                                                                                                                                                                ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX|x_fifo_din[6]                                                                                                                                                                                                      ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED|x_fifo_din[4]                                                                                                                                                                                                        ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX|x_fifo_din[12]                                                                                                                                                                                                     ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED|x_fifo_din[23]                                                                                                                                                                                                       ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX|x_fifo_din[23]                                                                                                                                                                                                     ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED|x_fifo_din[23]                                                                                                                                                                                                       ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX|x_fifo_din[17]                                                                                                                                                                                                     ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED|x_fifo_din[23]                                                                                                                                                                                                       ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX|x_fifo_din[23]                                                                                                                                                                                                     ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED|x_fifo_din[23]                                                                                                                                                                                                       ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX|x_fifo_din[15]                                                                                                                                                                                                     ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED|x_fifo_din[23]                                                                                                                                                                                                       ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX|x_fifo_din[23]                                                                                                                                                                                                     ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED|x_fifo_din[23]                                                                                                                                                                                                       ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX|x_fifo_din[23]                                                                                                                                                                                                     ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED|x_fifo_din[17]                                                                                                                                                                                                       ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX|sl_int_24b_cnt[0]                                                                                                                                                                                                  ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX|sl_int_24b_cnt[0]                                                                                                                                                                                                  ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX|sl_int_24b_cnt[0]                                                                                                                                                                                                  ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX|sl_int_24b_cnt[0]                                                                                                                                                                                                  ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX|sl_int_24b_cnt[0]                                                                                                                                                                                                  ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX|sl_int_24b_cnt[2]                                                                                                                                                                                                  ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX|sl_int_24b_cnt[2]                                                                                                                                                                                                  ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX|sl_int_24b_cnt[0]                                                                                                                                                                                                  ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED|sl_int_24b_cnt[2]                                                                                                                                                                                                    ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED|sl_int_24b_cnt[0]                                                                                                                                                                                                    ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED|sl_int_24b_cnt[2]                                                                                                                                                                                                    ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED|sl_int_24b_cnt[2]                                                                                                                                                                                                    ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED|sl_int_24b_cnt[0]                                                                                                                                                                                                    ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED|sl_int_24b_cnt[0]                                                                                                                                                                                                    ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED|sl_int_24b_cnt[0]                                                                                                                                                                                                    ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED|sl_int_24b_cnt[0]                                                                                                                                                                                                    ;
; 16:1               ; 2 bits    ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|Mux2                                                                                                                                                                                                                                                                                 ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX|sl_next_state.WAIT_PREAMBLE                                                                                                                                                                                        ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX|sl_next_state.IDLE                                                                                                                                                                                                 ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX|sl_next_state.OVERFLOW                                                                                                                                                                                             ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX|sl_next_state.IDLE                                                                                                                                                                                                 ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX|sl_next_state.WAIT_PREAMBLE                                                                                                                                                                                        ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX|sl_next_state.WAIT_END                                                                                                                                                                                             ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX|sl_next_state.TIMEOUT                                                                                                                                                                                              ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX|sl_next_state.IDLE                                                                                                                                                                                                 ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED|sl_next_state.OVERFLOW                                                                                                                                                                                               ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED|sl_next_state.WAIT_END                                                                                                                                                                                               ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED|sl_next_state.TIMEOUT                                                                                                                                                                                                ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED|sl_next_state.IDLE                                                                                                                                                                                                   ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED|sl_next_state.TIMEOUT                                                                                                                                                                                                ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED|sl_next_state.WAIT_END                                                                                                                                                                                               ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED|sl_next_state.TIMEOUT                                                                                                                                                                                                ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED|sl_next_state.WAIT_END                                                                                                                                                                                               ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|E_shift_rot_result[29]                                                                                                                                                                                         ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|command_config[0]                                                                                                      ;
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|d_byteenable[3]                                                                                                                                                                                                ;
; 257:1              ; 3 bits    ; 513 LEs       ; 24 LEs               ; 489 LEs                ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|reg_data_out[29]                                                                                                       ;
; 257:1              ; 10 bits   ; 1710 LEs      ; 20 LEs               ; 1690 LEs               ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|reg_data_out[16]                                                                                                       ;
; 257:1              ; 2 bits    ; 342 LEs       ; 22 LEs               ; 320 LEs                ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|reg_data_out[17]                                                                                                       ;
; 257:1              ; 4 bits    ; 684 LEs       ; 48 LEs               ; 636 LEs                ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|reg_data_out[12]                                                                                                       ;
; 257:1              ; 5 bits    ; 855 LEs       ; 80 LEs               ; 775 LEs                ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|reg_data_out[5]                                                                                                        ;
; 257:1              ; 4 bits    ; 684 LEs       ; 72 LEs               ; 612 LEs                ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|reg_data_out[4]                                                                                                        ;
; 3:1                ; 11 bits   ; 22 LEs        ; 22 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|wrclk_control_slave_threshold_writedata[6]                                                                                                             ;
; 10:1               ; 12 bits   ; 72 LEs        ; 72 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET|sl_int_data[11]                                                                                                                                                                                                                                                      ;
; 5:1                ; 6 bits    ; 18 LEs        ; 12 LEs               ; 6 LEs                  ; Yes        ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE|sl_int_phase_cnt[4]                                                                                                                                                                                                                                                  ;
; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE|Mux5                                                                                                                                                                                                                                                                 ;
; 10:1               ; 2 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; No         ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|Selector4                                                                                                                                                                                                                                                                                           ;
; 10:1               ; 2 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|Selector0                                                                                                                                                                                                                                                                                           ;
; 11:1               ; 2 bits    ; 14 LEs        ; 8 LEs                ; 6 LEs                  ; No         ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|Selector1                                                                                                                                                                                                                                                                                           ;
; 13:1               ; 6 bits    ; 48 LEs        ; 24 LEs               ; 24 LEs                 ; No         ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE|Selector13                                                                                                                                                                                                                                                           ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|d_writedata[25]                                                                                                                                                                                                ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|R_logic_op[0]                                                                                                                                                                                                  ;
; 3:1                ; 17 bits   ; 34 LEs        ; 34 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|E_src1[4]                                                                                                                                                                                                      ;
; 3:1                ; 15 bits   ; 30 LEs        ; 0 LEs                ; 30 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|E_src1[26]                                                                                                                                                                                                     ;
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|E_src2[3]                                                                                                                                                                                                      ;
; 4:1                ; 15 bits   ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|F_pc[4]                                                                                                                                                                                                        ;
; 4:1                ; 11 bits   ; 22 LEs        ; 0 LEs                ; 22 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|E_src2[12]                                                                                                                                                                                                     ;
; 4:1                ; 15 bits   ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|E_src2[17]                                                                                                                                                                                                     ;
; 4:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_alu_result[19]                                                                                                                                                                                               ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|D_dst_regnum[3]                                                                                                                                                                                                ;
; 4:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|E_logic_result[27]                                                                                                                                                                                             ;
; 4:1                ; 30 bits   ; 60 LEs        ; 60 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|W_rf_wr_data[11]                                                                                                                                                                                               ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX|sl_next_state.WAIT_PREAMBLE                                                                                                                                                                                        ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX|sl_next_state.IDLE                                                                                                                                                                                                 ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX|sl_next_state.OVERFLOW                                                                                                                                                                                             ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX|sl_next_state.IDLE                                                                                                                                                                                                 ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX|sl_next_state.RECEIVING                                                                                                                                                                                            ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX|sl_next_state.IDLE                                                                                                                                                                                                 ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX|sl_next_state.OVERFLOW                                                                                                                                                                                             ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX|sl_next_state.WAIT_END                                                                                                                                                                                             ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED|sl_next_state.TIMEOUT                                                                                                                                                                                                ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED|sl_next_state.WAIT_END                                                                                                                                                                                               ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED|sl_next_state.OVERFLOW                                                                                                                                                                                               ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED|sl_next_state.IDLE                                                                                                                                                                                                   ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED|sl_next_state.TIMEOUT                                                                                                                                                                                                ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED|sl_next_state.WAIT_END                                                                                                                                                                                               ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED|sl_next_state.WAIT_PREAMBLE                                                                                                                                                                                          ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED|sl_next_state.IDLE                                                                                                                                                                                                   ;
; 21:1               ; 2 bits    ; 28 LEs        ; 26 LEs               ; 2 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_dpram_din[21]                                                                                                                                                                               ;
; 21:1               ; 4 bits    ; 56 LEs        ; 56 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_dpram_din[9]                                                                                                                                                                                ;
; 22:1               ; 2 bits    ; 28 LEs        ; 28 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_dpram_din[23]                                                                                                                                                                               ;
; 22:1               ; 2 bits    ; 28 LEs        ; 28 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_dpram_din[25]                                                                                                                                                                               ;
; 22:1               ; 5 bits    ; 70 LEs        ; 70 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_dpram_din[31]                                                                                                                                                                               ;
; 22:1               ; 4 bits    ; 56 LEs        ; 56 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_dpram_din[15]                                                                                                                                                                               ;
; 23:1               ; 4 bits    ; 60 LEs        ; 56 LEs               ; 4 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_dpram_din[30]                                                                                                                                                                               ;
; 23:1               ; 2 bits    ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_dpram_din[14]                                                                                                                                                                               ;
; 11:1               ; 3 bits    ; 21 LEs        ; 3 LEs                ; 18 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_frame_cnt[2]                                                                                                                                                                                                                                                                  ;
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_next_L1_fifo_cnt                                                                                                                                                                                                                                                                  ;
; 16:1               ; 2 bits    ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|Mux1                                                                                                                                                                                                                                                                                 ;
; 9:1                ; 16 bits   ; 96 LEs        ; 96 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|x_L1_fifo_rd[10]                                                                                                                                                                                                                                                                     ;
; 19:1               ; 6 bits    ; 72 LEs        ; 48 LEs               ; 24 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_next_state.READ_L1_FIFO                                                                                                                                                                                                                                                           ;
; 21:1               ; 2 bits    ; 28 LEs        ; 14 LEs               ; 14 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_next_state.TRB_TRAILER_WAIT                                                                                                                                                                                                                                                       ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_counter[2]                                                                                                                                                                                                                              ;
; 3:1                ; 14 bits   ; 28 LEs        ; 28 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET|sl_int_data[13]                                                                                                                                                                                                                                                    ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[15]                                                                                                                                                                                                                                 ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|Selector17                                                                                                                                                                                                                                     ;
; 8:1                ; 4 bits    ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|Mux3                                                                                                                                                                                                                                           ;
; 4:1                ; 6 bits    ; 12 LEs        ; 0 LEs                ; 12 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|pending_reads_counter[5]                                                                                                                                                          ;
; 3:1                ; 10 bits   ; 20 LEs        ; 0 LEs                ; 20 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|count[4]                                                                                                                                                         ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_chksum_len[2]                                                                                                                                                                               ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|td_shift[9]                                                                                                                                                      ;
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|td_shift[4]                                                                                                                                                      ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|td_shift[5]                                                                                                                                                      ;
; 5:1                ; 9 bits    ; 27 LEs        ; 18 LEs               ; 9 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_chk_addr[6]                                                                                                                                                                                 ;
; 7:1                ; 7 bits    ; 28 LEs        ; 21 LEs               ; 7 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_len32[2]                                                                                                                                                                                    ;
; 10:1               ; 5 bits    ; 30 LEs        ; 5 LEs                ; 25 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_int_dpram_addr[6]                                                                                                                                                                               ;
; 3:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|sl_next_chk_state                                                                                                                                                                                  ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|sl_int_err_d[0]                                                                                                                                                                                                                                 ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|sl_int_err_d[2]                                                                                                                                                                                                                                 ;
; 3:1                ; 12 bits   ; 24 LEs        ; 0 LEs                ; 24 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_BCR_cnt[4]                                                                                                                                                                                                                                                                    ;
; 4:1                ; 24 bits   ; 48 LEs        ; 0 LEs                ; 48 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_L1A_cnt[1]                                                                                                                                                                                                                                                                    ;
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; Yes        ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET|sl_int_addr[0]                                                                                                                                                                                                                                                     ;
; 5:1                ; 5 bits    ; 15 LEs        ; 10 LEs               ; 5 LEs                  ; Yes        ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET|sl_int_addr[4]                                                                                                                                                                                                                                                       ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[4]                                                                                                                                                                                                                                                        ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[6]                                                                                                                                                                                                                                                        ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET|sl_int_addr[0]                                                                                                                                                                                                                                                        ;
; 12:1               ; 4 bits    ; 32 LEs        ; 28 LEs               ; 4 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_d16[15]                                                                                                                                                                                                                                                       ;
; 13:1               ; 3 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_d16[14]                                                                                                                                                                                                                                                       ;
; 13:1               ; 2 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_d16[5]                                                                                                                                                                                                                                                        ;
; 13:1               ; 2 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|sl_int_d16[1]                                                                                                                                                                                                                                                        ;
; 6:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_next_L1A_state.WAIT_PULSE                                                                                                                                                                                                                                                         ;
; 8:1                ; 3 bits    ; 15 LEs        ; 12 LEs               ; 3 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_next_timeout_state.TIMEOUT                                                                                                                                                                                                                                                        ;
; 15:1               ; 3 bits    ; 30 LEs        ; 9 LEs                ; 21 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Selector20                                                                                                                                                                                                                                      ;
; 15:1               ; 3 bits    ; 30 LEs        ; 9 LEs                ; 21 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Selector36                                                                                                                                                                                                                                      ;
; 17:1               ; 2 bits    ; 22 LEs        ; 6 LEs                ; 16 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Selector21                                                                                                                                                                                                                                      ;
; 17:1               ; 2 bits    ; 22 LEs        ; 6 LEs                ; 16 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Selector31                                                                                                                                                                                                                                      ;
; 17:1               ; 2 bits    ; 22 LEs        ; 8 LEs                ; 14 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Selector18                                                                                                                                                                                                                                      ;
; 17:1               ; 2 bits    ; 22 LEs        ; 8 LEs                ; 14 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Selector34                                                                                                                                                                                                                                      ;
; 44:1               ; 10 bits   ; 290 LEs       ; 100 LEs              ; 190 LEs                ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|Selector14                                                                                                                                                                                                                                                           ;
; 3:1                ; 8 bits    ; 16 LEs        ; 0 LEs                ; 16 LEs                 ; Yes        ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|sl_int_err_cnt_pll_locked[7]                                                                                                                                                                                                                                                                        ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_ff:output_buffer|dffs[2]                                                                                                                          ;
; 4:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFO_CHECK:C_DAQ_FIFO_CHECK|sl_int_timeout[0]                                                                                                                                                                             ;
; 7:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER|Selector12                                                                                                                                                                                                                                                           ;
; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|sl_int_dpar_latch[5]                                                                                                                                                                                                                                                                                                              ;
; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_cmd_process_error[1]                                                                                                                                                                                                                                               ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_sc_counter[1]                                                                                                                                                                                                                                                      ;
; 8:1                ; 4 bits    ; 20 LEs        ; 16 LEs               ; 4 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_cmd_process_error[9]                                                                                                                                                                                                                                               ;
; 7:1                ; 7 bits    ; 28 LEs        ; 7 LEs                ; 21 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|sl_int_frame_cnt[5]                                                                                                                                                                                                                                                       ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_next_state.STORE                                                                                                                                                                                                                                                ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_next_state.ERR                                                                                                                                                                                                                                                  ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_next_state.STORE                                                                                                                                                                                                                                                  ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_next_state.STORE                                                                                                                                                                                                                                                   ;
; 7:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|Selector10                                                                                                                                                                                                                                                                ;
; 9:1                ; 2 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Selector2                                                                                                                                                                                                                                       ;
; 11:1               ; 3 bits    ; 21 LEs        ; 15 LEs               ; 6 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|Selector70                                                                                                                                                                                                                                                                ;
; 11:1               ; 4 bits    ; 28 LEs        ; 16 LEs               ; 12 LEs                 ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|Selector64                                                                                                                                                                                                                                                                ;
; 20:1               ; 7 bits    ; 91 LEs        ; 35 LEs               ; 56 LEs                 ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|Selector49                                                                                                                                                                                                                                                                ;
; 50:1               ; 2 bits    ; 66 LEs        ; 22 LEs               ; 44 LEs                 ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|Selector46                                                                                                                                                                                                                                                                ;
; 50:1               ; 2 bits    ; 66 LEs        ; 18 LEs               ; 48 LEs                 ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER|Selector38                                                                                                                                                                                                                                                                ;
; 3:1                ; 8 bits    ; 16 LEs        ; 0 LEs                ; 16 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|rx_data32[18]                                                                         ;
; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_tx_if:U_MTX|mii_txd_int[3]                                                                                                     ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|byte_empty[1]                                                                         ;
; 4:1                ; 8 bits    ; 16 LEs        ; 0 LEs                ; 16 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|rx_data32[13]                                                                         ;
; 4:1                ; 8 bits    ; 16 LEs        ; 0 LEs                ; 16 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|rx_data32[7]                                                                          ;
; 4:1                ; 10 bits   ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|data[0]                                                                                                         ;
; 7:1                ; 9 bits    ; 36 LEs        ; 9 LEs                ; 27 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_rx_if:U_MRX|mii_rxd_o[5]                                                                                                       ;
; 3:1                ; 31 bits   ; 62 LEs        ; 0 LEs                ; 62 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_ser_data[175]                                                                                                                                                                                                              ;
; 3:1                ; 20 bits   ; 40 LEs        ; 0 LEs                ; 40 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_ser_data[7]                                                                                                                                                                                                                ;
; 3:1                ; 112 bits  ; 224 LEs       ; 0 LEs                ; 224 LEs                ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_ser_data[83]                                                                                                                                                                                                               ;
; 3:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_ser_data[29]                                                                                                                                                                                                               ;
; 4:1                ; 13 bits   ; 26 LEs        ; 0 LEs                ; 26 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_cal_delay_cnt[7]                                                                                                                                                                                                           ;
; 5:1                ; 20 bits   ; 60 LEs        ; 0 LEs                ; 60 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_cal_cnt[14]                                                                                                                                                                                                                ;
; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_ser_data[3]                                                                                                                                                                                                                ;
; 8:1                ; 2 bits    ; 10 LEs        ; 6 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_ser_data[5]                                                                                                                                                                                                                ;
; 9:1                ; 2 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_ser_data[2]                                                                                                                                                                                                                ;
; 12:1               ; 2 bits    ; 16 LEs        ; 6 LEs                ; 10 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_ser_nb[0]                                                                                                                                                                                                                  ;
; 8:1                ; 2 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Mux2                                                                                                                                                                                                                                            ;
; 24:1               ; 3 bits    ; 48 LEs        ; 30 LEs               ; 18 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|Selector224                                                                                                                                                                                                                       ;
; 24:1               ; 2 bits    ; 32 LEs        ; 20 LEs               ; 12 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|Selector230                                                                                                                                                                                                                       ;
; 24:1               ; 2 bits    ; 32 LEs        ; 18 LEs               ; 14 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|Selector237                                                                                                                                                                                                                       ;
; 25:1               ; 2 bits    ; 32 LEs        ; 18 LEs               ; 14 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|Selector234                                                                                                                                                                                                                       ;
; 3:1                ; 31 bits   ; 62 LEs        ; 0 LEs                ; 62 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_ser_data[172]                                                                                                                                                                                                              ;
; 3:1                ; 20 bits   ; 40 LEs        ; 0 LEs                ; 40 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_ser_data[22]                                                                                                                                                                                                               ;
; 3:1                ; 112 bits  ; 224 LEs       ; 0 LEs                ; 224 LEs                ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_ser_data[83]                                                                                                                                                                                                               ;
; 3:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_ser_data[27]                                                                                                                                                                                                               ;
; 4:1                ; 13 bits   ; 26 LEs        ; 0 LEs                ; 26 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_cal_delay_cnt[7]                                                                                                                                                                                                           ;
; 5:1                ; 20 bits   ; 60 LEs        ; 0 LEs                ; 60 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_cal_cnt[14]                                                                                                                                                                                                                ;
; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_ser_data[3]                                                                                                                                                                                                                ;
; 8:1                ; 2 bits    ; 10 LEs        ; 6 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_ser_data[6]                                                                                                                                                                                                                ;
; 9:1                ; 2 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_ser_data[1]                                                                                                                                                                                                                ;
; 12:1               ; 2 bits    ; 16 LEs        ; 6 LEs                ; 10 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_ser_nb[1]                                                                                                                                                                                                                  ;
; 8:1                ; 2 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Mux1                                                                                                                                                                                                                                            ;
; 24:1               ; 3 bits    ; 48 LEs        ; 30 LEs               ; 18 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|Selector225                                                                                                                                                                                                                       ;
; 24:1               ; 2 bits    ; 32 LEs        ; 20 LEs               ; 12 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|Selector230                                                                                                                                                                                                                       ;
; 24:1               ; 2 bits    ; 32 LEs        ; 18 LEs               ; 14 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|Selector237                                                                                                                                                                                                                       ;
; 25:1               ; 2 bits    ; 32 LEs        ; 18 LEs               ; 14 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|Selector234                                                                                                                                                                                                                       ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|eop[2]                                                         ;
; 4:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|rd_13[7]                                                       ;
; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|frm_cnt[0]                                                     ;
; 7:1                ; 8 bits    ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|rd_3[5]                                                        ;
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|pad_cnt[5]                                                     ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|user_length[0]                                                 ;
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|internal_used[4]                                                                           ;
; 8:1                ; 5 bits    ; 25 LEs        ; 15 LEs               ; 10 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block|readdata_d1[16]                                                                                                                                           ;
; 8:1                ; 4 bits    ; 20 LEs        ; 8 LEs                ; 12 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block|readdata_d1[9]                                                                                                                                            ;
; 8:1                ; 4 bits    ; 20 LEs        ; 12 LEs               ; 8 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block|readdata_d1[2]                                                                                                                                            ;
; 6:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block|readdata_d1[5]                                                                                                                                            ;
; 5:1                ; 16 bits   ; 48 LEs        ; 0 LEs                ; 48 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|ff_rx_data_reg[13]                                                                    ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|sw_reset_ff_flush_counter[2]                                                          ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|ff_rx_data[17]                                                                        ;
; 4:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|ff_rx_data[15]                                                                        ;
; 3:1                ; 12 bits   ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|address_counter[9]                                                                                                                                                                ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|write_address[1]                                                                            ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|read_address[2]                                                                             ;
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|internal_used[0]                                                                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block|control[4]                                                                                                                                                ;
; 4:1                ; 12 bits   ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|length_counter[9]                                                                                                                                                                 ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_int_desc_data[8]                                                                                                                                                                       ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_next_state                                                                                                                                                                             ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM|sl_next_state.NIOS_DESC_READ_ADDR                                                                                                                                                         ;
; 6:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFO_CHECK:C_DAQ_FIFO_CHECK|Selector0                                                                                                                                                                                     ;
; 6:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFO_CHECK:C_SC_FIFO_CHECK|Selector2                                                                                                                                                                                      ;
; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DISPATCHER:C_MSGDMA_DISPATCHER|sl_int_state_irq                                                                                                                                                                    ;
; 10:1               ; 4 bits    ; 24 LEs        ; 16 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_CSR_SM:C_MSGDMA_CSR_SM|Selector5                                                                                                                                                                                   ;
; 11:1               ; 4 bits    ; 28 LEs        ; 20 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DISPATCHER:C_MSGDMA_DISPATCHER|sl_int_state_rq                                                                                                                                                                     ;
; 13:1               ; 2 bits    ; 16 LEs        ; 10 LEs               ; 6 LEs                  ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DISPATCHER:C_MSGDMA_DISPATCHER|sl_int_state_rq                                                                                                                                                                     ;
; 14:1               ; 2 bits    ; 18 LEs        ; 8 LEs                ; 10 LEs                 ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|Selector51                                                                                                                                                                                         ;
; 14:1               ; 2 bits    ; 18 LEs        ; 8 LEs                ; 10 LEs                 ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|Selector49                                                                                                                                                                                         ;
; 15:1               ; 2 bits    ; 20 LEs        ; 8 LEs                ; 12 LEs                 ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|Selector42                                                                                                                                                                                         ;
; 16:1               ; 2 bits    ; 20 LEs        ; 8 LEs                ; 12 LEs                 ; No         ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM|Selector57                                                                                                                                                                                         ;
; 3:1                ; 15 bits   ; 30 LEs        ; 0 LEs                ; 30 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio:U_MDIO|reg_data[2]                                                                                                                             ;
; 3:1                ; 9 bits    ; 18 LEs        ; 0 LEs                ; 18 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio:U_MDIO|reg_phy_reg_add[2]                                                                                                                      ;
; 4:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFO_CHECK:C_SC_FIFO_CHECK|sl_int_timeout[13]                                                                                                                                                                             ;
; 5:1                ; 10 bits   ; 30 LEs        ; 0 LEs                ; 30 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_cntl:U_CNTL|mdio_data_out[2]                                                                                                                   ;
; 5:1                ; 5 bits    ; 15 LEs        ; 15 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_cntl:U_CNTL|mdio_data_out[10]                                                                                                                  ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|readdata[3]                                                                                                                                            ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|readdata[2]                                                                                                                                            ;
; 4:1                ; 9 bits    ; 18 LEs        ; 0 LEs                ; 18 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|MonAReg[9]                                                                               ;
; 4:1                ; 22 bits   ; 44 LEs        ; 0 LEs                ; 44 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|MonDReg[23]                                                                              ;
; 4:1                ; 9 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|MonDReg[29]                                                                              ;
; 4:1                ; 32 bits   ; 64 LEs        ; 0 LEs                ; 64 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_break:the_nios2_nios2_cpu_nios2_oci_break|break_readreg[17]                                                                  ;
; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|sr[36] ;
; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|sr[33] ;
; 6:1                ; 13 bits   ; 52 LEs        ; 26 LEs               ; 26 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|sr[4]  ;
; 6:1                ; 16 bits   ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; Yes        ; |FTR_TOP|ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|sr[23] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------+
; Source assignments for Top-level Entity: |FTR_TOP                     ;
+------------------------------+-------+------+-------------------------+
; Assignment                   ; Value ; From ; To                      ;
+------------------------------+-------+------+-------------------------+
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_phase_pll_locked ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_phase_pll_locked ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_main_clk         ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_main_clk         ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_sel_clk          ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_sel_clk          ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_sct_tx_clk[1]    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_sct_tx_clk[1]    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_sct_tx_clk[0]    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_sct_tx_clk[0]    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_sct_rx_clk[1]    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_sct_rx_clk[1]    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_sct_rx_clk[0]    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_sct_rx_clk[0]    ;
+------------------------------+-------+------+-------------------------+


+--------------------------------------------------------------+
; Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER         ;
+------------------------------+-------+------+----------------+
; Assignment                   ; Value ; From ; To             ;
+------------------------------+-------+------+----------------+
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_sel_clk ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_sel_clk ;
+------------------------------+-------+------+----------------+


+--------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i ;
+------------------------------+-------+------+----------------------------------------------------------------------+
; Assignment                   ; Value ; From ; To                                                                   ;
+------------------------------+-------+------+----------------------------------------------------------------------+
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; cntsel_temp[4]                                                       ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; cntsel_temp[4]                                                       ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; cntsel_temp[3]                                                       ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; cntsel_temp[3]                                                       ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; cntsel_temp[2]                                                       ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; cntsel_temp[2]                                                       ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; cntsel_temp[1]                                                       ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; cntsel_temp[1]                                                       ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; cntsel_temp[0]                                                       ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; cntsel_temp[0]                                                       ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gnd                                                                  ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gnd                                                                  ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_write                                                            ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_write                                                            ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[15]                                                    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[15]                                                    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[14]                                                    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[14]                                                    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[13]                                                    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[13]                                                    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[12]                                                    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[12]                                                    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[11]                                                    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[11]                                                    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[10]                                                    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[10]                                                    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[9]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[9]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[8]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[8]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[7]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[7]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[6]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[6]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[5]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[5]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[4]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[4]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[3]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[3]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[2]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[2]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[1]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[1]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[0]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[0]                                                     ;
+------------------------------+-------+------+----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                           ; Value ; From ; To                                                                                                        ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; PHYSICAL_SYNTHESIS_COMBO_LOGIC       ; OFF   ; -    ; -                                                                                                         ;
; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; OFF   ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP  ; OFF   ; -    ; -                                                                                                         ;
; REMOVE_REDUNDANT_LOGIC_CELLS         ; OFF   ; -    ; -                                                                                                         ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                           ; Value ; From ; To                                                                                                        ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; PHYSICAL_SYNTHESIS_COMBO_LOGIC       ; OFF   ; -    ; -                                                                                                         ;
; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; OFF   ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP  ; OFF   ; -    ; -                                                                                                         ;
; REMOVE_REDUNDANT_LOGIC_CELLS         ; OFF   ; -    ; -                                                                                                         ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                           ; Value ; From ; To                                                                                                        ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; PHYSICAL_SYNTHESIS_COMBO_LOGIC       ; OFF   ; -    ; -                                                                                                         ;
; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; OFF   ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP  ; OFF   ; -    ; -                                                                                                         ;
; REMOVE_REDUNDANT_LOGIC_CELLS         ; OFF   ; -    ; -                                                                                                         ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                           ; Value ; From ; To                                                                                                        ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; PHYSICAL_SYNTHESIS_COMBO_LOGIC       ; OFF   ; -    ; -                                                                                                         ;
; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; OFF   ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP  ; OFF   ; -    ; -                                                                                                         ;
; REMOVE_REDUNDANT_LOGIC_CELLS         ; OFF   ; -    ; -                                                                                                         ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                           ; Value ; From ; To                                                                                                        ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; PHYSICAL_SYNTHESIS_COMBO_LOGIC       ; OFF   ; -    ; -                                                                                                         ;
; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; OFF   ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP  ; OFF   ; -    ; -                                                                                                         ;
; REMOVE_REDUNDANT_LOGIC_CELLS         ; OFF   ; -    ; -                                                                                                         ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER ;
+------------------------------+-------+------+--------------------------------------+
; Assignment                   ; Value ; From ; To                                   ;
+------------------------------+-------+------+--------------------------------------+
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_pll_enet_clk                  ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_pll_enet_clk                  ;
+------------------------------+-------+------+--------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                                                   ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                                                    ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated ;
+---------------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                                                                                                                                        ;
+---------------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                                                                                                                                         ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                                                                                                                                         ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                                                                                                                                         ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                                                                                                                                         ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                                                                                                                                                   ;
+---------------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                                                                                                                                           ;
+----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                                                                                                                                                   ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                                                                                                                                      ;
+----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                                                                                                                                           ;
+----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                                                                                                                                                   ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                                                                                                                                      ;
+----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|altsyncram_m8d1:fifo_ram ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                                                                          ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                                                                           ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|dffpipe_3dc:rdaclr ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                                                                                                 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                                                                                                  ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                                                                            ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                                                                                                                                             ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                                                                                                                                             ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                                                                                                                                             ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                                                                                                                                             ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                                                                                                                                             ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                                                                                                                               ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                                                                                                                                ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|dffpipe_3dc:wraclr ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                                                                                                 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                                                                                                  ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                                                                                                 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                                                                                                  ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                                                                                                 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                                                                                                  ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                                                                            ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                                                                                                                                             ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                                                                                                                                             ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                                                                                                                                             ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                                                                                                                                             ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                                                                                                                                             ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                                                                                                                               ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                                                                                                                                ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|altera_std_synchronizer:rdreq_sync_i ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                       ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; dreg[0]                                                                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                  ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                  ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                  ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; din_s1                                                                                                                                                                   ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                   ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                   ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                   ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; dreg[2]                                                                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[2]                                                                                                                                                                  ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[2]                                                                                                                                                                  ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[2]                                                                                                                                                                  ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; dreg[1]                                                                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[1]                                                                                                                                                                  ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[1]                                                                                                                                                                  ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[1]                                                                                                                                                                  ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram|altsyncram:the_altsyncram|altsyncram_g572:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                         ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                          ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_tx_dpram:enet_nios_tx_dpram|altsyncram:the_altsyncram|altsyncram_g572:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                         ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                          ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                                                                  ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                                                                   ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                                                                   ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                                                                    ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated|a_dpfifo_b071:dpfifo|altsyncram_rgn1:FIFOram ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                                                          ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                                                           ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo|scfifo_p871:auto_generated|a_dpfifo_c071:dpfifo|altsyncram_tgn1:FIFOram ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                              ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                               ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                                                                  ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                                                                   ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                                                                   ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                                                                    ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo|altsyncram_3hn1:FIFOram ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                            ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                             ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram|altsyncram:the_altsyncram|altsyncram_dc72:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                  ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_demux:cmd_demux ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                                                                     ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                                                                    ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                                                                  ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                                                                     ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                                                                    ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                                                                  ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_001 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                                                                         ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                                                                        ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                                                                      ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_002 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                                                                         ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                                                                        ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                                                                      ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_003 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                                                                         ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                                                                        ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                                                                      ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_004 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                                                                         ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                                                                        ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                                                                      ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_005 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                                                                         ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                                                                        ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                                                                      ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_006 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                                                                         ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                                                                        ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                                                                      ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_007 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                                                                         ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                                                                        ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                                                                      ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_008 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                                                                         ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                                                                        ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                                                                      ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_009 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                                                                         ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                                                                        ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                                                                      ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_010 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                                                                         ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                                                                        ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                                                                      ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_011 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                                                                         ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                                                                        ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                                                                      ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_012 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                                                                         ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                                                                        ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                                                                      ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_013 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                                                                         ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                                                                        ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                                                                      ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux_014 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                                                                         ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                                                                        ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                                                                      ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ;
+-------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                                                                                                           ;
+-------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[1]                                                                                                                                       ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[0]                                                                                                                                       ;
+-------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                                                                                                               ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[0]                                                                                                                                           ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[1]                                                                                                                                           ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|altsyncram_7pu1:FIFOram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                                 ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                                  ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|altsyncram_7pu1:FIFOram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                                 ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                                  ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_msi1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                          ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                           ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_b_module:nios2_nios2_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_msi1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                          ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                           ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_debug:the_nios2_nios2_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                                                                          ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; dreg[0]                                                                                                                                                                                                                                                     ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                                                                     ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                                                                     ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                                                                     ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; din_s1                                                                                                                                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                                                                      ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_qid1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                                                                                                                                            ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                                                                                                                                             ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; dreg[0]                                                                                                                                                                                                                                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                                                                                                                                                  ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                                                                                                                                                  ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                                                                                                                                                  ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; din_s1                                                                                                                                                                                                                                                                                                                                   ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                                                                                                                                                   ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                                                                                                                                                   ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                                                                                                                                                   ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|altera_std_synchronizer:the_altera_std_synchronizer2 ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; dreg[0]                                                                                                                                                                                                                                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                                                                                                                                                  ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                                                                                                                                                  ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                                                                                                                                                  ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; din_s1                                                                                                                                                                                                                                                                                                                                   ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                                                                                                                                                   ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                                                                                                                                                   ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                                                                                                                                                   ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                                                                                                                                                             ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; dreg[0]                                                                                                                                                                                                                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; din_s1                                                                                                                                                                                                                                                                                                                                         ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                                                                                                                                                         ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                                                                                                                                                         ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                                                                                                                                                         ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                                                                                                                                                             ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; dreg[0]                                                                                                                                                                                                                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; din_s1                                                                                                                                                                                                                                                                                                                                         ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                                                                                                                                                         ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                                                                                                                                                         ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                                                                                                                                                         ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram|altsyncram_pnr1:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                         ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                          ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux:cmd_demux ;
+-----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                       ;
+-----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                      ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                    ;
+-----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux_001:cmd_demux_001 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                               ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                              ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                            ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux ;
+-----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                       ;
+-----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                      ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                    ;
+-----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_001 ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                           ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                          ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                        ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_002 ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                           ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                          ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                        ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux_001:rsp_demux_003 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                               ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                              ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                            ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_004 ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                           ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                          ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                        ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_005 ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                           ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                          ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                        ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_006 ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                           ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                          ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                        ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_007 ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                           ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                          ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                        ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_008 ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                           ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                          ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                        ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux_001:rsp_demux_009 ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                               ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                              ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                            ;
+-----------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_010 ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                           ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                          ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                        ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_011 ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                           ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                          ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                        ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_012 ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                           ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                          ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                        ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux_013 ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                           ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                          ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                        ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_cmd_demux:cmd_demux ;
+-----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                       ;
+-----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                      ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                    ;
+-----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_rsp_demux:rsp_demux ;
+-----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                       ;
+-----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                      ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                    ;
+-----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_rsp_demux:rsp_demux_001 ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                                                                           ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                                                                          ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                                                                        ;
+-----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller ;
+-------------------+-------+------+---------------------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                                      ;
+-------------------+-------+------+---------------------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[4]                                                                  ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[3]                                                                  ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[2]                                                                  ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[1]                                                                  ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[0]                                                                  ;
+-------------------+-------+------+---------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                                                                                 ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[1]                                                                                                             ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[0]                                                                                                             ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                                                                                     ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[0]                                                                                                                 ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[1]                                                                                                                 ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001 ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                                          ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[4]                                                                      ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[3]                                                                      ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[2]                                                                      ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[1]                                                                      ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[0]                                                                      ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                                                                                     ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[1]                                                                                                                 ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[0]                                                                                                                 ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;
+-------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                                                                                         ;
+-------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[0]                                                                                                                     ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[1]                                                                                                                     ;
+-------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002 ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                                          ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[4]                                                                      ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[3]                                                                      ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[2]                                                                      ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[1]                                                                      ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[0]                                                                      ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1 ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                                                                                     ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[1]                                                                                                                 ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[0]                                                                                                                 ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;
+-------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                                                                                         ;
+-------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[0]                                                                                                                     ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[1]                                                                                                                     ;
+-------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+---------------------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                                          ;
+-------------------------+-------------+------+---------------------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                                           ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                               ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                               ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                                         ;
+-------------------------+-------------+------+---------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                                      ;
+-----------------------------+---------+------+-------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                                       ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                                       ;
+-----------------------------+---------+------+-------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                          ;
+---------------------------------+-------+------+-------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                           ;
+---------------------------------+-------+------+-------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                               ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                          ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|a_graycounter_cg6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                  ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                          ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                             ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|a_graycounter_8ub:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                  ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                          ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                             ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|altsyncram_cia1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                 ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                  ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                        ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                         ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                        ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                         ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                   ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                    ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                    ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                    ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                    ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                      ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                       ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                        ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                         ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                        ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                         ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                   ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                    ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                    ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                    ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                    ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                      ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                       ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component|scfifo_7l91:auto_generated|a_dpfifo_er91:dpfifo|altsyncram_sqs1:FIFOram ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                     ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                      ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+---------------------+
; Assignment                      ; Value ; From ; To                  ;
+---------------------------------+-------+------+---------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                   ;
+---------------------------------+-------+------+---------------------+


+-------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated ;
+---------------------------------------+-------+------+------------------------------------------+
; Assignment                            ; Value ; From ; To                                       ;
+---------------------------------------+-------+------+------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                        ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                        ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                        ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                        ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                  ;
+---------------------------------------+-------+------+------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_uv6:rdptr_g1p ;
+----------------+-------+------+---------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                          ;
+----------------+-------+------+---------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                  ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                     ;
+----------------+-------+------+---------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_qdc:wrptr_g1p ;
+----------------+-------+------+---------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                          ;
+----------------+-------+------+---------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                  ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                     ;
+----------------+-------+------+---------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram ;
+---------------------------------+--------------------+------+------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                         ;
+---------------------------------+--------------------+------+------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                          ;
+---------------------------------+--------------------+------+------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:rs_brp ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                 ;
+---------------------------------+-------+------+-------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:rs_bwp ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                 ;
+---------------------------------+-------+------+-------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp ;
+-----------------------------+------------------------+------+--------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                           ;
+-----------------------------+------------------------+------+--------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                            ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                            ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                            ;
+-----------------------------+------------------------+------+--------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15 ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:ws_brp ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                 ;
+---------------------------------+-------+------+-------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:ws_bwp ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                 ;
+---------------------------------+-------+------+-------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp ;
+-----------------------------+------------------------+------+--------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                           ;
+-----------------------------+------------------------+------+--------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                            ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                            ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                            ;
+-----------------------------+------------------------+------+--------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18 ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------+
; Source assignments for FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET ;
+-------------------+-------+------+-------------------------------------------------+
; Assignment        ; Value ; From ; To                                              ;
+-------------------+-------+------+-------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][14]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][13]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][12]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][11]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][10]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][9]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][8]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][7]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][6]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][5]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][4]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][3]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][2]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][1]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][0]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][14]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][13]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][12]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][11]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][10]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][9]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][8]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][7]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][6]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][5]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][4]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][3]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][2]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][1]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][0]                                ;
+-------------------+-------+------+-------------------------------------------------+


+-------------------------------------------------------------------------------------+
; Source assignments for FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET ;
+-------------------+-------+------+--------------------------------------------------+
; Assignment        ; Value ; From ; To                                               ;
+-------------------+-------+------+--------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][0]                                 ;
+-------------------+-------+------+--------------------------------------------------+


+---------------------------------------------------------------------------------------+
; Source assignments for FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET ;
+-------------------+-------+------+----------------------------------------------------+
; Assignment        ; Value ; From ; To                                                 ;
+-------------------+-------+------+----------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][13]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][12]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][13]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][12]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][13]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][12]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][0]                                   ;
+-------------------+-------+------+----------------------------------------------------+


+---------------------------------------------------------------------------------------+
; Source assignments for FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET ;
+-------------------+-------+------+----------------------------------------------------+
; Assignment        ; Value ; From ; To                                                 ;
+-------------------+-------+------+----------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][11]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][10]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][9]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][8]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][7]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][6]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][5]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][4]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][3]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][2]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][1]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][0]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][11]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][10]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][9]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][8]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][7]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][6]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][5]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][4]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][3]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][2]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][1]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][0]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][11]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][10]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][9]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][8]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][7]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][6]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][5]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][4]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][3]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][2]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][1]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][0]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][11]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][10]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][9]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][8]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][7]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][6]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][5]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][4]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][3]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][2]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][1]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][0]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][11]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][10]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][9]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][8]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][7]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][6]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][5]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][4]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][3]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][2]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][1]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][0]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][0]                                   ;
+-------------------+-------+------+----------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                 ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                  ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                  ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                            ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                       ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                        ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                       ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                        ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                 ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                  ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                  ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                            ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                       ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                        ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                       ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                        ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                 ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                  ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                  ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                            ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                       ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                        ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                       ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                        ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                 ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                  ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                  ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                            ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                       ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                        ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                       ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                        ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                 ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                  ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                  ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                            ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                       ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                        ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                       ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                        ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                 ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                  ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                  ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                            ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                       ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                        ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                       ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                        ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                 ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                  ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                  ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                            ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                       ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                        ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                       ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                        ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                 ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                  ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                  ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                            ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                       ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                        ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                       ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                        ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                   ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                    ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                    ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                              ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                         ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                          ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                         ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                          ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                   ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                    ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                    ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                              ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                         ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                          ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                         ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                          ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                   ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                    ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                    ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                              ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                         ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                          ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                         ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                          ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                   ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                    ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                    ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                              ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                         ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                          ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                         ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                          ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                   ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                    ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                    ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                              ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                         ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                          ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                         ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                          ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                   ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                    ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                    ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                              ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                         ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                          ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                         ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                          ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                   ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                    ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                    ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                              ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                         ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                          ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                         ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                          ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                   ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                    ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                    ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                              ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                         ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                          ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                         ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                          ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo|altsyncram:mem_rtl_0|altsyncram_23n1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                                                                                                        ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                                                                                                         ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i ;
+--------------------------------------+------------------------+-------------------------------------------------------------------------------+
; Parameter Name                       ; Value                  ; Type                                                                          ;
+--------------------------------------+------------------------+-------------------------------------------------------------------------------+
; reference_clock_frequency            ; 40.0 MHz               ; String                                                                        ;
; fractional_vco_multiplier            ; false                  ; String                                                                        ;
; pll_type                             ; General                ; String                                                                        ;
; pll_subtype                          ; General                ; String                                                                        ;
; number_of_clocks                     ; 2                      ; Signed Integer                                                                ;
; operation_mode                       ; direct                 ; String                                                                        ;
; deserialization_factor               ; 4                      ; Signed Integer                                                                ;
; data_rate                            ; 0                      ; Signed Integer                                                                ;
; sim_additional_refclk_cycles_to_lock ; 0                      ; Signed Integer                                                                ;
; output_clock_frequency0              ; 40.000000 MHz          ; String                                                                        ;
; phase_shift0                         ; 0 ps                   ; String                                                                        ;
; duty_cycle0                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency1              ; 32.000000 MHz          ; String                                                                        ;
; phase_shift1                         ; 0 ps                   ; String                                                                        ;
; duty_cycle1                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency2              ; 0 MHz                  ; String                                                                        ;
; phase_shift2                         ; 0 ps                   ; String                                                                        ;
; duty_cycle2                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency3              ; 0 MHz                  ; String                                                                        ;
; phase_shift3                         ; 0 ps                   ; String                                                                        ;
; duty_cycle3                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency4              ; 0 MHz                  ; String                                                                        ;
; phase_shift4                         ; 0 ps                   ; String                                                                        ;
; duty_cycle4                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency5              ; 0 MHz                  ; String                                                                        ;
; phase_shift5                         ; 0 ps                   ; String                                                                        ;
; duty_cycle5                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency6              ; 0 MHz                  ; String                                                                        ;
; phase_shift6                         ; 0 ps                   ; String                                                                        ;
; duty_cycle6                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency7              ; 0 MHz                  ; String                                                                        ;
; phase_shift7                         ; 0 ps                   ; String                                                                        ;
; duty_cycle7                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency8              ; 0 MHz                  ; String                                                                        ;
; phase_shift8                         ; 0 ps                   ; String                                                                        ;
; duty_cycle8                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency9              ; 0 MHz                  ; String                                                                        ;
; phase_shift9                         ; 0 ps                   ; String                                                                        ;
; duty_cycle9                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency10             ; 0 MHz                  ; String                                                                        ;
; phase_shift10                        ; 0 ps                   ; String                                                                        ;
; duty_cycle10                         ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency11             ; 0 MHz                  ; String                                                                        ;
; phase_shift11                        ; 0 ps                   ; String                                                                        ;
; duty_cycle11                         ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency12             ; 0 MHz                  ; String                                                                        ;
; phase_shift12                        ; 0 ps                   ; String                                                                        ;
; duty_cycle12                         ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency13             ; 0 MHz                  ; String                                                                        ;
; phase_shift13                        ; 0 ps                   ; String                                                                        ;
; duty_cycle13                         ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency14             ; 0 MHz                  ; String                                                                        ;
; phase_shift14                        ; 0 ps                   ; String                                                                        ;
; duty_cycle14                         ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency15             ; 0 MHz                  ; String                                                                        ;
; phase_shift15                        ; 0 ps                   ; String                                                                        ;
; duty_cycle15                         ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency16             ; 0 MHz                  ; String                                                                        ;
; phase_shift16                        ; 0 ps                   ; String                                                                        ;
; duty_cycle16                         ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency17             ; 0 MHz                  ; String                                                                        ;
; phase_shift17                        ; 0 ps                   ; String                                                                        ;
; duty_cycle17                         ; 50                     ; Signed Integer                                                                ;
; clock_name_0                         ;                        ; String                                                                        ;
; clock_name_1                         ;                        ; String                                                                        ;
; clock_name_2                         ;                        ; String                                                                        ;
; clock_name_3                         ;                        ; String                                                                        ;
; clock_name_4                         ;                        ; String                                                                        ;
; clock_name_5                         ;                        ; String                                                                        ;
; clock_name_6                         ;                        ; String                                                                        ;
; clock_name_7                         ;                        ; String                                                                        ;
; clock_name_8                         ;                        ; String                                                                        ;
; clock_name_global_0                  ; false                  ; String                                                                        ;
; clock_name_global_1                  ; false                  ; String                                                                        ;
; clock_name_global_2                  ; false                  ; String                                                                        ;
; clock_name_global_3                  ; false                  ; String                                                                        ;
; clock_name_global_4                  ; false                  ; String                                                                        ;
; clock_name_global_5                  ; false                  ; String                                                                        ;
; clock_name_global_6                  ; false                  ; String                                                                        ;
; clock_name_global_7                  ; false                  ; String                                                                        ;
; clock_name_global_8                  ; false                  ; String                                                                        ;
; m_cnt_hi_div                         ; 1                      ; Signed Integer                                                                ;
; m_cnt_lo_div                         ; 1                      ; Signed Integer                                                                ;
; m_cnt_bypass_en                      ; false                  ; String                                                                        ;
; m_cnt_odd_div_duty_en                ; false                  ; String                                                                        ;
; n_cnt_hi_div                         ; 1                      ; Signed Integer                                                                ;
; n_cnt_lo_div                         ; 1                      ; Signed Integer                                                                ;
; n_cnt_bypass_en                      ; false                  ; String                                                                        ;
; n_cnt_odd_div_duty_en                ; false                  ; String                                                                        ;
; c_cnt_hi_div0                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div0                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en0                     ; false                  ; String                                                                        ;
; c_cnt_in_src0                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en0               ; false                  ; String                                                                        ;
; c_cnt_prst0                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst0                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div1                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div1                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en1                     ; false                  ; String                                                                        ;
; c_cnt_in_src1                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en1               ; false                  ; String                                                                        ;
; c_cnt_prst1                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst1                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div2                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div2                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en2                     ; false                  ; String                                                                        ;
; c_cnt_in_src2                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en2               ; false                  ; String                                                                        ;
; c_cnt_prst2                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst2                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div3                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div3                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en3                     ; false                  ; String                                                                        ;
; c_cnt_in_src3                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en3               ; false                  ; String                                                                        ;
; c_cnt_prst3                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst3                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div4                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div4                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en4                     ; false                  ; String                                                                        ;
; c_cnt_in_src4                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en4               ; false                  ; String                                                                        ;
; c_cnt_prst4                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst4                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div5                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div5                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en5                     ; false                  ; String                                                                        ;
; c_cnt_in_src5                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en5               ; false                  ; String                                                                        ;
; c_cnt_prst5                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst5                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div6                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div6                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en6                     ; false                  ; String                                                                        ;
; c_cnt_in_src6                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en6               ; false                  ; String                                                                        ;
; c_cnt_prst6                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst6                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div7                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div7                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en7                     ; false                  ; String                                                                        ;
; c_cnt_in_src7                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en7               ; false                  ; String                                                                        ;
; c_cnt_prst7                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst7                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div8                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div8                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en8                     ; false                  ; String                                                                        ;
; c_cnt_in_src8                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en8               ; false                  ; String                                                                        ;
; c_cnt_prst8                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst8                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div9                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div9                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en9                     ; false                  ; String                                                                        ;
; c_cnt_in_src9                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en9               ; false                  ; String                                                                        ;
; c_cnt_prst9                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst9                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div10                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div10                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en10                    ; false                  ; String                                                                        ;
; c_cnt_in_src10                       ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en10              ; false                  ; String                                                                        ;
; c_cnt_prst10                         ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst10                  ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div11                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div11                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en11                    ; false                  ; String                                                                        ;
; c_cnt_in_src11                       ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en11              ; false                  ; String                                                                        ;
; c_cnt_prst11                         ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst11                  ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div12                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div12                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en12                    ; false                  ; String                                                                        ;
; c_cnt_in_src12                       ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en12              ; false                  ; String                                                                        ;
; c_cnt_prst12                         ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst12                  ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div13                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div13                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en13                    ; false                  ; String                                                                        ;
; c_cnt_in_src13                       ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en13              ; false                  ; String                                                                        ;
; c_cnt_prst13                         ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst13                  ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div14                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div14                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en14                    ; false                  ; String                                                                        ;
; c_cnt_in_src14                       ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en14              ; false                  ; String                                                                        ;
; c_cnt_prst14                         ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst14                  ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div15                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div15                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en15                    ; false                  ; String                                                                        ;
; c_cnt_in_src15                       ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en15              ; false                  ; String                                                                        ;
; c_cnt_prst15                         ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst15                  ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div16                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div16                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en16                    ; false                  ; String                                                                        ;
; c_cnt_in_src16                       ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en16              ; false                  ; String                                                                        ;
; c_cnt_prst16                         ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst16                  ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div17                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div17                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en17                    ; false                  ; String                                                                        ;
; c_cnt_in_src17                       ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en17              ; false                  ; String                                                                        ;
; c_cnt_prst17                         ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst17                  ; 0                      ; Signed Integer                                                                ;
; pll_vco_div                          ; 1                      ; Signed Integer                                                                ;
; pll_slf_rst                          ; false                  ; String                                                                        ;
; pll_bw_sel                           ; low                    ; String                                                                        ;
; pll_output_clk_frequency             ; 0 MHz                  ; String                                                                        ;
; pll_cp_current                       ; 0                      ; Signed Integer                                                                ;
; pll_bwctrl                           ; 0                      ; Signed Integer                                                                ;
; pll_fractional_division              ; 1                      ; Signed Integer                                                                ;
; pll_fractional_cout                  ; 24                     ; Signed Integer                                                                ;
; pll_dsm_out_sel                      ; 1st_order              ; String                                                                        ;
; mimic_fbclk_type                     ; gclk                   ; String                                                                        ;
; pll_fbclk_mux_1                      ; glb                    ; String                                                                        ;
; pll_fbclk_mux_2                      ; fb_1                   ; String                                                                        ;
; pll_m_cnt_in_src                     ; ph_mux_clk             ; String                                                                        ;
; pll_vcoph_div                        ; 1                      ; Signed Integer                                                                ;
; refclk1_frequency                    ; 0 MHz                  ; String                                                                        ;
; pll_clkin_0_src                      ; clk_0                  ; String                                                                        ;
; pll_clkin_1_src                      ; clk_0                  ; String                                                                        ;
; pll_clk_loss_sw_en                   ; false                  ; String                                                                        ;
; pll_auto_clk_sw_en                   ; false                  ; String                                                                        ;
; pll_manu_clk_sw_en                   ; false                  ; String                                                                        ;
; pll_clk_sw_dly                       ; 0                      ; Signed Integer                                                                ;
; pll_extclk_0_cnt_src                 ; pll_extclk_cnt_src_vss ; String                                                                        ;
; pll_extclk_1_cnt_src                 ; pll_extclk_cnt_src_vss ; String                                                                        ;
+--------------------------------------+------------------------+-------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i ;
+--------------------------------------+------------------------+--------------------------------------------------------------------------+
; Parameter Name                       ; Value                  ; Type                                                                     ;
+--------------------------------------+------------------------+--------------------------------------------------------------------------+
; reference_clock_frequency            ; 40.0 MHz               ; String                                                                   ;
; fractional_vco_multiplier            ; false                  ; String                                                                   ;
; pll_type                             ; Cyclone V              ; String                                                                   ;
; pll_subtype                          ; DPS                    ; String                                                                   ;
; number_of_clocks                     ; 5                      ; Signed Integer                                                           ;
; operation_mode                       ; source synchronous     ; String                                                                   ;
; deserialization_factor               ; 4                      ; Signed Integer                                                           ;
; data_rate                            ; 0                      ; Signed Integer                                                           ;
; sim_additional_refclk_cycles_to_lock ; 0                      ; Signed Integer                                                           ;
; output_clock_frequency0              ; 40.000000 MHz          ; String                                                                   ;
; phase_shift0                         ; 0 ps                   ; String                                                                   ;
; duty_cycle0                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency1              ; 40.000000 MHz          ; String                                                                   ;
; phase_shift1                         ; 0 ps                   ; String                                                                   ;
; duty_cycle1                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency2              ; 40.000000 MHz          ; String                                                                   ;
; phase_shift2                         ; 0 ps                   ; String                                                                   ;
; duty_cycle2                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency3              ; 40.000000 MHz          ; String                                                                   ;
; phase_shift3                         ; 0 ps                   ; String                                                                   ;
; duty_cycle3                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency4              ; 40.000000 MHz          ; String                                                                   ;
; phase_shift4                         ; 0 ps                   ; String                                                                   ;
; duty_cycle4                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency5              ; 0 MHz                  ; String                                                                   ;
; phase_shift5                         ; 0 ps                   ; String                                                                   ;
; duty_cycle5                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency6              ; 0 MHz                  ; String                                                                   ;
; phase_shift6                         ; 0 ps                   ; String                                                                   ;
; duty_cycle6                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency7              ; 0 MHz                  ; String                                                                   ;
; phase_shift7                         ; 0 ps                   ; String                                                                   ;
; duty_cycle7                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency8              ; 0 MHz                  ; String                                                                   ;
; phase_shift8                         ; 0 ps                   ; String                                                                   ;
; duty_cycle8                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency9              ; 0 MHz                  ; String                                                                   ;
; phase_shift9                         ; 0 ps                   ; String                                                                   ;
; duty_cycle9                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency10             ; 0 MHz                  ; String                                                                   ;
; phase_shift10                        ; 0 ps                   ; String                                                                   ;
; duty_cycle10                         ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency11             ; 0 MHz                  ; String                                                                   ;
; phase_shift11                        ; 0 ps                   ; String                                                                   ;
; duty_cycle11                         ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency12             ; 0 MHz                  ; String                                                                   ;
; phase_shift12                        ; 0 ps                   ; String                                                                   ;
; duty_cycle12                         ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency13             ; 0 MHz                  ; String                                                                   ;
; phase_shift13                        ; 0 ps                   ; String                                                                   ;
; duty_cycle13                         ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency14             ; 0 MHz                  ; String                                                                   ;
; phase_shift14                        ; 0 ps                   ; String                                                                   ;
; duty_cycle14                         ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency15             ; 0 MHz                  ; String                                                                   ;
; phase_shift15                        ; 0 ps                   ; String                                                                   ;
; duty_cycle15                         ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency16             ; 0 MHz                  ; String                                                                   ;
; phase_shift16                        ; 0 ps                   ; String                                                                   ;
; duty_cycle16                         ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency17             ; 0 MHz                  ; String                                                                   ;
; phase_shift17                        ; 0 ps                   ; String                                                                   ;
; duty_cycle17                         ; 50                     ; Signed Integer                                                           ;
; clock_name_0                         ;                        ; String                                                                   ;
; clock_name_1                         ;                        ; String                                                                   ;
; clock_name_2                         ;                        ; String                                                                   ;
; clock_name_3                         ;                        ; String                                                                   ;
; clock_name_4                         ;                        ; String                                                                   ;
; clock_name_5                         ;                        ; String                                                                   ;
; clock_name_6                         ;                        ; String                                                                   ;
; clock_name_7                         ;                        ; String                                                                   ;
; clock_name_8                         ;                        ; String                                                                   ;
; clock_name_global_0                  ; false                  ; String                                                                   ;
; clock_name_global_1                  ; false                  ; String                                                                   ;
; clock_name_global_2                  ; false                  ; String                                                                   ;
; clock_name_global_3                  ; false                  ; String                                                                   ;
; clock_name_global_4                  ; false                  ; String                                                                   ;
; clock_name_global_5                  ; false                  ; String                                                                   ;
; clock_name_global_6                  ; false                  ; String                                                                   ;
; clock_name_global_7                  ; false                  ; String                                                                   ;
; clock_name_global_8                  ; false                  ; String                                                                   ;
; m_cnt_hi_div                         ; 4                      ; Signed Integer                                                           ;
; m_cnt_lo_div                         ; 4                      ; Signed Integer                                                           ;
; m_cnt_bypass_en                      ; false                  ; String                                                                   ;
; m_cnt_odd_div_duty_en                ; false                  ; String                                                                   ;
; n_cnt_hi_div                         ; 256                    ; Signed Integer                                                           ;
; n_cnt_lo_div                         ; 256                    ; Signed Integer                                                           ;
; n_cnt_bypass_en                      ; true                   ; String                                                                   ;
; n_cnt_odd_div_duty_en                ; false                  ; String                                                                   ;
; c_cnt_hi_div0                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_lo_div0                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_bypass_en0                     ; false                  ; String                                                                   ;
; c_cnt_in_src0                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en0               ; false                  ; String                                                                   ;
; c_cnt_prst0                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst0                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div1                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_lo_div1                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_bypass_en1                     ; false                  ; String                                                                   ;
; c_cnt_in_src1                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en1               ; false                  ; String                                                                   ;
; c_cnt_prst1                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst1                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div2                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_lo_div2                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_bypass_en2                     ; false                  ; String                                                                   ;
; c_cnt_in_src2                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en2               ; false                  ; String                                                                   ;
; c_cnt_prst2                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst2                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div3                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_lo_div3                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_bypass_en3                     ; false                  ; String                                                                   ;
; c_cnt_in_src3                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en3               ; false                  ; String                                                                   ;
; c_cnt_prst3                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst3                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div4                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_lo_div4                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_bypass_en4                     ; false                  ; String                                                                   ;
; c_cnt_in_src4                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en4               ; false                  ; String                                                                   ;
; c_cnt_prst4                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst4                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div5                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div5                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en5                     ; true                   ; String                                                                   ;
; c_cnt_in_src5                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en5               ; false                  ; String                                                                   ;
; c_cnt_prst5                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst5                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div6                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div6                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en6                     ; true                   ; String                                                                   ;
; c_cnt_in_src6                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en6               ; false                  ; String                                                                   ;
; c_cnt_prst6                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst6                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div7                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div7                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en7                     ; true                   ; String                                                                   ;
; c_cnt_in_src7                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en7               ; false                  ; String                                                                   ;
; c_cnt_prst7                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst7                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div8                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div8                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en8                     ; true                   ; String                                                                   ;
; c_cnt_in_src8                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en8               ; false                  ; String                                                                   ;
; c_cnt_prst8                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst8                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div9                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div9                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en9                     ; true                   ; String                                                                   ;
; c_cnt_in_src9                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en9               ; false                  ; String                                                                   ;
; c_cnt_prst9                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst9                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div10                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div10                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en10                    ; true                   ; String                                                                   ;
; c_cnt_in_src10                       ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en10              ; false                  ; String                                                                   ;
; c_cnt_prst10                         ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst10                  ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div11                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div11                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en11                    ; true                   ; String                                                                   ;
; c_cnt_in_src11                       ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en11              ; false                  ; String                                                                   ;
; c_cnt_prst11                         ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst11                  ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div12                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div12                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en12                    ; true                   ; String                                                                   ;
; c_cnt_in_src12                       ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en12              ; false                  ; String                                                                   ;
; c_cnt_prst12                         ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst12                  ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div13                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div13                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en13                    ; true                   ; String                                                                   ;
; c_cnt_in_src13                       ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en13              ; false                  ; String                                                                   ;
; c_cnt_prst13                         ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst13                  ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div14                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div14                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en14                    ; true                   ; String                                                                   ;
; c_cnt_in_src14                       ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en14              ; false                  ; String                                                                   ;
; c_cnt_prst14                         ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst14                  ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div15                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div15                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en15                    ; true                   ; String                                                                   ;
; c_cnt_in_src15                       ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en15              ; false                  ; String                                                                   ;
; c_cnt_prst15                         ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst15                  ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div16                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div16                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en16                    ; true                   ; String                                                                   ;
; c_cnt_in_src16                       ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en16              ; false                  ; String                                                                   ;
; c_cnt_prst16                         ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst16                  ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div17                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div17                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en17                    ; true                   ; String                                                                   ;
; c_cnt_in_src17                       ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en17              ; false                  ; String                                                                   ;
; c_cnt_prst17                         ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst17                  ; 0                      ; Signed Integer                                                           ;
; pll_vco_div                          ; 2                      ; Signed Integer                                                           ;
; pll_slf_rst                          ; false                  ; String                                                                   ;
; pll_bw_sel                           ; low                    ; String                                                                   ;
; pll_output_clk_frequency             ; 320.0 MHz              ; String                                                                   ;
; pll_cp_current                       ; 20                     ; Signed Integer                                                           ;
; pll_bwctrl                           ; 4000                   ; Signed Integer                                                           ;
; pll_fractional_division              ; 1                      ; String                                                                   ;
; pll_fractional_cout                  ; 32                     ; Signed Integer                                                           ;
; pll_dsm_out_sel                      ; 1st_order              ; String                                                                   ;
; mimic_fbclk_type                     ; gclk                   ; String                                                                   ;
; pll_fbclk_mux_1                      ; glb                    ; String                                                                   ;
; pll_fbclk_mux_2                      ; fb_1                   ; String                                                                   ;
; pll_m_cnt_in_src                     ; ph_mux_clk             ; String                                                                   ;
; pll_vcoph_div                        ; 1                      ; Signed Integer                                                           ;
; refclk1_frequency                    ; 0 MHz                  ; String                                                                   ;
; pll_clkin_0_src                      ; clk_0                  ; String                                                                   ;
; pll_clkin_1_src                      ; clk_0                  ; String                                                                   ;
; pll_clk_loss_sw_en                   ; false                  ; String                                                                   ;
; pll_auto_clk_sw_en                   ; false                  ; String                                                                   ;
; pll_manu_clk_sw_en                   ; false                  ; String                                                                   ;
; pll_clk_sw_dly                       ; 0                      ; Signed Integer                                                           ;
; pll_extclk_0_cnt_src                 ; pll_extclk_cnt_src_vss ; String                                                                   ;
; pll_extclk_1_cnt_src                 ; pll_extclk_cnt_src_vss ; String                                                                   ;
+--------------------------------------+------------------------+--------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE ;
+----------------+-------+----------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                             ;
+----------------+-------+----------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                       ;
+----------------+-------+----------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER ;
+-----------------------------+------------------+-------------------------------+
; Parameter Name              ; Value            ; Type                          ;
+-----------------------------+------------------+-------------------------------+
; x_reset_active              ; '0'              ; Enumerated                    ;
; x_nb_config_word16          ; 1                ; Signed Integer                ;
; x_nb_config_word16_size     ; 1                ; Signed Integer                ;
; x_nb_dpram_size             ; 1                ; Signed Integer                ;
; x_nb_devices_size           ; 0                ; Signed Integer                ;
; x_daq_timeout               ; 0001001110000111 ; Unsigned Binary               ;
; x_daq_fifo_xfer_level       ; 300              ; Signed Integer                ;
; x_daq_fifo_depth_size       ; 16               ; Signed Integer                ;
; x_timeout_prescaler_ms_size ; 16               ; Signed Integer                ;
; x_timeout_prescaler_ms_nb   ; 39998            ; Signed Integer                ;
; x_timeout_ms_size           ; 10               ; Signed Integer                ;
; x_timeout_ms                ; 500              ; Signed Integer                ;
+-----------------------------+------------------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER ;
+-----------------------+------------------+---------------------------------------------------------------+
; Parameter Name        ; Value            ; Type                                                          ;
+-----------------------+------------------+---------------------------------------------------------------+
; x_reset_active        ; '0'              ; Enumerated                                                    ;
; x_sc_timeout          ; 0000001111100111 ; Unsigned Binary                                               ;
; x_sc_fifo_xfer_level  ; 50               ; Signed Integer                                                ;
; x_sc_fifo_depth_size  ; 7                ; Signed Integer                                                ;
; x_daq_timeout         ; 0001001110000111 ; Unsigned Binary                                               ;
; x_daq_fifo_xfer_level ; 300              ; Signed Integer                                                ;
; x_daq_fifo_depth_size ; 16               ; Signed Integer                                                ;
+-----------------------+------------------+---------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                                                                                                                                                ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                                                                                                                                             ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                                                                                                                                          ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                                                                                                                                        ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                                                                                                                                        ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                                                                                                                                      ;
; LPM_WIDTH               ; 32          ; Signed Integer                                                                                                                                                                                                                                      ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                                                                                                                                      ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                                                                                                                                      ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                                                                                                                                             ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                                                                                                                                             ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                                                                                                                                             ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                                                                                                                                             ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                                                                                                                                             ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                                                                                                                                             ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                                                                                                                                             ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                                                                                                                                             ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                                                                                                                                      ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                                                                                                                                      ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                                                                                                                                             ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                                                                                                                                             ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                                                                                                                                             ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                                                                                                                                             ;
; WRITE_ACLR_SYNCH        ; ON          ; Untyped                                                                                                                                                                                                                                             ;
; READ_ACLR_SYNCH         ; ON          ; Untyped                                                                                                                                                                                                                                             ;
; CBXI_PARAMETER          ; dcfifo_iq62 ; Untyped                                                                                                                                                                                                                                             ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|altera_std_synchronizer:rdreq_sync_i ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 4     ; Signed Integer                                                                                                                                                                                                                      ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+-------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                                                                ;
+------------------------------------+----------------------+-------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                                                             ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                                                          ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                                                        ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                                                        ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                                                      ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                                                             ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT      ; Untyped                                                                                                                             ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                                                                                      ;
; WIDTHAD_A                          ; 9                    ; Signed Integer                                                                                                                      ;
; NUMWORDS_A                         ; 512                  ; Signed Integer                                                                                                                      ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                                                             ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                                                             ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                             ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                                                             ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                                                             ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                             ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                                                                                      ;
; WIDTHAD_B                          ; 9                    ; Signed Integer                                                                                                                      ;
; NUMWORDS_B                         ; 512                  ; Signed Integer                                                                                                                      ;
; INDATA_REG_B                       ; CLOCK0               ; Untyped                                                                                                                             ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK0               ; Untyped                                                                                                                             ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                                                                             ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                                                                             ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                                                                             ;
; BYTEENA_REG_B                      ; CLOCK0               ; Untyped                                                                                                                             ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                                                             ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                             ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                                                             ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                             ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                             ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                             ;
; WIDTH_BYTEENA_A                    ; 4                    ; Signed Integer                                                                                                                      ;
; WIDTH_BYTEENA_B                    ; 4                    ; Signed Integer                                                                                                                      ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                                                             ;
; BYTE_SIZE                          ; 8                    ; Signed Integer                                                                                                                      ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                                                                                             ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                             ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                             ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                                                                                             ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                                                             ;
; MAXIMUM_DEPTH                      ; 512                  ; Signed Integer                                                                                                                      ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                                                             ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                                                             ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                                                             ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                                                             ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                             ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                             ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                                                             ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                                                                                                             ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                                                                             ;
; DEVICE_FAMILY                      ; Cyclone V            ; Untyped                                                                                                                             ;
; CBXI_PARAMETER                     ; altsyncram_g572      ; Untyped                                                                                                                             ;
+------------------------------------+----------------------+-------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_tx_dpram:enet_nios_tx_dpram|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+-------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                                                                ;
+------------------------------------+----------------------+-------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                                                             ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                                                          ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                                                        ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                                                        ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                                                      ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                                                             ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT      ; Untyped                                                                                                                             ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                                                                                      ;
; WIDTHAD_A                          ; 9                    ; Signed Integer                                                                                                                      ;
; NUMWORDS_A                         ; 512                  ; Signed Integer                                                                                                                      ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                                                             ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                                                             ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                             ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                                                             ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                                                             ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                             ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                                                                                      ;
; WIDTHAD_B                          ; 9                    ; Signed Integer                                                                                                                      ;
; NUMWORDS_B                         ; 512                  ; Signed Integer                                                                                                                      ;
; INDATA_REG_B                       ; CLOCK0               ; Untyped                                                                                                                             ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK0               ; Untyped                                                                                                                             ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                                                                             ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                                                                             ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                                                                             ;
; BYTEENA_REG_B                      ; CLOCK0               ; Untyped                                                                                                                             ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                                                             ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                             ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                                                             ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                             ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                             ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                             ;
; WIDTH_BYTEENA_A                    ; 4                    ; Signed Integer                                                                                                                      ;
; WIDTH_BYTEENA_B                    ; 4                    ; Signed Integer                                                                                                                      ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                                                             ;
; BYTE_SIZE                          ; 8                    ; Signed Integer                                                                                                                      ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                                                                                             ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                             ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                             ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                                                                                             ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                                                             ;
; MAXIMUM_DEPTH                      ; 512                  ; Signed Integer                                                                                                                      ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                                                             ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                                                             ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                                                             ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                                                             ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                             ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                             ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                                                             ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                                                                                                             ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                                                                             ;
; DEVICE_FAMILY                      ; Cyclone V            ; Untyped                                                                                                                             ;
; CBXI_PARAMETER                     ; altsyncram_g572      ; Untyped                                                                                                                             ;
+------------------------------------+----------------------+-------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal ;
+-----------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name              ; Value ; Type                                                                                                                                                   ;
+-----------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; MODE                        ; 2     ; Signed Integer                                                                                                                                         ;
; RESPONSE_PORT               ; 0     ; Signed Integer                                                                                                                                         ;
; DESCRIPTOR_FIFO_DEPTH       ; 16    ; Signed Integer                                                                                                                                         ;
; ENHANCED_FEATURES           ; 0     ; Signed Integer                                                                                                                                         ;
; DESCRIPTOR_WIDTH            ; 128   ; Signed Integer                                                                                                                                         ;
; DESCRIPTOR_BYTEENABLE_WIDTH ; 16    ; Signed Integer                                                                                                                                         ;
; CSR_ADDRESS_WIDTH           ; 3     ; Signed Integer                                                                                                                                         ;
; DESCRIPTOR_INTERFACE        ; 0     ; Signed Integer                                                                                                                                         ;
+-----------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers ;
+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                                                                                                       ;
+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MODE              ; 2     ; Signed Integer                                                                                                                                                                                             ;
; DATA_WIDTH        ; 128   ; Signed Integer                                                                                                                                                                                             ;
; BYTE_ENABLE_WIDTH ; 16    ; Signed Integer                                                                                                                                                                                             ;
; FIFO_DEPTH        ; 16    ; Signed Integer                                                                                                                                                                                             ;
; FIFO_DEPTH_LOG2   ; 4     ; Signed Integer                                                                                                                                                                                             ;
+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|write_signal_breakout:the_write_signal_breakout ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                          ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DATA_WIDTH     ; 128   ; Signed Integer                                                                                                                                                                                                                                                ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|read_signal_breakout:the_read_signal_breakout ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DATA_WIDTH     ; 128   ; Signed Integer                                                                                                                                                                                                                                              ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO ;
+-----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                                     ;
+-----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DATA_WIDTH      ; 128   ; Signed Integer                                                                                                                                                                                                                                           ;
; FIFO_DEPTH      ; 16    ; Signed Integer                                                                                                                                                                                                                                           ;
; FIFO_DEPTH_LOG2 ; 4     ; Signed Integer                                                                                                                                                                                                                                           ;
; LATENCY         ; 2     ; Signed Integer                                                                                                                                                                                                                                           ;
+-----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                                                                                                                                                                         ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                                                                                                                                                                      ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                                                                                                                                                                   ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                                                                                                                                                                 ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                                                                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                                                                                                                                                               ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                                                                                                                                                                      ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                                                                                                                                                                                      ;
; WIDTH_A                            ; 128                  ; Signed Integer                                                                                                                                                                                                                               ;
; WIDTHAD_A                          ; 4                    ; Signed Integer                                                                                                                                                                                                                               ;
; NUMWORDS_A                         ; 16                   ; Signed Integer                                                                                                                                                                                                                               ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                                                                      ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; WIDTH_B                            ; 128                  ; Signed Integer                                                                                                                                                                                                                               ;
; WIDTHAD_B                          ; 4                    ; Signed Integer                                                                                                                                                                                                                               ;
; NUMWORDS_B                         ; 16                   ; Signed Integer                                                                                                                                                                                                                               ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                                                                                                                                                                                      ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                                                                                                                                                                                      ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                                                                                                                                                                                      ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                                                                                                                                                                                      ;
; OUTDATA_REG_B                      ; CLOCK0               ; Untyped                                                                                                                                                                                                                                      ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                                                                      ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; WIDTH_BYTEENA_A                    ; 16                   ; Signed Integer                                                                                                                                                                                                                               ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                                                                                                                                                                                      ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                                                                                                                                                                      ;
; BYTE_SIZE                          ; 8                    ; Signed Integer                                                                                                                                                                                                                               ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                                                                                                                                                                                                      ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                                                                      ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                                                                      ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                                                                                                                                                                                                      ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                                                                                                                                                                      ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                                                                                                                                                                                                                      ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                                                                                                                                                                      ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                                                                                                                                                                      ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                                                                                                                                                                      ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                                                                                                                                                                      ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                                                                      ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                                                                      ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                                                                                                                                                                      ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                                                                                                                                                                                                                      ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                                                                                                                                                                                      ;
; DEVICE_FAMILY                      ; Cyclone V            ; Untyped                                                                                                                                                                                                                                      ;
; CBXI_PARAMETER                     ; altsyncram_p5j1      ; Untyped                                                                                                                                                                                                                                      ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                                      ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DATA_WIDTH      ; 128   ; Signed Integer                                                                                                                                                                                                                                            ;
; FIFO_DEPTH      ; 16    ; Signed Integer                                                                                                                                                                                                                                            ;
; FIFO_DEPTH_LOG2 ; 4     ; Signed Integer                                                                                                                                                                                                                                            ;
; LATENCY         ; 2     ; Signed Integer                                                                                                                                                                                                                                            ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram ;
+------------------------------------+----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                                                                                                                                                                          ;
+------------------------------------+----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                                                                                                                                                                       ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                                                                                                                                                                    ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                                                                                                                                                                  ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                                                                                                                                                                  ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                                                                                                                                                                ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                                                                                                                                                                       ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                                                                                                                                                                                       ;
; WIDTH_A                            ; 128                  ; Signed Integer                                                                                                                                                                                                                                ;
; WIDTHAD_A                          ; 4                    ; Signed Integer                                                                                                                                                                                                                                ;
; NUMWORDS_A                         ; 16                   ; Signed Integer                                                                                                                                                                                                                                ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                                                                       ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; WIDTH_B                            ; 128                  ; Signed Integer                                                                                                                                                                                                                                ;
; WIDTHAD_B                          ; 4                    ; Signed Integer                                                                                                                                                                                                                                ;
; NUMWORDS_B                         ; 16                   ; Signed Integer                                                                                                                                                                                                                                ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                                                                                                                                                                                       ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                                                                                                                                                                                       ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                                                                                                                                                                                       ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                                                                                                                                                                                       ;
; OUTDATA_REG_B                      ; CLOCK0               ; Untyped                                                                                                                                                                                                                                       ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                                                                       ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; WIDTH_BYTEENA_A                    ; 16                   ; Signed Integer                                                                                                                                                                                                                                ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                                                                                                                                                                                       ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                                                                                                                                                                       ;
; BYTE_SIZE                          ; 8                    ; Signed Integer                                                                                                                                                                                                                                ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                                                                                                                                                                                                       ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                                                                       ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                                                                       ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                                                                                                                                                                                                       ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                                                                                                                                                                       ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                                                                                                                                                                                                                       ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                                                                                                                                                                       ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                                                                                                                                                                       ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                                                                                                                                                                       ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                                                                                                                                                                       ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                                                                       ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                                                                       ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                                                                                                                                                                       ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                                                                                                                                                                                                                       ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                                                                                                                                                                                       ;
; DEVICE_FAMILY                      ; Cyclone V            ; Untyped                                                                                                                                                                                                                                       ;
; CBXI_PARAMETER                     ; altsyncram_p5j1      ; Untyped                                                                                                                                                                                                                                       ;
+------------------------------------+----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                        ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDRESS_WIDTH  ; 3     ; Signed Integer                                                                                                                                                                              ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block ;
+-----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                 ;
+-----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; RESPONSE_PORT   ; 0     ; Signed Integer                                                                                                                                                                                       ;
; FIFO_DEPTH      ; 32    ; Signed Integer                                                                                                                                                                                       ;
; FIFO_DEPTH_LOG2 ; 5     ; Signed Integer                                                                                                                                                                                       ;
+-----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                                                                                                            ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                                                                                                      ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                                                                                                    ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                                                                                                    ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                                                                                                  ;
; lpm_width               ; 41          ; Signed Integer                                                                                                                                                                                                  ;
; LPM_NUMWORDS            ; 32          ; Signed Integer                                                                                                                                                                                                  ;
; LPM_WIDTHU              ; 5           ; Signed Integer                                                                                                                                                                                                  ;
; LPM_SHOWAHEAD           ; ON          ; Untyped                                                                                                                                                                                                         ;
; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                                                                                                                                                                         ;
; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                                                                                                                                                                         ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                                                                                                                                                         ;
; ADD_RAM_OUTPUT_REGISTER ; ON          ; Untyped                                                                                                                                                                                                         ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                                                                                                                                                                         ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                                                                                                                                                         ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                                                                                                         ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                                                                                                         ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                                                                                                         ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                                                                                                         ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                                                                                                                                                                         ;
; CBXI_PARAMETER          ; scfifo_o871 ; Untyped                                                                                                                                                                                                         ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal ;
+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                  ;
+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; UNALIGNED_ACCESSES_ENABLE      ; 0     ; Signed Integer                                                                                                                                        ;
; ONLY_FULL_ACCESS_ENABLE        ; 0     ; Signed Integer                                                                                                                                        ;
; STRIDE_ENABLE                  ; 0     ; Signed Integer                                                                                                                                        ;
; STRIDE_WIDTH                   ; 1     ; Signed Integer                                                                                                                                        ;
; PACKET_ENABLE                  ; 1     ; Signed Integer                                                                                                                                        ;
; ERROR_ENABLE                   ; 1     ; Signed Integer                                                                                                                                        ;
; ERROR_WIDTH                    ; 6     ; Signed Integer                                                                                                                                        ;
; DATA_WIDTH                     ; 32    ; Signed Integer                                                                                                                                        ;
; BYTE_ENABLE_WIDTH              ; 4     ; Signed Integer                                                                                                                                        ;
; BYTE_ENABLE_WIDTH_LOG2         ; 2     ; Signed Integer                                                                                                                                        ;
; ADDRESS_WIDTH                  ; 11    ; Signed Integer                                                                                                                                        ;
; LENGTH_WIDTH                   ; 12    ; Signed Integer                                                                                                                                        ;
; ACTUAL_BYTES_TRANSFERRED_WIDTH ; 13    ; Signed Integer                                                                                                                                        ;
; FIFO_DEPTH                     ; 32    ; Signed Integer                                                                                                                                        ;
; FIFO_DEPTH_LOG2                ; 5     ; Signed Integer                                                                                                                                        ;
; FIFO_SPEED_OPTIMIZATION        ; 1     ; Signed Integer                                                                                                                                        ;
; SYMBOL_WIDTH                   ; 8     ; Signed Integer                                                                                                                                        ;
; NUMBER_OF_SYMBOLS              ; 4     ; Signed Integer                                                                                                                                        ;
; NUMBER_OF_SYMBOLS_LOG2         ; 2     ; Signed Integer                                                                                                                                        ;
; BURST_ENABLE                   ; 0     ; Signed Integer                                                                                                                                        ;
; MAX_BURST_COUNT                ; 1     ; Signed Integer                                                                                                                                        ;
; MAX_BURST_COUNT_WIDTH          ; 1     ; Signed Integer                                                                                                                                        ;
; PROGRAMMABLE_BURST_ENABLE      ; 0     ; Signed Integer                                                                                                                                        ;
; BURST_WRAPPING_SUPPORT         ; 0     ; Signed Integer                                                                                                                                        ;
+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo ;
+-------------------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                                                                                ;
+-------------------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                                                                          ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                                                                        ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                                                                        ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                                                                      ;
; lpm_width               ; 42          ; Signed Integer                                                                                                                                                                      ;
; LPM_NUMWORDS            ; 32          ; Signed Integer                                                                                                                                                                      ;
; LPM_WIDTHU              ; 5           ; Signed Integer                                                                                                                                                                      ;
; LPM_SHOWAHEAD           ; ON          ; Untyped                                                                                                                                                                             ;
; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                                                                                                                                             ;
; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                                                                                                                                             ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                                                                                                                             ;
; ADD_RAM_OUTPUT_REGISTER ; ON          ; Untyped                                                                                                                                                                             ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                                                                                                                                             ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                                                                                                                             ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                                                                             ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                                                                             ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                                                                             ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                                                                             ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                                                                                                                                             ;
; CBXI_PARAMETER          ; scfifo_p871 ; Untyped                                                                                                                                                                             ;
+-------------------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|ST_to_MM_Adapter:the_ST_to_MM_Adapter ;
+-------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value ; Type                                                                                                                                                                                               ;
+-------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DATA_WIDTH              ; 32    ; Signed Integer                                                                                                                                                                                     ;
; BYTEENABLE_WIDTH_LOG2   ; 2     ; Signed Integer                                                                                                                                                                                     ;
; ADDRESS_WIDTH           ; 11    ; Signed Integer                                                                                                                                                                                     ;
; UNALIGNED_ACCESS_ENABLE ; 0     ; Signed Integer                                                                                                                                                                                     ;
+-------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|byte_enable_generator:the_byte_enable_generator ;
+------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name   ; Value ; Type                                                                                                                                                                                                                ;
+------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTEENABLE_WIDTH ; 4     ; Signed Integer                                                                                                                                                                                                      ;
+------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|write_burst_control:the_write_burst_control ;
+------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value ; Type                                                                                                                                                                                                      ;
+------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BURST_ENABLE           ; 0     ; Signed Integer                                                                                                                                                                                            ;
; BURST_COUNT_WIDTH      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; WORD_SIZE              ; 4     ; Signed Integer                                                                                                                                                                                            ;
; WORD_SIZE_LOG2         ; 2     ; Signed Integer                                                                                                                                                                                            ;
; ADDRESS_WIDTH          ; 11    ; Signed Integer                                                                                                                                                                                            ;
; LENGTH_WIDTH           ; 12    ; Signed Integer                                                                                                                                                                                            ;
; WRITE_FIFO_USED_WIDTH  ; 5     ; Signed Integer                                                                                                                                                                                            ;
; BURST_WRAPPING_SUPPORT ; 0     ; Signed Integer                                                                                                                                                                                            ;
+------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal ;
+-----------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name              ; Value ; Type                                                                                                                                                   ;
+-----------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; MODE                        ; 1     ; Signed Integer                                                                                                                                         ;
; RESPONSE_PORT               ; 2     ; Signed Integer                                                                                                                                         ;
; DESCRIPTOR_FIFO_DEPTH       ; 16    ; Signed Integer                                                                                                                                         ;
; ENHANCED_FEATURES           ; 0     ; Signed Integer                                                                                                                                         ;
; DESCRIPTOR_WIDTH            ; 128   ; Signed Integer                                                                                                                                         ;
; DESCRIPTOR_BYTEENABLE_WIDTH ; 16    ; Signed Integer                                                                                                                                         ;
; CSR_ADDRESS_WIDTH           ; 3     ; Signed Integer                                                                                                                                         ;
; DESCRIPTOR_INTERFACE        ; 0     ; Signed Integer                                                                                                                                         ;
+-----------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers ;
+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                                                                                                       ;
+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; MODE              ; 1     ; Signed Integer                                                                                                                                                                                             ;
; DATA_WIDTH        ; 128   ; Signed Integer                                                                                                                                                                                             ;
; BYTE_ENABLE_WIDTH ; 16    ; Signed Integer                                                                                                                                                                                             ;
; FIFO_DEPTH        ; 16    ; Signed Integer                                                                                                                                                                                             ;
; FIFO_DEPTH_LOG2   ; 4     ; Signed Integer                                                                                                                                                                                             ;
+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|write_signal_breakout:the_write_signal_breakout ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                          ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DATA_WIDTH     ; 128   ; Signed Integer                                                                                                                                                                                                                                                ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|read_signal_breakout:the_read_signal_breakout ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DATA_WIDTH     ; 128   ; Signed Integer                                                                                                                                                                                                                                              ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO ;
+-----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                                     ;
+-----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DATA_WIDTH      ; 128   ; Signed Integer                                                                                                                                                                                                                                           ;
; FIFO_DEPTH      ; 16    ; Signed Integer                                                                                                                                                                                                                                           ;
; FIFO_DEPTH_LOG2 ; 4     ; Signed Integer                                                                                                                                                                                                                                           ;
; LATENCY         ; 2     ; Signed Integer                                                                                                                                                                                                                                           ;
+-----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                                                                                                                                                                         ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                                                                                                                                                                      ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                                                                                                                                                                   ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                                                                                                                                                                 ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                                                                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                                                                                                                                                               ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                                                                                                                                                                      ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                                                                                                                                                                                      ;
; WIDTH_A                            ; 128                  ; Signed Integer                                                                                                                                                                                                                               ;
; WIDTHAD_A                          ; 4                    ; Signed Integer                                                                                                                                                                                                                               ;
; NUMWORDS_A                         ; 16                   ; Signed Integer                                                                                                                                                                                                                               ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                                                                      ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; WIDTH_B                            ; 128                  ; Signed Integer                                                                                                                                                                                                                               ;
; WIDTHAD_B                          ; 4                    ; Signed Integer                                                                                                                                                                                                                               ;
; NUMWORDS_B                         ; 16                   ; Signed Integer                                                                                                                                                                                                                               ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                                                                                                                                                                                      ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                                                                                                                                                                                      ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                                                                                                                                                                                      ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                                                                                                                                                                                      ;
; OUTDATA_REG_B                      ; CLOCK0               ; Untyped                                                                                                                                                                                                                                      ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                                                                      ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                      ;
; WIDTH_BYTEENA_A                    ; 16                   ; Signed Integer                                                                                                                                                                                                                               ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                                                                                                                                                                                      ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                                                                                                                                                                      ;
; BYTE_SIZE                          ; 8                    ; Signed Integer                                                                                                                                                                                                                               ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                                                                                                                                                                                                      ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                                                                      ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                                                                      ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                                                                                                                                                                                                      ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                                                                                                                                                                      ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                                                                                                                                                                                                                      ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                                                                                                                                                                      ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                                                                                                                                                                      ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                                                                                                                                                                      ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                                                                                                                                                                      ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                                                                      ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                                                                      ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                                                                                                                                                                      ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                                                                                                                                                                                                                      ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                                                                                                                                                                                      ;
; DEVICE_FAMILY                      ; Cyclone V            ; Untyped                                                                                                                                                                                                                                      ;
; CBXI_PARAMETER                     ; altsyncram_p5j1      ; Untyped                                                                                                                                                                                                                                      ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                                      ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DATA_WIDTH      ; 128   ; Signed Integer                                                                                                                                                                                                                                            ;
; FIFO_DEPTH      ; 16    ; Signed Integer                                                                                                                                                                                                                                            ;
; FIFO_DEPTH_LOG2 ; 4     ; Signed Integer                                                                                                                                                                                                                                            ;
; LATENCY         ; 2     ; Signed Integer                                                                                                                                                                                                                                            ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram ;
+------------------------------------+----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                                                                                                                                                                          ;
+------------------------------------+----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                                                                                                                                                                       ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                                                                                                                                                                    ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                                                                                                                                                                  ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                                                                                                                                                                  ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                                                                                                                                                                ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                                                                                                                                                                       ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                                                                                                                                                                                       ;
; WIDTH_A                            ; 128                  ; Signed Integer                                                                                                                                                                                                                                ;
; WIDTHAD_A                          ; 4                    ; Signed Integer                                                                                                                                                                                                                                ;
; NUMWORDS_A                         ; 16                   ; Signed Integer                                                                                                                                                                                                                                ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                                                                       ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; WIDTH_B                            ; 128                  ; Signed Integer                                                                                                                                                                                                                                ;
; WIDTHAD_B                          ; 4                    ; Signed Integer                                                                                                                                                                                                                                ;
; NUMWORDS_B                         ; 16                   ; Signed Integer                                                                                                                                                                                                                                ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                                                                                                                                                                                       ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                                                                                                                                                                                       ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                                                                                                                                                                                       ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                                                                                                                                                                                       ;
; OUTDATA_REG_B                      ; CLOCK0               ; Untyped                                                                                                                                                                                                                                       ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                                                                       ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                       ;
; WIDTH_BYTEENA_A                    ; 16                   ; Signed Integer                                                                                                                                                                                                                                ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                                                                                                                                                                                       ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                                                                                                                                                                       ;
; BYTE_SIZE                          ; 8                    ; Signed Integer                                                                                                                                                                                                                                ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                                                                                                                                                                                                       ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                                                                       ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                                                                       ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                                                                                                                                                                                                       ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                                                                                                                                                                       ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                                                                                                                                                                                                                       ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                                                                                                                                                                       ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                                                                                                                                                                       ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                                                                                                                                                                       ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                                                                                                                                                                       ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                                                                       ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                                                                       ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                                                                                                                                                                       ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                                                                                                                                                                                                                       ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                                                                                                                                                                                       ;
; DEVICE_FAMILY                      ; Cyclone V            ; Untyped                                                                                                                                                                                                                                       ;
; CBXI_PARAMETER                     ; altsyncram_p5j1      ; Untyped                                                                                                                                                                                                                                       ;
+------------------------------------+----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                        ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDRESS_WIDTH  ; 3     ; Signed Integer                                                                                                                                                                              ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block ;
+-----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                 ;
+-----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; RESPONSE_PORT   ; 2     ; Signed Integer                                                                                                                                                                                       ;
; FIFO_DEPTH      ; 32    ; Signed Integer                                                                                                                                                                                       ;
; FIFO_DEPTH_LOG2 ; 5     ; Signed Integer                                                                                                                                                                                       ;
+-----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                     ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; UNALIGNED_ACCESSES_ENABLE ; 0     ; Signed Integer                                                                                                                                           ;
; ONLY_FULL_ACCESS_ENABLE   ; 0     ; Signed Integer                                                                                                                                           ;
; STRIDE_ENABLE             ; 0     ; Signed Integer                                                                                                                                           ;
; STRIDE_WIDTH              ; 1     ; Signed Integer                                                                                                                                           ;
; PACKET_ENABLE             ; 1     ; Signed Integer                                                                                                                                           ;
; ERROR_ENABLE              ; 1     ; Signed Integer                                                                                                                                           ;
; ERROR_WIDTH               ; 1     ; Signed Integer                                                                                                                                           ;
; CHANNEL_ENABLE            ; 0     ; Signed Integer                                                                                                                                           ;
; CHANNEL_WIDTH             ; 8     ; Signed Integer                                                                                                                                           ;
; DATA_WIDTH                ; 32    ; Signed Integer                                                                                                                                           ;
; BYTE_ENABLE_WIDTH         ; 4     ; Signed Integer                                                                                                                                           ;
; BYTE_ENABLE_WIDTH_LOG2    ; 2     ; Signed Integer                                                                                                                                           ;
; ADDRESS_WIDTH             ; 14    ; Signed Integer                                                                                                                                           ;
; LENGTH_WIDTH              ; 12    ; Signed Integer                                                                                                                                           ;
; FIFO_DEPTH                ; 32    ; Signed Integer                                                                                                                                           ;
; FIFO_DEPTH_LOG2           ; 5     ; Signed Integer                                                                                                                                           ;
; FIFO_SPEED_OPTIMIZATION   ; 1     ; Signed Integer                                                                                                                                           ;
; SYMBOL_WIDTH              ; 8     ; Signed Integer                                                                                                                                           ;
; NUMBER_OF_SYMBOLS         ; 4     ; Signed Integer                                                                                                                                           ;
; NUMBER_OF_SYMBOLS_LOG2    ; 2     ; Signed Integer                                                                                                                                           ;
; BURST_ENABLE              ; 0     ; Signed Integer                                                                                                                                           ;
; MAX_BURST_COUNT           ; 1     ; Signed Integer                                                                                                                                           ;
; MAX_BURST_COUNT_WIDTH     ; 1     ; Signed Integer                                                                                                                                           ;
; PROGRAMMABLE_BURST_ENABLE ; 0     ; Signed Integer                                                                                                                                           ;
; BURST_WRAPPING_SUPPORT    ; 0     ; Signed Integer                                                                                                                                           ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|MM_to_ST_Adapter:the_MM_to_ST_adapter ;
+-------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value ; Type                                                                                                                                                                                             ;
+-------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DATA_WIDTH              ; 32    ; Signed Integer                                                                                                                                                                                   ;
; LENGTH_WIDTH            ; 12    ; Signed Integer                                                                                                                                                                                   ;
; ADDRESS_WIDTH           ; 14    ; Signed Integer                                                                                                                                                                                   ;
; BYTE_ADDRESS_WIDTH      ; 2     ; Signed Integer                                                                                                                                                                                   ;
; READS_PENDING_WIDTH     ; 6     ; Signed Integer                                                                                                                                                                                   ;
; EMPTY_WIDTH             ; 2     ; Signed Integer                                                                                                                                                                                   ;
; PACKET_SUPPORT          ; 1     ; Signed Integer                                                                                                                                                                                   ;
; UNALIGNED_ACCESS_ENABLE ; 0     ; Signed Integer                                                                                                                                                                                   ;
; FULL_WORD_ACCESS_ONLY   ; 0     ; Signed Integer                                                                                                                                                                                   ;
+-------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                                                                              ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                                                                        ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                                                                      ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                                                                      ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                                                                    ;
; lpm_width               ; 45          ; Signed Integer                                                                                                                                                                    ;
; LPM_NUMWORDS            ; 32          ; Signed Integer                                                                                                                                                                    ;
; LPM_WIDTHU              ; 5           ; Signed Integer                                                                                                                                                                    ;
; LPM_SHOWAHEAD           ; ON          ; Untyped                                                                                                                                                                           ;
; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                                                                                                                                           ;
; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                                                                                                                                           ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                                                                                                                           ;
; ADD_RAM_OUTPUT_REGISTER ; ON          ; Untyped                                                                                                                                                                           ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                                                                                                                                           ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                                                                                                                           ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                                                                           ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                                                                           ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                                                                           ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                                                                           ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                                                                                                                                           ;
; CBXI_PARAMETER          ; scfifo_s871 ; Untyped                                                                                                                                                                           ;
+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|read_burst_control:the_read_burst_control ;
+------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value ; Type                                                                                                                                                                                                  ;
+------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BURST_ENABLE           ; 0     ; Signed Integer                                                                                                                                                                                        ;
; BURST_COUNT_WIDTH      ; 1     ; Signed Integer                                                                                                                                                                                        ;
; WORD_SIZE_LOG2         ; 2     ; Signed Integer                                                                                                                                                                                        ;
; ADDRESS_WIDTH          ; 14    ; Signed Integer                                                                                                                                                                                        ;
; LENGTH_WIDTH           ; 12    ; Signed Integer                                                                                                                                                                                        ;
; BURST_WRAPPING_SUPPORT ; 0     ; Signed Integer                                                                                                                                                                                        ;
+------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+-----------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                                                        ;
+------------------------------------+----------------------+-----------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                                                     ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                                                  ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                                                ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                                                ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                                              ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                                                     ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT      ; Untyped                                                                                                                     ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                                                                              ;
; WIDTHAD_A                          ; 10                   ; Signed Integer                                                                                                              ;
; NUMWORDS_A                         ; 1024                 ; Signed Integer                                                                                                              ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                                                     ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                                                     ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                     ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                                                     ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                                                     ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                     ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                                                                              ;
; WIDTHAD_B                          ; 10                   ; Signed Integer                                                                                                              ;
; NUMWORDS_B                         ; 1024                 ; Signed Integer                                                                                                              ;
; INDATA_REG_B                       ; CLOCK0               ; Untyped                                                                                                                     ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK0               ; Untyped                                                                                                                     ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                                                                     ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                                                                     ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                                                                     ;
; BYTEENA_REG_B                      ; CLOCK0               ; Untyped                                                                                                                     ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                                                     ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                     ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                                                     ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                     ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                     ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                     ;
; WIDTH_BYTEENA_A                    ; 4                    ; Signed Integer                                                                                                              ;
; WIDTH_BYTEENA_B                    ; 4                    ; Signed Integer                                                                                                              ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                                                     ;
; BYTE_SIZE                          ; 8                    ; Signed Integer                                                                                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                                                                                     ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                     ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                     ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                                                                                     ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                                                     ;
; MAXIMUM_DEPTH                      ; 1024                 ; Signed Integer                                                                                                              ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                                                     ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                                                     ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                                                     ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                                                     ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                     ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                     ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                                                     ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                                                                                                     ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                                                                     ;
; DEVICE_FAMILY                      ; Cyclone V            ; Untyped                                                                                                                     ;
; CBXI_PARAMETER                     ; altsyncram_dc72      ; Untyped                                                                                                                     ;
+------------------------------------+----------------------+-----------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_avalon_mm_bridge:if_bridge ;
+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                                                      ;
+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; DATA_WIDTH        ; 32    ; Signed Integer                                                                                                                                            ;
; SYMBOL_WIDTH      ; 8     ; Signed Integer                                                                                                                                            ;
; RESPONSE_WIDTH    ; 2     ; Signed Integer                                                                                                                                            ;
; HDL_ADDR_WIDTH    ; 8     ; Signed Integer                                                                                                                                            ;
; BURSTCOUNT_WIDTH  ; 1     ; Signed Integer                                                                                                                                            ;
; PIPELINE_COMMAND  ; 0     ; Signed Integer                                                                                                                                            ;
; PIPELINE_RESPONSE ; 0     ; Signed Integer                                                                                                                                            ;
; BYTEEN_WIDTH      ; 4     ; Signed Integer                                                                                                                                            ;
+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:if_bridge_m0_translator ;
+-----------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name              ; Value ; Type                                                                                                                                                                                                                      ;
+-----------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                ; 8     ; Signed Integer                                                                                                                                                                                                            ;
; AV_DATA_W                   ; 32    ; Signed Integer                                                                                                                                                                                                            ;
; AV_BURSTCOUNT_W             ; 1     ; Signed Integer                                                                                                                                                                                                            ;
; AV_BYTEENABLE_W             ; 4     ; Signed Integer                                                                                                                                                                                                            ;
; UAV_ADDRESS_W               ; 8     ; Signed Integer                                                                                                                                                                                                            ;
; UAV_BURSTCOUNT_W            ; 3     ; Signed Integer                                                                                                                                                                                                            ;
; USE_BURSTCOUNT              ; 1     ; Signed Integer                                                                                                                                                                                                            ;
; USE_BEGINBURSTTRANSFER      ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; USE_BEGINTRANSFER           ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; USE_CHIPSELECT              ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; USE_READ                    ; 1     ; Signed Integer                                                                                                                                                                                                            ;
; USE_READDATAVALID           ; 1     ; Signed Integer                                                                                                                                                                                                            ;
; USE_WRITE                   ; 1     ; Signed Integer                                                                                                                                                                                                            ;
; USE_WAITREQUEST             ; 1     ; Signed Integer                                                                                                                                                                                                            ;
; USE_WRITERESPONSE           ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; USE_READRESPONSE            ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; AV_REGISTERINCOMINGSIGNALS  ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; AV_SYMBOLS_PER_WORD         ; 4     ; Signed Integer                                                                                                                                                                                                            ;
; AV_ADDRESS_SYMBOLS          ; 1     ; Signed Integer                                                                                                                                                                                                            ;
; AV_CONSTANT_BURST_BEHAVIOR  ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; UAV_CONSTANT_BURST_BEHAVIOR ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; AV_BURSTCOUNT_SYMBOLS       ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; AV_LINEWRAPBURSTS           ; 0     ; Signed Integer                                                                                                                                                                                                            ;
+-----------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_s1_translator ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                                                       ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                                                             ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                                             ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                                             ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                                                             ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                                             ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                                             ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                                             ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                                             ;
; UAV_ADDRESS_W                  ; 8     ; Signed Integer                                                                                                                                                                                                             ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                                             ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                                             ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                                             ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_s1_translator ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                                                       ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                                                             ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                                             ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                                             ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                                                             ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                                             ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                                             ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                                             ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                                             ;
; UAV_ADDRESS_W                  ; 8     ; Signed Integer                                                                                                                                                                                                             ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                                             ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                                             ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                                             ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_s1_translator ;
+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                                                    ;
+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                                                          ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                                          ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                                          ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                                                          ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                                          ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                                          ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                                          ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                                          ;
; UAV_ADDRESS_W                  ; 8     ; Signed Integer                                                                                                                                                                                                          ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                                          ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                                          ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                                          ;
+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_ip_addr_s1_translator ;
+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                                                         ;
+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                                                               ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                                               ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                                               ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                                                               ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                                               ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                                               ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                                               ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                                               ;
; UAV_ADDRESS_W                  ; 8     ; Signed Integer                                                                                                                                                                                                               ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                                               ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                                               ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                                               ;
+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_ip_addr_s1_translator ;
+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                                                        ;
+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                                                              ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                                              ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                                              ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                                                              ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                                              ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                                              ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                                              ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                              ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                              ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                                              ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                                              ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                                                              ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                                              ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                                              ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                                              ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                                              ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                                              ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                                              ;
; UAV_ADDRESS_W                  ; 8     ; Signed Integer                                                                                                                                                                                                              ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                                              ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                                              ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                                              ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                                              ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                                              ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                                              ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                                              ;
+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator ;
+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                                                   ;
+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                                                         ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                                         ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                                         ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                                                         ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                                         ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                                         ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                                         ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                                         ;
; UAV_ADDRESS_W                  ; 8     ; Signed Integer                                                                                                                                                                                                         ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                                         ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                                         ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                                         ;
+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_l_s1_translator ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                                                           ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                                                 ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                                                                 ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                                                 ;
; UAV_ADDRESS_W                  ; 8     ; Signed Integer                                                                                                                                                                                                                 ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                                                 ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                                                 ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_h_s1_translator ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                                                           ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                                                 ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                                                                 ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                                                 ;
; UAV_ADDRESS_W                  ; 8     ; Signed Integer                                                                                                                                                                                                                 ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                                                 ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                                                 ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                                                 ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_l_s1_translator ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                                                            ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                                                  ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                                                                  ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                                                  ;
; UAV_ADDRESS_W                  ; 8     ; Signed Integer                                                                                                                                                                                                                  ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                                                  ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                                                  ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_h_s1_translator ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                                                            ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                                                  ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                                                                  ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                                                  ;
; UAV_ADDRESS_W                  ; 8     ; Signed Integer                                                                                                                                                                                                                  ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                                                  ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                                                  ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                                                  ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:testing_s1_translator ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                                                ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                                                      ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                                      ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                                      ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                                                      ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                                      ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                                      ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                                      ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                                      ;
; UAV_ADDRESS_W                  ; 8     ; Signed Integer                                                                                                                                                                                                      ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                                      ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                                      ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                                      ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:version_s1_translator ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                                                ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                                                      ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                                      ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                                      ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                                                      ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                                      ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                                      ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                                      ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                                      ;
; UAV_ADDRESS_W                  ; 8     ; Signed Integer                                                                                                                                                                                                      ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                                      ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                                      ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                                      ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                                      ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                                                       ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                                                             ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                                             ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                                             ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                                                             ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                                             ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                                             ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                                             ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                                             ;
; UAV_ADDRESS_W                  ; 8     ; Signed Integer                                                                                                                                                                                                             ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                                             ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                                             ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                                             ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator ;
+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                                                          ;
+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                                                                ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                                                ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                                                ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                                                                ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                                                ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                                                ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                                                ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                                                ;
; UAV_ADDRESS_W                  ; 8     ; Signed Integer                                                                                                                                                                                                                ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                                                ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                                                ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                                                ;
+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator ;
+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                                                          ;
+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                                                                ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                                                ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                                                ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                                                                ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                                                ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                                                ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                                                ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                                                ;
; UAV_ADDRESS_W                  ; 8     ; Signed Integer                                                                                                                                                                                                                ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                                                ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                                                ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                                                ;
+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:if_bridge_m0_agent ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                              ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_QOS_H                 ; 62    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_QOS_L                 ; 62    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_DATA_SIDEBAND_H       ; 60    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_DATA_SIDEBAND_L       ; 60    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_ADDR_SIDEBAND_H       ; 59    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_ADDR_SIDEBAND_L       ; 59    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_CACHE_H               ; 78    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_CACHE_L               ; 75    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_THREAD_ID_H           ; 71    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_THREAD_ID_L           ; 71    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BEGIN_BURST           ; 61    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BURSTWRAP_H           ; 53    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BURSTWRAP_L           ; 53    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_ADDR_H                ; 43    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BURST_SIZE_H          ; 56    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BURST_SIZE_L          ; 54    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BURST_TYPE_H          ; 58    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BURST_TYPE_L          ; 57    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_TRANS_EXCLUSIVE       ; 49    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_TRANS_LOCK            ; 48    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_TRANS_COMPRESSED_READ ; 44    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_TRANS_READ            ; 47    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                                                    ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                    ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                    ;
; AV_BURSTCOUNT_W           ; 3     ; Signed Integer                                                                                                                                                                                                    ;
; ID                        ; 0     ; Signed Integer                                                                                                                                                                                                    ;
; SUPPRESS_0_BYTEEN_RSP     ; 0     ; Signed Integer                                                                                                                                                                                                    ;
; BURSTWRAP_VALUE           ; 1     ; Signed Integer                                                                                                                                                                                                    ;
; CACHE_VALUE               ; 0     ; Signed Integer                                                                                                                                                                                                    ;
; SECURE_ACCESS_BIT         ; 1     ; Signed Integer                                                                                                                                                                                                    ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                                    ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BURSTWRAP_W           ; 1     ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BYTE_CNT_W            ; 3     ; Signed Integer                                                                                                                                                                                                    ;
; PKT_PROTECTION_W          ; 3     ; Signed Integer                                                                                                                                                                                                    ;
; PKT_ADDR_W                ; 8     ; Signed Integer                                                                                                                                                                                                    ;
; PKT_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BYTEEN_W              ; 4     ; Signed Integer                                                                                                                                                                                                    ;
; PKT_SRC_ID_W              ; 4     ; Signed Integer                                                                                                                                                                                                    ;
; PKT_DEST_ID_W             ; 4     ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BURST_SIZE_W          ; 3     ; Signed Integer                                                                                                                                                                                                    ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_s1_agent ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                                  ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 61    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                                        ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_ADDR_H                ; 43    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_TRANS_LOCK            ; 48    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_TRANS_COMPRESSED_READ ; 44    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_TRANS_READ            ; 47    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BURSTWRAP_H           ; 53    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BURSTWRAP_L           ; 53    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BURST_SIZE_H          ; 56    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BURST_SIZE_L          ; 54    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                                                        ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                        ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                        ;
; ADDR_W                    ; 8     ; Signed Integer                                                                                                                                                                                                        ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                                        ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                                                        ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                                                        ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                                        ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                                        ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                                        ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                                        ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                                                        ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                                        ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                                                        ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                                        ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                           ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 8     ; Signed Integer                                                                                                                                                                                                                                                                 ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                                                                 ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                                                                 ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                                                 ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                                                 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                                             ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                                                   ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                                                                   ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                                                   ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                                                                   ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_s1_agent ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                                  ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 61    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                                        ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_ADDR_H                ; 43    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_TRANS_LOCK            ; 48    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_TRANS_COMPRESSED_READ ; 44    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_TRANS_READ            ; 47    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BURSTWRAP_H           ; 53    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BURSTWRAP_L           ; 53    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BURST_SIZE_H          ; 56    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BURST_SIZE_L          ; 54    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                                                        ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                        ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                        ;
; ADDR_W                    ; 8     ; Signed Integer                                                                                                                                                                                                        ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                                        ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                                                        ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                                                        ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                                        ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                                        ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                                        ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                                        ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                                                        ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                                        ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                                                        ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                                        ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                           ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 8     ; Signed Integer                                                                                                                                                                                                                                                                 ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                                                                 ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                                                                 ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                                                 ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                                                 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                                             ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                                                   ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                                                                   ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                                                   ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                                                                   ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_s1_agent ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                               ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 61    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                                     ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                                     ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_ADDR_H                ; 43    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_TRANS_LOCK            ; 48    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_TRANS_COMPRESSED_READ ; 44    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_TRANS_READ            ; 47    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_BURSTWRAP_H           ; 53    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_BURSTWRAP_L           ; 53    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_BURST_SIZE_H          ; 56    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_BURST_SIZE_L          ; 54    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                                                     ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                                                     ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                     ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                     ;
; ADDR_W                    ; 8     ; Signed Integer                                                                                                                                                                                                     ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                                     ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                                                     ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                                                     ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                                     ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                                     ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                                     ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                                     ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                                                     ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                                     ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                                                     ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                                     ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                        ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 8     ; Signed Integer                                                                                                                                                                                                                                                              ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                                                              ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                                                              ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                                              ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                                              ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo ;
+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                                          ;
+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                                                ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                                                                ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                                                ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                                                ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                                                ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                                                ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                                                                ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                ;
+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_ip_addr_s1_agent ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                                    ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 61    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                                          ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_ADDR_H                ; 43    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_TRANS_LOCK            ; 48    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_TRANS_COMPRESSED_READ ; 44    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_TRANS_READ            ; 47    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_BURSTWRAP_H           ; 53    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_BURSTWRAP_L           ; 53    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_BURST_SIZE_H          ; 56    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_BURST_SIZE_L          ; 54    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                                                          ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                                                          ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                          ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                          ;
; ADDR_W                    ; 8     ; Signed Integer                                                                                                                                                                                                          ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                                          ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                                                          ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                                                          ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                                          ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                                          ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                                                          ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                                          ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                                                          ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                                          ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                             ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 8     ; Signed Integer                                                                                                                                                                                                                                                                   ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                                                                   ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                                                                   ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                                                   ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo ;
+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                                               ;
+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                                                     ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                                                                     ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                                                     ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                                                     ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                     ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                                                     ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                                                     ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                                                     ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                                                     ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                                                     ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                                                     ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                                                     ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                                                                     ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                     ;
+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_ip_addr_s1_agent ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                                   ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 61    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                                         ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_ADDR_H                ; 43    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_TRANS_LOCK            ; 48    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_TRANS_COMPRESSED_READ ; 44    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_TRANS_READ            ; 47    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_BURSTWRAP_H           ; 53    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_BURSTWRAP_L           ; 53    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_BURST_SIZE_H          ; 56    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_BURST_SIZE_L          ; 54    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                                                         ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                         ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                         ;
; ADDR_W                    ; 8     ; Signed Integer                                                                                                                                                                                                         ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                                         ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                                                         ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                                                         ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                                         ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                                                         ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                                         ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                                                         ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                                         ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_ip_addr_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                            ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 8     ; Signed Integer                                                                                                                                                                                                                                                                  ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                                                                  ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                                                                  ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                                                  ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                                                  ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                                              ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                                                    ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                                                                    ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                                                    ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                                                    ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                    ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                                                    ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                                                    ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                                                    ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                                                    ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                                                    ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                                                    ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                                                    ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                                                                    ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                    ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:rot_switch_s1_agent ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                              ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 61    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                                    ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_ADDR_H                ; 43    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_TRANS_LOCK            ; 48    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_TRANS_COMPRESSED_READ ; 44    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_TRANS_READ            ; 47    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BURSTWRAP_H           ; 53    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BURSTWRAP_L           ; 53    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BURST_SIZE_H          ; 56    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_BURST_SIZE_L          ; 54    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                                                    ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                                                    ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                    ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                    ;
; ADDR_W                    ; 8     ; Signed Integer                                                                                                                                                                                                    ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                                    ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                                                    ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                                                    ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                                    ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                                    ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                                    ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                                    ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                                                    ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                                    ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                                                    ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                                    ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:rot_switch_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                       ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 8     ; Signed Integer                                                                                                                                                                                                                                                             ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                                                             ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                                                             ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                                             ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                                             ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo ;
+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                                         ;
+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                                               ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                                                               ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                                               ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                                               ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                                               ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                                               ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                                                               ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                               ;
+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_l_s1_agent ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                                      ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 61    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                                            ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_ADDR_H                ; 43    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_TRANS_LOCK            ; 48    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_TRANS_COMPRESSED_READ ; 44    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_TRANS_READ            ; 47    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_BURSTWRAP_H           ; 53    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_BURSTWRAP_L           ; 53    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_BURST_SIZE_H          ; 56    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_BURST_SIZE_L          ; 54    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                                                            ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                            ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                            ;
; ADDR_W                    ; 8     ; Signed Integer                                                                                                                                                                                                            ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                                            ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                                                            ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                                                            ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                                            ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                                                            ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                                            ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                                                            ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                                            ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                               ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 8     ; Signed Integer                                                                                                                                                                                                                                                                     ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                                                                     ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                                                                     ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                                                     ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                                                     ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                                                 ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                                                       ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                                                                       ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                                                       ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                                                       ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                       ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                                                       ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                                                       ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                                                       ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                                                       ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                                                       ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                                                       ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                                                       ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                                                                       ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                       ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_h_s1_agent ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                                      ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 61    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                                            ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_ADDR_H                ; 43    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_TRANS_LOCK            ; 48    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_TRANS_COMPRESSED_READ ; 44    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_TRANS_READ            ; 47    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_BURSTWRAP_H           ; 53    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_BURSTWRAP_L           ; 53    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_BURST_SIZE_H          ; 56    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_BURST_SIZE_L          ; 54    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                                                            ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                                                            ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                            ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                            ;
; ADDR_W                    ; 8     ; Signed Integer                                                                                                                                                                                                            ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                                            ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                                                            ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                                                            ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                                            ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                                                            ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                                            ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                                                            ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                                            ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                               ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 8     ; Signed Integer                                                                                                                                                                                                                                                                     ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                                                                     ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                                                                     ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                                                     ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                                                     ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                                                 ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                                                       ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                                                                       ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                                                       ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                                                       ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                       ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                                                       ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                                                       ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                                                       ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                                                       ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                                                       ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                                                       ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                                                       ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                                                                       ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                       ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_l_s1_agent ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                                       ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 61    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                                             ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_ADDR_H                ; 43    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_TRANS_LOCK            ; 48    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_TRANS_COMPRESSED_READ ; 44    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_TRANS_READ            ; 47    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_BURSTWRAP_H           ; 53    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_BURSTWRAP_L           ; 53    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_BURST_SIZE_H          ; 56    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_BURST_SIZE_L          ; 54    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                                                             ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                             ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                             ;
; ADDR_W                    ; 8     ; Signed Integer                                                                                                                                                                                                             ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                                             ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                                                             ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                                                             ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                                             ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                                                             ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                                             ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                                                             ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                                             ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                                ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 8     ; Signed Integer                                                                                                                                                                                                                                                                      ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                                                                      ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                                                                      ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                                                      ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                                                      ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                                                  ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                                                        ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                                                                        ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                                                        ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                                                        ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                        ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                                                        ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                                                        ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                                                        ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                                                        ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                                                        ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                                                        ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                                                        ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                                                                        ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                        ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_h_s1_agent ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                                       ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 61    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                                             ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_ADDR_H                ; 43    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_TRANS_LOCK            ; 48    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_TRANS_COMPRESSED_READ ; 44    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_TRANS_READ            ; 47    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_BURSTWRAP_H           ; 53    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_BURSTWRAP_L           ; 53    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_BURST_SIZE_H          ; 56    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_BURST_SIZE_L          ; 54    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                                                             ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                                                             ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                             ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                             ;
; ADDR_W                    ; 8     ; Signed Integer                                                                                                                                                                                                             ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                                             ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                                                             ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                                                             ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                                             ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                                             ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                                                             ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                                             ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                                                             ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                                             ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_h_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                                ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 8     ; Signed Integer                                                                                                                                                                                                                                                                      ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                                                                      ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                                                                      ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                                                      ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                                                      ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                                                  ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                                                        ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                                                                        ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                                                        ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                                                        ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                        ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                                                        ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                                                        ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                                                        ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                                                        ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                                                        ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                                                        ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                                                        ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                                                                        ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                        ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:testing_s1_agent ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                           ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 61    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                                 ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                                 ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_ADDR_H                ; 43    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_TRANS_LOCK            ; 48    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_TRANS_COMPRESSED_READ ; 44    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_TRANS_READ            ; 47    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_BURSTWRAP_H           ; 53    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_BURSTWRAP_L           ; 53    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_BURST_SIZE_H          ; 56    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_BURST_SIZE_L          ; 54    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                                                 ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                 ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                 ;
; ADDR_W                    ; 8     ; Signed Integer                                                                                                                                                                                                 ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                                 ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                                                 ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                                                 ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                                 ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                                 ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                                 ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                                 ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                                                 ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                                 ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                                                 ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                                 ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:testing_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                    ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 8     ; Signed Integer                                                                                                                                                                                                                                                          ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                                                          ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                                                          ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                                          ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                                          ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                                      ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                                            ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                                                            ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                                            ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                                            ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                                            ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                                                            ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                            ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:version_s1_agent ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                           ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 61    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                                 ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                                 ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_ADDR_H                ; 43    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_TRANS_LOCK            ; 48    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_TRANS_COMPRESSED_READ ; 44    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_TRANS_READ            ; 47    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_BURSTWRAP_H           ; 53    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_BURSTWRAP_L           ; 53    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_BURST_SIZE_H          ; 56    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_BURST_SIZE_L          ; 54    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                                                 ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                                                 ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                 ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                 ;
; ADDR_W                    ; 8     ; Signed Integer                                                                                                                                                                                                 ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                                 ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                                                 ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                                                 ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                                 ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                                 ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                                 ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                                 ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                                                 ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                                 ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                                                 ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                                 ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:version_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                    ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 8     ; Signed Integer                                                                                                                                                                                                                                                          ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                                                          ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                                                          ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                                          ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                                          ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                                      ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                                            ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                                                            ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                                            ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                                            ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                                            ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                                            ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                                                            ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                            ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_in_s1_agent ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                                  ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 61    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                                        ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_ADDR_H                ; 43    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_TRANS_LOCK            ; 48    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_TRANS_COMPRESSED_READ ; 44    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_TRANS_READ            ; 47    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BURSTWRAP_H           ; 53    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BURSTWRAP_L           ; 53    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BURST_SIZE_H          ; 56    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_BURST_SIZE_L          ; 54    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                                                        ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                                                        ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                        ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                        ;
; ADDR_W                    ; 8     ; Signed Integer                                                                                                                                                                                                        ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                                        ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                                                        ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                                                        ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                                        ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                                        ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                                        ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                                        ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                                                        ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                                        ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                                                        ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                                        ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                           ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 8     ; Signed Integer                                                                                                                                                                                                                                                                 ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                                                                 ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                                                                 ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                                                 ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                                                 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                                             ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                                                   ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                                                                   ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                                                   ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                                                   ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                                                                   ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                   ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_in_s1_agent ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                                     ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 61    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                                           ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                                           ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_ADDR_H                ; 43    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_TRANS_LOCK            ; 48    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_TRANS_COMPRESSED_READ ; 44    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_TRANS_READ            ; 47    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_BURSTWRAP_H           ; 53    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_BURSTWRAP_L           ; 53    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_BURST_SIZE_H          ; 56    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_BURST_SIZE_L          ; 54    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                                                           ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                           ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                           ;
; ADDR_W                    ; 8     ; Signed Integer                                                                                                                                                                                                           ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                                           ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                                                           ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                                                           ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                                           ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                                           ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                                           ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                                           ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                                                           ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                                           ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                                                           ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                                           ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                              ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 8     ; Signed Integer                                                                                                                                                                                                                                                                    ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                                                                    ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                                                                    ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                                                    ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                                                    ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo ;
+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                                                ;
+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                                                      ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                                                                      ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                                                      ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                                                      ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                      ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                                                      ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                                                      ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                                                      ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                                                      ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                                                      ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                                                      ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                                                      ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                                                                      ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                      ;
+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_in_s1_agent ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                                     ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 61    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                                           ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                                           ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_ADDR_H                ; 43    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_TRANS_LOCK            ; 48    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_TRANS_COMPRESSED_READ ; 44    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_TRANS_READ            ; 47    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_BURSTWRAP_H           ; 53    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_BURSTWRAP_L           ; 53    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_BURST_SIZE_H          ; 56    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_BURST_SIZE_L          ; 54    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                                                           ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                                                           ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                           ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                           ;
; ADDR_W                    ; 8     ; Signed Integer                                                                                                                                                                                                           ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                                           ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                                                           ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                                                           ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                                           ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                                           ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                                           ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                                           ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                                                           ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                                           ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                                                           ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                                           ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_in_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                              ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 8     ; Signed Integer                                                                                                                                                                                                                                                                    ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                                                                    ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                                                                    ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                                                    ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                                                    ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo ;
+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                                                ;
+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                                                      ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                                                                      ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                                                      ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                                                      ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                      ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                                                      ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                                                      ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                                                      ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                                                      ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                                                      ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                                                      ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                                                      ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                                                                      ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                                                      ;
+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router:router|nios2_fabric_if_mm_interconnect_0_router_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                                                                  ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                        ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                        ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                        ;
; DEFAULT_DESTID     ; 10    ; Signed Integer                                                                                                                                                                                                                                                                                        ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_001|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                                                                              ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_002|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                                                                              ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_003|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                                                                              ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_004|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                                                                              ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_005|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                                                                              ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_006|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                                                                              ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_007|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                                                                              ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_008|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                                                                              ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_009|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                                                                              ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_010|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                                                                              ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_011|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                                                                              ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_012|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                                                                              ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_013|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                                                                              ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_014|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                                                                              ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_015|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                                                                              ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                                                                                    ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:if_bridge_m0_limiter ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                                                   ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_TRANS_POSTED          ; 45    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_DEST_ID_L             ; 67    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_SRC_ID_H              ; 66    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_SRC_ID_L              ; 63    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_BYTE_CNT_H            ; 52    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_BYTE_CNT_L            ; 50    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_TRANS_WRITE           ; 46    ; Signed Integer                                                                                                                                                                                                         ;
; PKT_TRANS_READ            ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                                                         ;
; ST_CHANNEL_W              ; 15    ; Signed Integer                                                                                                                                                                                                         ;
; MAX_OUTSTANDING_RESPONSES ; 1     ; Signed Integer                                                                                                                                                                                                         ;
; PIPELINED                 ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; ENFORCE_ORDER             ; 1     ; Signed Integer                                                                                                                                                                                                         ;
; VALID_WIDTH               ; 15    ; Signed Integer                                                                                                                                                                                                         ;
; PREVENT_HAZARDS           ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; SUPPORTS_POSTED_WRITES    ; 1     ; Signed Integer                                                                                                                                                                                                         ;
; SUPPORTS_NONPOSTED_WRITES ; 0     ; Signed Integer                                                                                                                                                                                                         ;
; REORDER                   ; 0     ; Signed Integer                                                                                                                                                                                                         ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb ;
+----------------+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                                                                                                                                                                                                         ;
+----------------+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; NUM_REQUESTERS ; 15     ; Signed Integer                                                                                                                                                                                                                                               ;
; SCHEME         ; no-arb ; String                                                                                                                                                                                                                                                       ;
; PIPELINE       ; 0      ; Signed Integer                                                                                                                                                                                                                                               ;
+----------------+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                                        ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; WIDTH          ; 30    ; Signed Integer                                                                                                                                                                                                                                                                              ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter ;
+-----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                      ;
+-----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                                                            ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                                                            ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                                                            ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                                                            ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                                                            ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                                                            ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                                                            ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                                                            ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                                                            ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                                                            ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                                                            ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                                                            ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                                                            ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                                                            ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                                                            ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                                                            ;
+-----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                          ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                          ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                          ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_004 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                          ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                          ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                          ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                          ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                          ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                          ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                          ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                          ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                          ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                          ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_014 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                                                          ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                                                                ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                                                                ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller ;
+---------------------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value    ; Type                                                                                                                                                ;
+---------------------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; NUM_RESET_INPUTS          ; 1        ; Signed Integer                                                                                                                                      ;
; USE_RESET_REQUEST_IN0     ; 0        ; Signed Integer                                                                                                                                      ;
; USE_RESET_REQUEST_IN1     ; 0        ; Signed Integer                                                                                                                                      ;
; USE_RESET_REQUEST_IN2     ; 0        ; Signed Integer                                                                                                                                      ;
; USE_RESET_REQUEST_IN3     ; 0        ; Signed Integer                                                                                                                                      ;
; USE_RESET_REQUEST_IN4     ; 0        ; Signed Integer                                                                                                                                      ;
; USE_RESET_REQUEST_IN5     ; 0        ; Signed Integer                                                                                                                                      ;
; USE_RESET_REQUEST_IN6     ; 0        ; Signed Integer                                                                                                                                      ;
; USE_RESET_REQUEST_IN7     ; 0        ; Signed Integer                                                                                                                                      ;
; USE_RESET_REQUEST_IN8     ; 0        ; Signed Integer                                                                                                                                      ;
; USE_RESET_REQUEST_IN9     ; 0        ; Signed Integer                                                                                                                                      ;
; USE_RESET_REQUEST_IN10    ; 0        ; Signed Integer                                                                                                                                      ;
; USE_RESET_REQUEST_IN11    ; 0        ; Signed Integer                                                                                                                                      ;
; USE_RESET_REQUEST_IN12    ; 0        ; Signed Integer                                                                                                                                      ;
; USE_RESET_REQUEST_IN13    ; 0        ; Signed Integer                                                                                                                                      ;
; USE_RESET_REQUEST_IN14    ; 0        ; Signed Integer                                                                                                                                      ;
; USE_RESET_REQUEST_IN15    ; 0        ; Signed Integer                                                                                                                                      ;
; OUTPUT_RESET_SYNC_EDGES   ; deassert ; String                                                                                                                                              ;
; SYNC_DEPTH                ; 2        ; Signed Integer                                                                                                                                      ;
; RESET_REQUEST_PRESENT     ; 0        ; Signed Integer                                                                                                                                      ;
; RESET_REQ_WAIT_TIME       ; 1        ; Signed Integer                                                                                                                                      ;
; MIN_RST_ASSERTION_TIME    ; 3        ; Signed Integer                                                                                                                                      ;
; RESET_REQ_EARLY_DSRT_TIME ; 1        ; Signed Integer                                                                                                                                      ;
; ADAPT_RESET_REQUEST       ; 0        ; Signed Integer                                                                                                                                      ;
+---------------------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                         ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ASYNC_RESET    ; 1     ; Unsigned Binary                                                                                                                                                                                              ;
; DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                               ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                             ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ASYNC_RESET    ; 0     ; Signed Integer                                                                                                                                                                                                   ;
; DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                                   ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo ;
+-------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                                                                                   ;
+-------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                                                                             ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                                                                           ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                                                                           ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                                                                         ;
; lpm_width               ; 8           ; Signed Integer                                                                                                                                                                         ;
; LPM_NUMWORDS            ; 64          ; Signed Integer                                                                                                                                                                         ;
; LPM_WIDTHU              ; 6           ; Signed Integer                                                                                                                                                                         ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                                                                                ;
; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                                                                                                                                                ;
; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                                                                                                                                                ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                                                                                                                                ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                                                                                ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                                                                                                                                                ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                                                                                                                                ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                                                                                ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                                                                                ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                                                                                ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                                                                                ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                                                                                                                                                ;
; CBXI_PARAMETER          ; scfifo_3291 ; Untyped                                                                                                                                                                                ;
+-------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r|scfifo:rfifo ;
+-------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                                                                                   ;
+-------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                                                                             ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                                                                           ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                                                                           ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                                                                         ;
; lpm_width               ; 8           ; Signed Integer                                                                                                                                                                         ;
; LPM_NUMWORDS            ; 64          ; Signed Integer                                                                                                                                                                         ;
; LPM_WIDTHU              ; 6           ; Signed Integer                                                                                                                                                                         ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                                                                                ;
; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                                                                                                                                                ;
; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                                                                                                                                                ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                                                                                                                                ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                                                                                ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                                                                                                                                                ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                                                                                                                                ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                                                                                ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                                                                                ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                                                                                ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                                                                                ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                                                                                                                                                ;
; CBXI_PARAMETER          ; scfifo_3291 ; Untyped                                                                                                                                                                                ;
+-------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a ;
+----------------+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                                                                                                                                                         ;
+----------------+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                                                                                                                                                       ;
+----------------+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                                                                                                                                 ;
+------------------------------------+----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                                                                                                                              ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                                                                                                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                                                                                                                         ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                                                                                                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                                                                                                                       ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                                                                                                                              ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                                                                                                                                              ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                                                                                                                                                       ;
; WIDTHAD_A                          ; 5                    ; Signed Integer                                                                                                                                                                                       ;
; NUMWORDS_A                         ; 32                   ; Signed Integer                                                                                                                                                                                       ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                              ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                              ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                              ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                                                                                                                              ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                                                                                                                              ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                              ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                                                                                                                                                       ;
; WIDTHAD_B                          ; 5                    ; Signed Integer                                                                                                                                                                                       ;
; NUMWORDS_B                         ; 32                   ; Signed Integer                                                                                                                                                                                       ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                                                                                                                                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                                                                                                                                              ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                                                                                                                                                              ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                                                                                                                                              ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                              ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                              ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                                                                                                                              ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                              ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                              ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                              ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                              ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                              ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                                                                                                                                              ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                                                                                                                                              ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                                                                                                                              ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                                                                                                                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                                                                                                                                                              ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                              ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                              ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                                                                                                                                                              ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                                                                                                                              ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                                                                                                                                                       ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                                                                                                                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                                                                                                                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                                                                                                                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                                                                                                                              ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                              ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                              ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                                                                                                                              ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                                                                                                                                                                              ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                                                                                                                                              ;
; DEVICE_FAMILY                      ; Cyclone V            ; Untyped                                                                                                                                                                                              ;
; CBXI_PARAMETER                     ; altsyncram_msi1      ; Untyped                                                                                                                                                                                              ;
+------------------------------------+----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_b_module:nios2_nios2_cpu_register_bank_b ;
+----------------+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                                                                                                                                                         ;
+----------------+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                                                                                                                                                       ;
+----------------+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_b_module:nios2_nios2_cpu_register_bank_b|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                                                                                                                                 ;
+------------------------------------+----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                                                                                                                              ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                                                                                                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                                                                                                                         ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                                                                                                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                                                                                                                       ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                                                                                                                              ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                                                                                                                                              ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                                                                                                                                                       ;
; WIDTHAD_A                          ; 5                    ; Signed Integer                                                                                                                                                                                       ;
; NUMWORDS_A                         ; 32                   ; Signed Integer                                                                                                                                                                                       ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                              ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                              ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                              ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                                                                                                                              ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                                                                                                                              ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                              ;
; WIDTH_B                            ; 32                   ; Signed Integer                                                                                                                                                                                       ;
; WIDTHAD_B                          ; 5                    ; Signed Integer                                                                                                                                                                                       ;
; NUMWORDS_B                         ; 32                   ; Signed Integer                                                                                                                                                                                       ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                                                                                                                                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                                                                                                                                              ;
; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                                                                                                                                                              ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                                                                                                                                              ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                              ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                              ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                                                                                                                              ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                              ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                              ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                              ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                              ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                              ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                                                                                                                                              ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                                                                                                                                              ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                                                                                                                              ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                                                                                                                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                                                                                                                                                              ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                              ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                              ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                                                                                                                                                              ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                                                                                                                              ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                                                                                                                                                       ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                                                                                                                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                                                                                                                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                                                                                                                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                                                                                                                              ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                              ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                              ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                                                                                                                              ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                                                                                                                                                                              ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                                                                                                                                              ;
; DEVICE_FAMILY                      ; Cyclone V            ; Untyped                                                                                                                                                                                              ;
; CBXI_PARAMETER                     ; altsyncram_msi1      ; Untyped                                                                                                                                                                                              ;
+------------------------------------+----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_debug:the_nios2_nios2_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                                                                   ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                                                                                         ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram ;
+----------------+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                                                                                                                                                                                                                                                                           ;
+----------------+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                                                                                                                                                                                                                                                                         ;
+----------------+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                                                                                                                                                                                                                                                   ;
+------------------------------------+----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                                                                                                                                                                                                                                                ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                                                                                                                                                                                                                                             ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                                                                                                                                                                                                                                           ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                                                                                                                                                                                                                                           ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                                                                                                                                                                                                                                         ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                                                                                                                                                                                                                                                ;
; OPERATION_MODE                     ; SINGLE_PORT          ; Untyped                                                                                                                                                                                                                                                                                                                ;
; WIDTH_A                            ; 32                   ; Signed Integer                                                                                                                                                                                                                                                                                                         ;
; WIDTHAD_A                          ; 8                    ; Signed Integer                                                                                                                                                                                                                                                                                                         ;
; NUMWORDS_A                         ; 256                  ; Signed Integer                                                                                                                                                                                                                                                                                                         ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                                                                                                                                                ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                                                ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                                                ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                                                ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                                                ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                                                ;
; WIDTH_B                            ; 1                    ; Untyped                                                                                                                                                                                                                                                                                                                ;
; WIDTHAD_B                          ; 1                    ; Untyped                                                                                                                                                                                                                                                                                                                ;
; NUMWORDS_B                         ; 1                    ; Untyped                                                                                                                                                                                                                                                                                                                ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                                                                                                                                                                                                                                                                ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                                                                                                                                                                                                                                                                ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                                                                                                                                                                                                                                                                ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                                                                                                                                                ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                                                                                                                                                ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                                                                                                                                                ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                                                ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                                                ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                                                ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                                                ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                                                ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                                                ;
; WIDTH_BYTEENA_A                    ; 4                    ; Signed Integer                                                                                                                                                                                                                                                                                                         ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                                                                                                                                                                                                                                                                ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                                                                                                                                                                                                                                                ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                                                                                                                                                                                                                                                                ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                                                                                                                                                                                                                                                                                ;
; READ_DURING_WRITE_MODE_PORT_A      ; DONT_CARE            ; Untyped                                                                                                                                                                                                                                                                                                                ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                                                                                                                                                ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                                                                                                                                                                                                                                                                                ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                                                                                                                                                                                                                                                ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                                                                                                                                                                                                                                                                                                         ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                                                                                                                                                                                                                                                ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                                                                                                                                                                                                                                                ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                                                                                                                                                                                                                                                ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                                                                                                                                                                                                                                                ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                                                                                                                                                ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                                                                                                                                                ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                                                                                                                                                                                                                                                ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                                                                                                                                                                                                                                                                                                ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                                                                                                                                                                                                                                                                ;
; DEVICE_FAMILY                      ; Cyclone V            ; Untyped                                                                                                                                                                                                                                                                                                                ;
; CBXI_PARAMETER                     ; altsyncram_qid1      ; Untyped                                                                                                                                                                                                                                                                                                                ;
+------------------------------------+----------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                                                                                                                                                ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                                                                                                                                                                      ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck|altera_std_synchronizer:the_altera_std_synchronizer2 ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                                                                                                                                                ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                                                                                                                                                                      ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                                                                                                                                                      ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                                                                                                                                                                            ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                                                                                                                                                      ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                                                                                                                                                                                            ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:nios2_nios2_cpu_debug_slave_phy ;
+-------------------------+------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value                  ; Type                                                                                                                                                                                                                                                                                                    ;
+-------------------------+------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; sld_mfg_id              ; 70                     ; Signed Integer                                                                                                                                                                                                                                                                                          ;
; sld_type_id             ; 34                     ; Signed Integer                                                                                                                                                                                                                                                                                          ;
; sld_version             ; 3                      ; Signed Integer                                                                                                                                                                                                                                                                                          ;
; sld_instance_index      ; 0                      ; Signed Integer                                                                                                                                                                                                                                                                                          ;
; sld_auto_instance_index ; YES                    ; String                                                                                                                                                                                                                                                                                                  ;
; sld_ir_width            ; 2                      ; Signed Integer                                                                                                                                                                                                                                                                                          ;
; sld_sim_n_scan          ; 0                      ; Signed Integer                                                                                                                                                                                                                                                                                          ;
; sld_sim_action          ;                        ; String                                                                                                                                                                                                                                                                                                  ;
; sld_sim_total_length    ; 0                      ; Signed Integer                                                                                                                                                                                                                                                                                          ;
; lpm_type                ; sld_virtual_jtag_basic ; String                                                                                                                                                                                                                                                                                                  ;
; lpm_hint                ; UNUSED                 ; String                                                                                                                                                                                                                                                                                                  ;
+-------------------------+------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem ;
+----------------+---------------------------------------------------------------------------+----------------------------------------------------------+
; Parameter Name ; Value                                                                     ; Type                                                     ;
+----------------+---------------------------------------------------------------------------+----------------------------------------------------------+
; INIT_FILE      ; J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex ; String                                                   ;
+----------------+---------------------------------------------------------------------------+----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram ;
+------------------------------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
; Parameter Name                     ; Value                                                                     ; Type                                                           ;
+------------------------------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                                                                         ; Untyped                                                        ;
; AUTO_CARRY_CHAINS                  ; ON                                                                        ; AUTO_CARRY                                                     ;
; IGNORE_CARRY_BUFFERS               ; OFF                                                                       ; IGNORE_CARRY                                                   ;
; AUTO_CASCADE_CHAINS                ; ON                                                                        ; AUTO_CASCADE                                                   ;
; IGNORE_CASCADE_BUFFERS             ; OFF                                                                       ; IGNORE_CASCADE                                                 ;
; WIDTH_BYTEENA                      ; 1                                                                         ; Untyped                                                        ;
; OPERATION_MODE                     ; SINGLE_PORT                                                               ; Untyped                                                        ;
; WIDTH_A                            ; 32                                                                        ; Signed Integer                                                 ;
; WIDTHAD_A                          ; 15                                                                        ; Signed Integer                                                 ;
; NUMWORDS_A                         ; 32768                                                                     ; Signed Integer                                                 ;
; OUTDATA_REG_A                      ; UNREGISTERED                                                              ; Untyped                                                        ;
; ADDRESS_ACLR_A                     ; NONE                                                                      ; Untyped                                                        ;
; OUTDATA_ACLR_A                     ; NONE                                                                      ; Untyped                                                        ;
; WRCONTROL_ACLR_A                   ; NONE                                                                      ; Untyped                                                        ;
; INDATA_ACLR_A                      ; NONE                                                                      ; Untyped                                                        ;
; BYTEENA_ACLR_A                     ; NONE                                                                      ; Untyped                                                        ;
; WIDTH_B                            ; 1                                                                         ; Untyped                                                        ;
; WIDTHAD_B                          ; 1                                                                         ; Untyped                                                        ;
; NUMWORDS_B                         ; 1                                                                         ; Untyped                                                        ;
; INDATA_REG_B                       ; CLOCK1                                                                    ; Untyped                                                        ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                                                                    ; Untyped                                                        ;
; RDCONTROL_REG_B                    ; CLOCK1                                                                    ; Untyped                                                        ;
; ADDRESS_REG_B                      ; CLOCK1                                                                    ; Untyped                                                        ;
; OUTDATA_REG_B                      ; UNREGISTERED                                                              ; Untyped                                                        ;
; BYTEENA_REG_B                      ; CLOCK1                                                                    ; Untyped                                                        ;
; INDATA_ACLR_B                      ; NONE                                                                      ; Untyped                                                        ;
; WRCONTROL_ACLR_B                   ; NONE                                                                      ; Untyped                                                        ;
; ADDRESS_ACLR_B                     ; NONE                                                                      ; Untyped                                                        ;
; OUTDATA_ACLR_B                     ; NONE                                                                      ; Untyped                                                        ;
; RDCONTROL_ACLR_B                   ; NONE                                                                      ; Untyped                                                        ;
; BYTEENA_ACLR_B                     ; NONE                                                                      ; Untyped                                                        ;
; WIDTH_BYTEENA_A                    ; 4                                                                         ; Signed Integer                                                 ;
; WIDTH_BYTEENA_B                    ; 1                                                                         ; Untyped                                                        ;
; RAM_BLOCK_TYPE                     ; AUTO                                                                      ; Untyped                                                        ;
; BYTE_SIZE                          ; 8                                                                         ; Signed Integer                                                 ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                 ; Untyped                                                        ;
; READ_DURING_WRITE_MODE_PORT_A      ; DONT_CARE                                                                 ; Untyped                                                        ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ                                                      ; Untyped                                                        ;
; INIT_FILE                          ; J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex ; Untyped                                                        ;
; INIT_FILE_LAYOUT                   ; PORT_A                                                                    ; Untyped                                                        ;
; MAXIMUM_DEPTH                      ; 32768                                                                     ; Signed Integer                                                 ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                                                                    ; Untyped                                                        ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                                                                    ; Untyped                                                        ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                                                                    ; Untyped                                                        ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                                                                    ; Untyped                                                        ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                                                           ; Untyped                                                        ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                                                           ; Untyped                                                        ;
; ENABLE_ECC                         ; FALSE                                                                     ; Untyped                                                        ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                                                                     ; Untyped                                                        ;
; WIDTH_ECCSTATUS                    ; 3                                                                         ; Untyped                                                        ;
; DEVICE_FAMILY                      ; Cyclone V                                                                 ; Untyped                                                        ;
; CBXI_PARAMETER                     ; altsyncram_pnr1                                                           ; Untyped                                                        ;
+------------------------------------+---------------------------------------------------------------------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_pll_enet:pll_enet|altera_pll:altera_pll_i ;
+--------------------------------------+------------------------+-----------------------------------------------------------------------------------------------------------+
; Parameter Name                       ; Value                  ; Type                                                                                                      ;
+--------------------------------------+------------------------+-----------------------------------------------------------------------------------------------------------+
; reference_clock_frequency            ; 40.0 MHz               ; String                                                                                                    ;
; fractional_vco_multiplier            ; false                  ; String                                                                                                    ;
; pll_type                             ; General                ; String                                                                                                    ;
; pll_subtype                          ; General                ; String                                                                                                    ;
; number_of_clocks                     ; 1                      ; Signed Integer                                                                                            ;
; operation_mode                       ; direct                 ; String                                                                                                    ;
; deserialization_factor               ; 4                      ; Signed Integer                                                                                            ;
; data_rate                            ; 0                      ; Signed Integer                                                                                            ;
; sim_additional_refclk_cycles_to_lock ; 0                      ; Signed Integer                                                                                            ;
; output_clock_frequency0              ; 125.000000 MHz         ; String                                                                                                    ;
; phase_shift0                         ; 0 ps                   ; String                                                                                                    ;
; duty_cycle0                          ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency1              ; 0 MHz                  ; String                                                                                                    ;
; phase_shift1                         ; 0 ps                   ; String                                                                                                    ;
; duty_cycle1                          ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency2              ; 0 MHz                  ; String                                                                                                    ;
; phase_shift2                         ; 0 ps                   ; String                                                                                                    ;
; duty_cycle2                          ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency3              ; 0 MHz                  ; String                                                                                                    ;
; phase_shift3                         ; 0 ps                   ; String                                                                                                    ;
; duty_cycle3                          ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency4              ; 0 MHz                  ; String                                                                                                    ;
; phase_shift4                         ; 0 ps                   ; String                                                                                                    ;
; duty_cycle4                          ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency5              ; 0 MHz                  ; String                                                                                                    ;
; phase_shift5                         ; 0 ps                   ; String                                                                                                    ;
; duty_cycle5                          ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency6              ; 0 MHz                  ; String                                                                                                    ;
; phase_shift6                         ; 0 ps                   ; String                                                                                                    ;
; duty_cycle6                          ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency7              ; 0 MHz                  ; String                                                                                                    ;
; phase_shift7                         ; 0 ps                   ; String                                                                                                    ;
; duty_cycle7                          ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency8              ; 0 MHz                  ; String                                                                                                    ;
; phase_shift8                         ; 0 ps                   ; String                                                                                                    ;
; duty_cycle8                          ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency9              ; 0 MHz                  ; String                                                                                                    ;
; phase_shift9                         ; 0 ps                   ; String                                                                                                    ;
; duty_cycle9                          ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency10             ; 0 MHz                  ; String                                                                                                    ;
; phase_shift10                        ; 0 ps                   ; String                                                                                                    ;
; duty_cycle10                         ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency11             ; 0 MHz                  ; String                                                                                                    ;
; phase_shift11                        ; 0 ps                   ; String                                                                                                    ;
; duty_cycle11                         ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency12             ; 0 MHz                  ; String                                                                                                    ;
; phase_shift12                        ; 0 ps                   ; String                                                                                                    ;
; duty_cycle12                         ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency13             ; 0 MHz                  ; String                                                                                                    ;
; phase_shift13                        ; 0 ps                   ; String                                                                                                    ;
; duty_cycle13                         ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency14             ; 0 MHz                  ; String                                                                                                    ;
; phase_shift14                        ; 0 ps                   ; String                                                                                                    ;
; duty_cycle14                         ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency15             ; 0 MHz                  ; String                                                                                                    ;
; phase_shift15                        ; 0 ps                   ; String                                                                                                    ;
; duty_cycle15                         ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency16             ; 0 MHz                  ; String                                                                                                    ;
; phase_shift16                        ; 0 ps                   ; String                                                                                                    ;
; duty_cycle16                         ; 50                     ; Signed Integer                                                                                            ;
; output_clock_frequency17             ; 0 MHz                  ; String                                                                                                    ;
; phase_shift17                        ; 0 ps                   ; String                                                                                                    ;
; duty_cycle17                         ; 50                     ; Signed Integer                                                                                            ;
; clock_name_0                         ;                        ; String                                                                                                    ;
; clock_name_1                         ;                        ; String                                                                                                    ;
; clock_name_2                         ;                        ; String                                                                                                    ;
; clock_name_3                         ;                        ; String                                                                                                    ;
; clock_name_4                         ;                        ; String                                                                                                    ;
; clock_name_5                         ;                        ; String                                                                                                    ;
; clock_name_6                         ;                        ; String                                                                                                    ;
; clock_name_7                         ;                        ; String                                                                                                    ;
; clock_name_8                         ;                        ; String                                                                                                    ;
; clock_name_global_0                  ; false                  ; String                                                                                                    ;
; clock_name_global_1                  ; false                  ; String                                                                                                    ;
; clock_name_global_2                  ; false                  ; String                                                                                                    ;
; clock_name_global_3                  ; false                  ; String                                                                                                    ;
; clock_name_global_4                  ; false                  ; String                                                                                                    ;
; clock_name_global_5                  ; false                  ; String                                                                                                    ;
; clock_name_global_6                  ; false                  ; String                                                                                                    ;
; clock_name_global_7                  ; false                  ; String                                                                                                    ;
; clock_name_global_8                  ; false                  ; String                                                                                                    ;
; m_cnt_hi_div                         ; 1                      ; Signed Integer                                                                                            ;
; m_cnt_lo_div                         ; 1                      ; Signed Integer                                                                                            ;
; m_cnt_bypass_en                      ; false                  ; String                                                                                                    ;
; m_cnt_odd_div_duty_en                ; false                  ; String                                                                                                    ;
; n_cnt_hi_div                         ; 1                      ; Signed Integer                                                                                            ;
; n_cnt_lo_div                         ; 1                      ; Signed Integer                                                                                            ;
; n_cnt_bypass_en                      ; false                  ; String                                                                                                    ;
; n_cnt_odd_div_duty_en                ; false                  ; String                                                                                                    ;
; c_cnt_hi_div0                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div0                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en0                     ; false                  ; String                                                                                                    ;
; c_cnt_in_src0                        ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en0               ; false                  ; String                                                                                                    ;
; c_cnt_prst0                          ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst0                   ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div1                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div1                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en1                     ; false                  ; String                                                                                                    ;
; c_cnt_in_src1                        ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en1               ; false                  ; String                                                                                                    ;
; c_cnt_prst1                          ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst1                   ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div2                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div2                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en2                     ; false                  ; String                                                                                                    ;
; c_cnt_in_src2                        ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en2               ; false                  ; String                                                                                                    ;
; c_cnt_prst2                          ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst2                   ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div3                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div3                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en3                     ; false                  ; String                                                                                                    ;
; c_cnt_in_src3                        ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en3               ; false                  ; String                                                                                                    ;
; c_cnt_prst3                          ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst3                   ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div4                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div4                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en4                     ; false                  ; String                                                                                                    ;
; c_cnt_in_src4                        ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en4               ; false                  ; String                                                                                                    ;
; c_cnt_prst4                          ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst4                   ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div5                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div5                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en5                     ; false                  ; String                                                                                                    ;
; c_cnt_in_src5                        ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en5               ; false                  ; String                                                                                                    ;
; c_cnt_prst5                          ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst5                   ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div6                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div6                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en6                     ; false                  ; String                                                                                                    ;
; c_cnt_in_src6                        ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en6               ; false                  ; String                                                                                                    ;
; c_cnt_prst6                          ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst6                   ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div7                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div7                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en7                     ; false                  ; String                                                                                                    ;
; c_cnt_in_src7                        ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en7               ; false                  ; String                                                                                                    ;
; c_cnt_prst7                          ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst7                   ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div8                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div8                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en8                     ; false                  ; String                                                                                                    ;
; c_cnt_in_src8                        ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en8               ; false                  ; String                                                                                                    ;
; c_cnt_prst8                          ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst8                   ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div9                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div9                        ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en9                     ; false                  ; String                                                                                                    ;
; c_cnt_in_src9                        ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en9               ; false                  ; String                                                                                                    ;
; c_cnt_prst9                          ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst9                   ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div10                       ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div10                       ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en10                    ; false                  ; String                                                                                                    ;
; c_cnt_in_src10                       ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en10              ; false                  ; String                                                                                                    ;
; c_cnt_prst10                         ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst10                  ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div11                       ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div11                       ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en11                    ; false                  ; String                                                                                                    ;
; c_cnt_in_src11                       ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en11              ; false                  ; String                                                                                                    ;
; c_cnt_prst11                         ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst11                  ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div12                       ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div12                       ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en12                    ; false                  ; String                                                                                                    ;
; c_cnt_in_src12                       ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en12              ; false                  ; String                                                                                                    ;
; c_cnt_prst12                         ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst12                  ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div13                       ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div13                       ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en13                    ; false                  ; String                                                                                                    ;
; c_cnt_in_src13                       ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en13              ; false                  ; String                                                                                                    ;
; c_cnt_prst13                         ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst13                  ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div14                       ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div14                       ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en14                    ; false                  ; String                                                                                                    ;
; c_cnt_in_src14                       ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en14              ; false                  ; String                                                                                                    ;
; c_cnt_prst14                         ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst14                  ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div15                       ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div15                       ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en15                    ; false                  ; String                                                                                                    ;
; c_cnt_in_src15                       ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en15              ; false                  ; String                                                                                                    ;
; c_cnt_prst15                         ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst15                  ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div16                       ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div16                       ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en16                    ; false                  ; String                                                                                                    ;
; c_cnt_in_src16                       ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en16              ; false                  ; String                                                                                                    ;
; c_cnt_prst16                         ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst16                  ; 0                      ; Signed Integer                                                                                            ;
; c_cnt_hi_div17                       ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_lo_div17                       ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_bypass_en17                    ; false                  ; String                                                                                                    ;
; c_cnt_in_src17                       ; ph_mux_clk             ; String                                                                                                    ;
; c_cnt_odd_div_duty_en17              ; false                  ; String                                                                                                    ;
; c_cnt_prst17                         ; 1                      ; Signed Integer                                                                                            ;
; c_cnt_ph_mux_prst17                  ; 0                      ; Signed Integer                                                                                            ;
; pll_vco_div                          ; 1                      ; Signed Integer                                                                                            ;
; pll_slf_rst                          ; false                  ; String                                                                                                    ;
; pll_bw_sel                           ; low                    ; String                                                                                                    ;
; pll_output_clk_frequency             ; 0 MHz                  ; String                                                                                                    ;
; pll_cp_current                       ; 0                      ; Signed Integer                                                                                            ;
; pll_bwctrl                           ; 0                      ; Signed Integer                                                                                            ;
; pll_fractional_division              ; 1                      ; Signed Integer                                                                                            ;
; pll_fractional_cout                  ; 24                     ; Signed Integer                                                                                            ;
; pll_dsm_out_sel                      ; 1st_order              ; String                                                                                                    ;
; mimic_fbclk_type                     ; gclk                   ; String                                                                                                    ;
; pll_fbclk_mux_1                      ; glb                    ; String                                                                                                    ;
; pll_fbclk_mux_2                      ; fb_1                   ; String                                                                                                    ;
; pll_m_cnt_in_src                     ; ph_mux_clk             ; String                                                                                                    ;
; pll_vcoph_div                        ; 1                      ; Signed Integer                                                                                            ;
; refclk1_frequency                    ; 0 MHz                  ; String                                                                                                    ;
; pll_clkin_0_src                      ; clk_0                  ; String                                                                                                    ;
; pll_clkin_1_src                      ; clk_0                  ; String                                                                                                    ;
; pll_clk_loss_sw_en                   ; false                  ; String                                                                                                    ;
; pll_auto_clk_sw_en                   ; false                  ; String                                                                                                    ;
; pll_manu_clk_sw_en                   ; false                  ; String                                                                                                    ;
; pll_clk_sw_dly                       ; 0                      ; Signed Integer                                                                                            ;
; pll_extclk_0_cnt_src                 ; pll_extclk_cnt_src_vss ; String                                                                                                    ;
; pll_extclk_1_cnt_src                 ; pll_extclk_cnt_src_vss ; String                                                                                                    ;
+--------------------------------------+------------------------+-----------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_data_master_translator ;
+-----------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name              ; Value ; Type                                                                                                                                                                                       ;
+-----------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                ; 20    ; Signed Integer                                                                                                                                                                             ;
; AV_DATA_W                   ; 32    ; Signed Integer                                                                                                                                                                             ;
; AV_BURSTCOUNT_W             ; 1     ; Signed Integer                                                                                                                                                                             ;
; AV_BYTEENABLE_W             ; 4     ; Signed Integer                                                                                                                                                                             ;
; UAV_ADDRESS_W               ; 20    ; Signed Integer                                                                                                                                                                             ;
; UAV_BURSTCOUNT_W            ; 3     ; Signed Integer                                                                                                                                                                             ;
; USE_BURSTCOUNT              ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_BEGINBURSTTRANSFER      ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_BEGINTRANSFER           ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_CHIPSELECT              ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_READ                    ; 1     ; Signed Integer                                                                                                                                                                             ;
; USE_READDATAVALID           ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_WRITE                   ; 1     ; Signed Integer                                                                                                                                                                             ;
; USE_WAITREQUEST             ; 1     ; Signed Integer                                                                                                                                                                             ;
; USE_WRITERESPONSE           ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_READRESPONSE            ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_REGISTERINCOMINGSIGNALS  ; 1     ; Signed Integer                                                                                                                                                                             ;
; AV_SYMBOLS_PER_WORD         ; 4     ; Signed Integer                                                                                                                                                                             ;
; AV_ADDRESS_SYMBOLS          ; 1     ; Signed Integer                                                                                                                                                                             ;
; AV_CONSTANT_BURST_BEHAVIOR  ; 0     ; Signed Integer                                                                                                                                                                             ;
; UAV_CONSTANT_BURST_BEHAVIOR ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_BURSTCOUNT_SYMBOLS       ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_LINEWRAPBURSTS           ; 0     ; Signed Integer                                                                                                                                                                             ;
+-----------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_instruction_master_translator ;
+-----------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name              ; Value ; Type                                                                                                                                                                                              ;
+-----------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                ; 19    ; Signed Integer                                                                                                                                                                                    ;
; AV_DATA_W                   ; 32    ; Signed Integer                                                                                                                                                                                    ;
; AV_BURSTCOUNT_W             ; 1     ; Signed Integer                                                                                                                                                                                    ;
; AV_BYTEENABLE_W             ; 4     ; Signed Integer                                                                                                                                                                                    ;
; UAV_ADDRESS_W               ; 20    ; Signed Integer                                                                                                                                                                                    ;
; UAV_BURSTCOUNT_W            ; 3     ; Signed Integer                                                                                                                                                                                    ;
; USE_BURSTCOUNT              ; 0     ; Signed Integer                                                                                                                                                                                    ;
; USE_BEGINBURSTTRANSFER      ; 0     ; Signed Integer                                                                                                                                                                                    ;
; USE_BEGINTRANSFER           ; 0     ; Signed Integer                                                                                                                                                                                    ;
; USE_CHIPSELECT              ; 0     ; Signed Integer                                                                                                                                                                                    ;
; USE_READ                    ; 1     ; Signed Integer                                                                                                                                                                                    ;
; USE_READDATAVALID           ; 0     ; Signed Integer                                                                                                                                                                                    ;
; USE_WRITE                   ; 0     ; Signed Integer                                                                                                                                                                                    ;
; USE_WAITREQUEST             ; 1     ; Signed Integer                                                                                                                                                                                    ;
; USE_WRITERESPONSE           ; 0     ; Signed Integer                                                                                                                                                                                    ;
; USE_READRESPONSE            ; 0     ; Signed Integer                                                                                                                                                                                    ;
; AV_REGISTERINCOMINGSIGNALS  ; 0     ; Signed Integer                                                                                                                                                                                    ;
; AV_SYMBOLS_PER_WORD         ; 4     ; Signed Integer                                                                                                                                                                                    ;
; AV_ADDRESS_SYMBOLS          ; 1     ; Signed Integer                                                                                                                                                                                    ;
; AV_CONSTANT_BURST_BEHAVIOR  ; 0     ; Signed Integer                                                                                                                                                                                    ;
; UAV_CONSTANT_BURST_BEHAVIOR ; 0     ; Signed Integer                                                                                                                                                                                    ;
; AV_BURSTCOUNT_SYMBOLS       ; 0     ; Signed Integer                                                                                                                                                                                    ;
; AV_LINEWRAPBURSTS           ; 1     ; Signed Integer                                                                                                                                                                                    ;
+-----------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                               ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 1     ; Signed Integer                                                                                                                                                                                     ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                     ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                     ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                                     ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                     ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                     ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                     ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                     ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                     ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                     ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                     ;
; USE_WAITREQUEST                ; 1     ; Signed Integer                                                                                                                                                                                     ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                     ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                     ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                     ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                     ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                     ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                     ;
; UAV_ADDRESS_W                  ; 20    ; Signed Integer                                                                                                                                                                                     ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                     ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                     ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                     ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                     ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                     ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                     ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                     ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:eth_tse_mac_control_port_translator ;
+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                          ;
+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 8     ; Signed Integer                                                                                                                                                                                ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                ;
; AV_BYTEENABLE_W                ; 4     ; Signed Integer                                                                                                                                                                                ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                ;
; AV_WRITE_WAIT_CYCLES           ; 1     ; Signed Integer                                                                                                                                                                                ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                ;
; USE_WAITREQUEST                ; 1     ; Signed Integer                                                                                                                                                                                ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                ;
; UAV_ADDRESS_W                  ; 20    ; Signed Integer                                                                                                                                                                                ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                ;
+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_csr_translator ;
+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                    ;
+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 3     ; Signed Integer                                                                                                                                                                          ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                          ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                          ;
; AV_BYTEENABLE_W                ; 4     ; Signed Integer                                                                                                                                                                          ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                          ;
; AV_READLATENCY                 ; 1     ; Signed Integer                                                                                                                                                                          ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                          ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                          ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                          ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                          ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                          ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                          ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                          ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                          ;
; UAV_ADDRESS_W                  ; 20    ; Signed Integer                                                                                                                                                                          ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                          ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                          ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                          ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                          ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                          ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                          ;
+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:nios2_debug_mem_slave_translator ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                       ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 9     ; Signed Integer                                                                                                                                                                             ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                             ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                             ;
; AV_BYTEENABLE_W                ; 4     ; Signed Integer                                                                                                                                                                             ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                             ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                             ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_WAITREQUEST                ; 1     ; Signed Integer                                                                                                                                                                             ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                             ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                             ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                             ;
; UAV_ADDRESS_W                  ; 20    ; Signed Integer                                                                                                                                                                             ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                             ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                             ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                             ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                             ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                             ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator ;
+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                                 ;
+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 1     ; Signed Integer                                                                                                                                                                                       ;
; AV_DATA_W                      ; 128   ; Signed Integer                                                                                                                                                                                       ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                       ;
; AV_BYTEENABLE_W                ; 16    ; Signed Integer                                                                                                                                                                                       ;
; UAV_BYTEENABLE_W               ; 16    ; Signed Integer                                                                                                                                                                                       ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                       ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                                       ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                       ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                       ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                       ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                                       ;
; USE_WAITREQUEST                ; 1     ; Signed Integer                                                                                                                                                                                       ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                       ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                       ;
; AV_SYMBOLS_PER_WORD            ; 16    ; Signed Integer                                                                                                                                                                                       ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                                       ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                       ;
; BITS_PER_WORD                  ; 4     ; Signed Integer                                                                                                                                                                                       ;
; UAV_ADDRESS_W                  ; 20    ; Signed Integer                                                                                                                                                                                       ;
; UAV_BURSTCOUNT_W               ; 5     ; Signed Integer                                                                                                                                                                                       ;
; UAV_DATA_W                     ; 128   ; Signed Integer                                                                                                                                                                                       ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                       ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                       ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                       ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                       ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                       ;
+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fabric_if_if_bridge_slave_translator ;
+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                           ;
+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 8     ; Signed Integer                                                                                                                                                                                 ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                                 ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                                 ;
; AV_BYTEENABLE_W                ; 4     ; Signed Integer                                                                                                                                                                                 ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                                 ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                                 ;
; AV_READ_WAIT_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                 ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                 ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                                 ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                                 ;
; USE_READDATAVALID              ; 1     ; Signed Integer                                                                                                                                                                                 ;
; USE_WAITREQUEST                ; 1     ; Signed Integer                                                                                                                                                                                 ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                                 ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                                 ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                                 ;
; AV_ADDRESS_SYMBOLS             ; 1     ; Signed Integer                                                                                                                                                                                 ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                                 ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                                 ;
; UAV_ADDRESS_W                  ; 20    ; Signed Integer                                                                                                                                                                                 ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                                 ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                                 ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                                 ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                                 ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                                 ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                                 ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                                 ;
+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator ;
+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                ;
+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 1     ; Signed Integer                                                                                                                                                                      ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                      ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                      ;
; AV_BYTEENABLE_W                ; 4     ; Signed Integer                                                                                                                                                                      ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                      ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                      ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                      ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                      ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                      ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                      ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                      ;
; USE_WAITREQUEST                ; 1     ; Signed Integer                                                                                                                                                                      ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                      ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                      ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                      ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                      ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                      ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                      ;
; UAV_ADDRESS_W                  ; 20    ; Signed Integer                                                                                                                                                                      ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                      ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                      ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                      ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                      ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                      ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                      ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                      ;
+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator ;
+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                    ;
+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 3     ; Signed Integer                                                                                                                                                                          ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                          ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                          ;
; AV_BYTEENABLE_W                ; 4     ; Signed Integer                                                                                                                                                                          ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                          ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                          ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                          ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                          ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                          ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                          ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                          ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                          ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                          ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                          ;
; UAV_ADDRESS_W                  ; 20    ; Signed Integer                                                                                                                                                                          ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                          ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                          ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                          ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                          ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                          ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                          ;
+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_response_translator ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                         ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 1     ; Signed Integer                                                                                                                                                                               ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                               ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                               ;
; AV_BYTEENABLE_W                ; 4     ; Signed Integer                                                                                                                                                                               ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                               ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                               ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                               ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                               ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                               ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                               ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                               ;
; USE_WAITREQUEST                ; 1     ; Signed Integer                                                                                                                                                                               ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                               ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                               ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                               ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                               ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                               ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                               ;
; UAV_ADDRESS_W                  ; 20    ; Signed Integer                                                                                                                                                                               ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                               ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                               ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                               ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                               ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                               ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                               ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                               ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:onchip_mem_s1_translator ;
+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                               ;
+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 15    ; Signed Integer                                                                                                                                                                     ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                     ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                     ;
; AV_BYTEENABLE_W                ; 4     ; Signed Integer                                                                                                                                                                     ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                     ;
; AV_READLATENCY                 ; 1     ; Signed Integer                                                                                                                                                                     ;
; AV_READ_WAIT_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                     ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                     ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                     ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                     ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                     ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                     ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                     ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                     ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                     ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                     ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                     ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                     ;
; UAV_ADDRESS_W                  ; 20    ; Signed Integer                                                                                                                                                                     ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                     ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                     ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                     ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                     ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                     ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                     ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                     ;
+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_tx_dpram_s1_translator ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                       ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 9     ; Signed Integer                                                                                                                                                                             ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                             ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                             ;
; AV_BYTEENABLE_W                ; 4     ; Signed Integer                                                                                                                                                                             ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                             ;
; AV_READLATENCY                 ; 1     ; Signed Integer                                                                                                                                                                             ;
; AV_READ_WAIT_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                             ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                             ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                             ;
; UAV_ADDRESS_W                  ; 20    ; Signed Integer                                                                                                                                                                             ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                             ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                             ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                             ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                             ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                             ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_ctrl_s1_translator ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                            ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                  ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                  ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                  ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                  ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                  ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                  ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                  ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                  ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                  ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                  ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                  ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                  ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                  ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                  ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                  ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                  ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                  ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                  ;
; UAV_ADDRESS_W                  ; 20    ; Signed Integer                                                                                                                                                                  ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                  ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                  ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                  ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                  ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                  ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                  ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                  ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator ;
+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                              ;
+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                                                                                    ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                    ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                    ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                                                                                    ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                    ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                                                                                    ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                                                                                    ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                    ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                    ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                    ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                    ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                    ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                    ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                    ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                    ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                    ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                    ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                    ;
; UAV_ADDRESS_W                  ; 20    ; Signed Integer                                                                                                                                                                    ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                    ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                    ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                    ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                    ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                    ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                    ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                    ;
+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_rx_dpram_s1_translator ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                       ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 9     ; Signed Integer                                                                                                                                                                             ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                             ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                             ;
; AV_BYTEENABLE_W                ; 4     ; Signed Integer                                                                                                                                                                             ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                             ;
; AV_READLATENCY                 ; 1     ; Signed Integer                                                                                                                                                                             ;
; AV_READ_WAIT_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                             ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                             ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                             ;
; UAV_ADDRESS_W                  ; 20    ; Signed Integer                                                                                                                                                                             ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                             ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                             ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                             ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                             ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                             ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_data_master_agent ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                               ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_QOS_H                 ; 78    ; Signed Integer                                                                                                                                                                     ;
; PKT_QOS_L                 ; 78    ; Signed Integer                                                                                                                                                                     ;
; PKT_DATA_SIDEBAND_H       ; 76    ; Signed Integer                                                                                                                                                                     ;
; PKT_DATA_SIDEBAND_L       ; 76    ; Signed Integer                                                                                                                                                                     ;
; PKT_ADDR_SIDEBAND_H       ; 75    ; Signed Integer                                                                                                                                                                     ;
; PKT_ADDR_SIDEBAND_L       ; 75    ; Signed Integer                                                                                                                                                                     ;
; PKT_CACHE_H               ; 94    ; Signed Integer                                                                                                                                                                     ;
; PKT_CACHE_L               ; 91    ; Signed Integer                                                                                                                                                                     ;
; PKT_THREAD_ID_H           ; 87    ; Signed Integer                                                                                                                                                                     ;
; PKT_THREAD_ID_L           ; 87    ; Signed Integer                                                                                                                                                                     ;
; PKT_BEGIN_BURST           ; 77    ; Signed Integer                                                                                                                                                                     ;
; PKT_PROTECTION_H          ; 90    ; Signed Integer                                                                                                                                                                     ;
; PKT_PROTECTION_L          ; 88    ; Signed Integer                                                                                                                                                                     ;
; PKT_BURSTWRAP_H           ; 69    ; Signed Integer                                                                                                                                                                     ;
; PKT_BURSTWRAP_L           ; 67    ; Signed Integer                                                                                                                                                                     ;
; PKT_BYTE_CNT_H            ; 66    ; Signed Integer                                                                                                                                                                     ;
; PKT_BYTE_CNT_L            ; 62    ; Signed Integer                                                                                                                                                                     ;
; PKT_ADDR_H                ; 55    ; Signed Integer                                                                                                                                                                     ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                     ;
; PKT_BURST_SIZE_H          ; 72    ; Signed Integer                                                                                                                                                                     ;
; PKT_BURST_SIZE_L          ; 70    ; Signed Integer                                                                                                                                                                     ;
; PKT_BURST_TYPE_H          ; 74    ; Signed Integer                                                                                                                                                                     ;
; PKT_BURST_TYPE_L          ; 73    ; Signed Integer                                                                                                                                                                     ;
; PKT_TRANS_EXCLUSIVE       ; 61    ; Signed Integer                                                                                                                                                                     ;
; PKT_TRANS_LOCK            ; 60    ; Signed Integer                                                                                                                                                                     ;
; PKT_TRANS_COMPRESSED_READ ; 56    ; Signed Integer                                                                                                                                                                     ;
; PKT_TRANS_POSTED          ; 57    ; Signed Integer                                                                                                                                                                     ;
; PKT_TRANS_WRITE           ; 58    ; Signed Integer                                                                                                                                                                     ;
; PKT_TRANS_READ            ; 59    ; Signed Integer                                                                                                                                                                     ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                     ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                     ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                     ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                     ;
; PKT_SRC_ID_H              ; 82    ; Signed Integer                                                                                                                                                                     ;
; PKT_SRC_ID_L              ; 79    ; Signed Integer                                                                                                                                                                     ;
; PKT_DEST_ID_H             ; 86    ; Signed Integer                                                                                                                                                                     ;
; PKT_DEST_ID_L             ; 83    ; Signed Integer                                                                                                                                                                     ;
; PKT_RESPONSE_STATUS_L     ; 95    ; Signed Integer                                                                                                                                                                     ;
; PKT_RESPONSE_STATUS_H     ; 96    ; Signed Integer                                                                                                                                                                     ;
; PKT_ORI_BURST_SIZE_L      ; 97    ; Signed Integer                                                                                                                                                                     ;
; PKT_ORI_BURST_SIZE_H      ; 99    ; Signed Integer                                                                                                                                                                     ;
; ST_DATA_W                 ; 100   ; Signed Integer                                                                                                                                                                     ;
; ST_CHANNEL_W              ; 14    ; Signed Integer                                                                                                                                                                     ;
; AV_BURSTCOUNT_W           ; 3     ; Signed Integer                                                                                                                                                                     ;
; ID                        ; 0     ; Signed Integer                                                                                                                                                                     ;
; SUPPRESS_0_BYTEEN_RSP     ; 1     ; Signed Integer                                                                                                                                                                     ;
; BURSTWRAP_VALUE           ; 7     ; Signed Integer                                                                                                                                                                     ;
; CACHE_VALUE               ; 0     ; Signed Integer                                                                                                                                                                     ;
; SECURE_ACCESS_BIT         ; 1     ; Signed Integer                                                                                                                                                                     ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                     ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                     ;
; PKT_BURSTWRAP_W           ; 3     ; Signed Integer                                                                                                                                                                     ;
; PKT_BYTE_CNT_W            ; 5     ; Signed Integer                                                                                                                                                                     ;
; PKT_PROTECTION_W          ; 3     ; Signed Integer                                                                                                                                                                     ;
; PKT_ADDR_W                ; 20    ; Signed Integer                                                                                                                                                                     ;
; PKT_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                     ;
; PKT_BYTEEN_W              ; 4     ; Signed Integer                                                                                                                                                                     ;
; PKT_SRC_ID_W              ; 4     ; Signed Integer                                                                                                                                                                     ;
; PKT_DEST_ID_W             ; 4     ; Signed Integer                                                                                                                                                                     ;
; PKT_BURST_SIZE_W          ; 3     ; Signed Integer                                                                                                                                                                     ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_instruction_master_agent ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                      ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_QOS_H                 ; 78    ; Signed Integer                                                                                                                                                                            ;
; PKT_QOS_L                 ; 78    ; Signed Integer                                                                                                                                                                            ;
; PKT_DATA_SIDEBAND_H       ; 76    ; Signed Integer                                                                                                                                                                            ;
; PKT_DATA_SIDEBAND_L       ; 76    ; Signed Integer                                                                                                                                                                            ;
; PKT_ADDR_SIDEBAND_H       ; 75    ; Signed Integer                                                                                                                                                                            ;
; PKT_ADDR_SIDEBAND_L       ; 75    ; Signed Integer                                                                                                                                                                            ;
; PKT_CACHE_H               ; 94    ; Signed Integer                                                                                                                                                                            ;
; PKT_CACHE_L               ; 91    ; Signed Integer                                                                                                                                                                            ;
; PKT_THREAD_ID_H           ; 87    ; Signed Integer                                                                                                                                                                            ;
; PKT_THREAD_ID_L           ; 87    ; Signed Integer                                                                                                                                                                            ;
; PKT_BEGIN_BURST           ; 77    ; Signed Integer                                                                                                                                                                            ;
; PKT_PROTECTION_H          ; 90    ; Signed Integer                                                                                                                                                                            ;
; PKT_PROTECTION_L          ; 88    ; Signed Integer                                                                                                                                                                            ;
; PKT_BURSTWRAP_H           ; 69    ; Signed Integer                                                                                                                                                                            ;
; PKT_BURSTWRAP_L           ; 67    ; Signed Integer                                                                                                                                                                            ;
; PKT_BYTE_CNT_H            ; 66    ; Signed Integer                                                                                                                                                                            ;
; PKT_BYTE_CNT_L            ; 62    ; Signed Integer                                                                                                                                                                            ;
; PKT_ADDR_H                ; 55    ; Signed Integer                                                                                                                                                                            ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                            ;
; PKT_BURST_SIZE_H          ; 72    ; Signed Integer                                                                                                                                                                            ;
; PKT_BURST_SIZE_L          ; 70    ; Signed Integer                                                                                                                                                                            ;
; PKT_BURST_TYPE_H          ; 74    ; Signed Integer                                                                                                                                                                            ;
; PKT_BURST_TYPE_L          ; 73    ; Signed Integer                                                                                                                                                                            ;
; PKT_TRANS_EXCLUSIVE       ; 61    ; Signed Integer                                                                                                                                                                            ;
; PKT_TRANS_LOCK            ; 60    ; Signed Integer                                                                                                                                                                            ;
; PKT_TRANS_COMPRESSED_READ ; 56    ; Signed Integer                                                                                                                                                                            ;
; PKT_TRANS_POSTED          ; 57    ; Signed Integer                                                                                                                                                                            ;
; PKT_TRANS_WRITE           ; 58    ; Signed Integer                                                                                                                                                                            ;
; PKT_TRANS_READ            ; 59    ; Signed Integer                                                                                                                                                                            ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                            ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                            ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                            ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                            ;
; PKT_SRC_ID_H              ; 82    ; Signed Integer                                                                                                                                                                            ;
; PKT_SRC_ID_L              ; 79    ; Signed Integer                                                                                                                                                                            ;
; PKT_DEST_ID_H             ; 86    ; Signed Integer                                                                                                                                                                            ;
; PKT_DEST_ID_L             ; 83    ; Signed Integer                                                                                                                                                                            ;
; PKT_RESPONSE_STATUS_L     ; 95    ; Signed Integer                                                                                                                                                                            ;
; PKT_RESPONSE_STATUS_H     ; 96    ; Signed Integer                                                                                                                                                                            ;
; PKT_ORI_BURST_SIZE_L      ; 97    ; Signed Integer                                                                                                                                                                            ;
; PKT_ORI_BURST_SIZE_H      ; 99    ; Signed Integer                                                                                                                                                                            ;
; ST_DATA_W                 ; 100   ; Signed Integer                                                                                                                                                                            ;
; ST_CHANNEL_W              ; 14    ; Signed Integer                                                                                                                                                                            ;
; AV_BURSTCOUNT_W           ; 3     ; Signed Integer                                                                                                                                                                            ;
; ID                        ; 1     ; Signed Integer                                                                                                                                                                            ;
; SUPPRESS_0_BYTEEN_RSP     ; 1     ; Signed Integer                                                                                                                                                                            ;
; BURSTWRAP_VALUE           ; 3     ; Signed Integer                                                                                                                                                                            ;
; CACHE_VALUE               ; 0     ; Signed Integer                                                                                                                                                                            ;
; SECURE_ACCESS_BIT         ; 1     ; Signed Integer                                                                                                                                                                            ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                            ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                            ;
; PKT_BURSTWRAP_W           ; 3     ; Signed Integer                                                                                                                                                                            ;
; PKT_BYTE_CNT_W            ; 5     ; Signed Integer                                                                                                                                                                            ;
; PKT_PROTECTION_W          ; 3     ; Signed Integer                                                                                                                                                                            ;
; PKT_ADDR_W                ; 20    ; Signed Integer                                                                                                                                                                            ;
; PKT_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                            ;
; PKT_BYTEEN_W              ; 4     ; Signed Integer                                                                                                                                                                            ;
; PKT_SRC_ID_W              ; 4     ; Signed Integer                                                                                                                                                                            ;
; PKT_DEST_ID_W             ; 4     ; Signed Integer                                                                                                                                                                            ;
; PKT_BURST_SIZE_W          ; 3     ; Signed Integer                                                                                                                                                                            ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                          ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 77    ; Signed Integer                                                                                                                                                                                ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                ;
; PKT_ADDR_H                ; 55    ; Signed Integer                                                                                                                                                                                ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                ;
; PKT_TRANS_LOCK            ; 60    ; Signed Integer                                                                                                                                                                                ;
; PKT_TRANS_COMPRESSED_READ ; 56    ; Signed Integer                                                                                                                                                                                ;
; PKT_TRANS_POSTED          ; 57    ; Signed Integer                                                                                                                                                                                ;
; PKT_TRANS_WRITE           ; 58    ; Signed Integer                                                                                                                                                                                ;
; PKT_TRANS_READ            ; 59    ; Signed Integer                                                                                                                                                                                ;
; PKT_SRC_ID_H              ; 82    ; Signed Integer                                                                                                                                                                                ;
; PKT_SRC_ID_L              ; 79    ; Signed Integer                                                                                                                                                                                ;
; PKT_DEST_ID_H             ; 86    ; Signed Integer                                                                                                                                                                                ;
; PKT_DEST_ID_L             ; 83    ; Signed Integer                                                                                                                                                                                ;
; PKT_BURSTWRAP_H           ; 69    ; Signed Integer                                                                                                                                                                                ;
; PKT_BURSTWRAP_L           ; 67    ; Signed Integer                                                                                                                                                                                ;
; PKT_BYTE_CNT_H            ; 66    ; Signed Integer                                                                                                                                                                                ;
; PKT_BYTE_CNT_L            ; 62    ; Signed Integer                                                                                                                                                                                ;
; PKT_PROTECTION_H          ; 90    ; Signed Integer                                                                                                                                                                                ;
; PKT_PROTECTION_L          ; 88    ; Signed Integer                                                                                                                                                                                ;
; PKT_RESPONSE_STATUS_H     ; 96    ; Signed Integer                                                                                                                                                                                ;
; PKT_RESPONSE_STATUS_L     ; 95    ; Signed Integer                                                                                                                                                                                ;
; PKT_BURST_SIZE_H          ; 72    ; Signed Integer                                                                                                                                                                                ;
; PKT_BURST_SIZE_L          ; 70    ; Signed Integer                                                                                                                                                                                ;
; PKT_ORI_BURST_SIZE_L      ; 97    ; Signed Integer                                                                                                                                                                                ;
; PKT_ORI_BURST_SIZE_H      ; 99    ; Signed Integer                                                                                                                                                                                ;
; ST_DATA_W                 ; 100   ; Signed Integer                                                                                                                                                                                ;
; ST_CHANNEL_W              ; 14    ; Signed Integer                                                                                                                                                                                ;
; ADDR_W                    ; 20    ; Signed Integer                                                                                                                                                                                ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                                ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                                ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                                ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                                ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                ;
; FIFO_DATA_W               ; 101   ; Signed Integer                                                                                                                                                                                ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                   ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 20    ; Signed Integer                                                                                                                                                                                                                                         ;
; BURSTWRAP_W    ; 3     ; Signed Integer                                                                                                                                                                                                                                         ;
; BYTE_CNT_W     ; 5     ; Signed Integer                                                                                                                                                                                                                                         ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                         ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                         ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                     ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                           ;
; BITS_PER_SYMBOL     ; 101   ; Signed Integer                                                                                                                                                                                           ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                           ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                           ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                           ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                           ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                           ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                           ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                           ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                           ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                           ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                           ;
; DATA_WIDTH          ; 101   ; Signed Integer                                                                                                                                                                                           ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                           ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:eth_tse_mac_control_port_agent ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                     ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 77    ; Signed Integer                                                                                                                                                                           ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                           ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                           ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                           ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                           ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                           ;
; PKT_ADDR_H                ; 55    ; Signed Integer                                                                                                                                                                           ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                           ;
; PKT_TRANS_LOCK            ; 60    ; Signed Integer                                                                                                                                                                           ;
; PKT_TRANS_COMPRESSED_READ ; 56    ; Signed Integer                                                                                                                                                                           ;
; PKT_TRANS_POSTED          ; 57    ; Signed Integer                                                                                                                                                                           ;
; PKT_TRANS_WRITE           ; 58    ; Signed Integer                                                                                                                                                                           ;
; PKT_TRANS_READ            ; 59    ; Signed Integer                                                                                                                                                                           ;
; PKT_SRC_ID_H              ; 82    ; Signed Integer                                                                                                                                                                           ;
; PKT_SRC_ID_L              ; 79    ; Signed Integer                                                                                                                                                                           ;
; PKT_DEST_ID_H             ; 86    ; Signed Integer                                                                                                                                                                           ;
; PKT_DEST_ID_L             ; 83    ; Signed Integer                                                                                                                                                                           ;
; PKT_BURSTWRAP_H           ; 69    ; Signed Integer                                                                                                                                                                           ;
; PKT_BURSTWRAP_L           ; 67    ; Signed Integer                                                                                                                                                                           ;
; PKT_BYTE_CNT_H            ; 66    ; Signed Integer                                                                                                                                                                           ;
; PKT_BYTE_CNT_L            ; 62    ; Signed Integer                                                                                                                                                                           ;
; PKT_PROTECTION_H          ; 90    ; Signed Integer                                                                                                                                                                           ;
; PKT_PROTECTION_L          ; 88    ; Signed Integer                                                                                                                                                                           ;
; PKT_RESPONSE_STATUS_H     ; 96    ; Signed Integer                                                                                                                                                                           ;
; PKT_RESPONSE_STATUS_L     ; 95    ; Signed Integer                                                                                                                                                                           ;
; PKT_BURST_SIZE_H          ; 72    ; Signed Integer                                                                                                                                                                           ;
; PKT_BURST_SIZE_L          ; 70    ; Signed Integer                                                                                                                                                                           ;
; PKT_ORI_BURST_SIZE_L      ; 97    ; Signed Integer                                                                                                                                                                           ;
; PKT_ORI_BURST_SIZE_H      ; 99    ; Signed Integer                                                                                                                                                                           ;
; ST_DATA_W                 ; 100   ; Signed Integer                                                                                                                                                                           ;
; ST_CHANNEL_W              ; 14    ; Signed Integer                                                                                                                                                                           ;
; ADDR_W                    ; 20    ; Signed Integer                                                                                                                                                                           ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                           ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                           ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                           ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                           ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                           ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                           ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                           ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                           ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                           ;
; FIFO_DATA_W               ; 101   ; Signed Integer                                                                                                                                                                           ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                           ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:eth_tse_mac_control_port_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                              ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 20    ; Signed Integer                                                                                                                                                                                                                                    ;
; BURSTWRAP_W    ; 3     ; Signed Integer                                                                                                                                                                                                                                    ;
; BYTE_CNT_W     ; 5     ; Signed Integer                                                                                                                                                                                                                                    ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                    ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                    ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                      ;
; BITS_PER_SYMBOL     ; 101   ; Signed Integer                                                                                                                                                                                      ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                      ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                      ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                      ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                      ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                      ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                      ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                      ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                      ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                      ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                      ;
; DATA_WIDTH          ; 101   ; Signed Integer                                                                                                                                                                                      ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                      ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_csr_agent ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                               ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 77    ; Signed Integer                                                                                                                                                                     ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                     ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                     ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                     ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                     ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                     ;
; PKT_ADDR_H                ; 55    ; Signed Integer                                                                                                                                                                     ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                     ;
; PKT_TRANS_LOCK            ; 60    ; Signed Integer                                                                                                                                                                     ;
; PKT_TRANS_COMPRESSED_READ ; 56    ; Signed Integer                                                                                                                                                                     ;
; PKT_TRANS_POSTED          ; 57    ; Signed Integer                                                                                                                                                                     ;
; PKT_TRANS_WRITE           ; 58    ; Signed Integer                                                                                                                                                                     ;
; PKT_TRANS_READ            ; 59    ; Signed Integer                                                                                                                                                                     ;
; PKT_SRC_ID_H              ; 82    ; Signed Integer                                                                                                                                                                     ;
; PKT_SRC_ID_L              ; 79    ; Signed Integer                                                                                                                                                                     ;
; PKT_DEST_ID_H             ; 86    ; Signed Integer                                                                                                                                                                     ;
; PKT_DEST_ID_L             ; 83    ; Signed Integer                                                                                                                                                                     ;
; PKT_BURSTWRAP_H           ; 69    ; Signed Integer                                                                                                                                                                     ;
; PKT_BURSTWRAP_L           ; 67    ; Signed Integer                                                                                                                                                                     ;
; PKT_BYTE_CNT_H            ; 66    ; Signed Integer                                                                                                                                                                     ;
; PKT_BYTE_CNT_L            ; 62    ; Signed Integer                                                                                                                                                                     ;
; PKT_PROTECTION_H          ; 90    ; Signed Integer                                                                                                                                                                     ;
; PKT_PROTECTION_L          ; 88    ; Signed Integer                                                                                                                                                                     ;
; PKT_RESPONSE_STATUS_H     ; 96    ; Signed Integer                                                                                                                                                                     ;
; PKT_RESPONSE_STATUS_L     ; 95    ; Signed Integer                                                                                                                                                                     ;
; PKT_BURST_SIZE_H          ; 72    ; Signed Integer                                                                                                                                                                     ;
; PKT_BURST_SIZE_L          ; 70    ; Signed Integer                                                                                                                                                                     ;
; PKT_ORI_BURST_SIZE_L      ; 97    ; Signed Integer                                                                                                                                                                     ;
; PKT_ORI_BURST_SIZE_H      ; 99    ; Signed Integer                                                                                                                                                                     ;
; ST_DATA_W                 ; 100   ; Signed Integer                                                                                                                                                                     ;
; ST_CHANNEL_W              ; 14    ; Signed Integer                                                                                                                                                                     ;
; ADDR_W                    ; 20    ; Signed Integer                                                                                                                                                                     ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                     ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                     ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                     ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                     ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                     ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                     ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                     ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                     ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                     ;
; FIFO_DATA_W               ; 101   ; Signed Integer                                                                                                                                                                     ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                     ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_csr_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                        ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 20    ; Signed Integer                                                                                                                                                                                                                              ;
; BURSTWRAP_W    ; 3     ; Signed Integer                                                                                                                                                                                                                              ;
; BYTE_CNT_W     ; 5     ; Signed Integer                                                                                                                                                                                                                              ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                              ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                              ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                          ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                ;
; BITS_PER_SYMBOL     ; 101   ; Signed Integer                                                                                                                                                                                ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                ;
; DATA_WIDTH          ; 101   ; Signed Integer                                                                                                                                                                                ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:nios2_debug_mem_slave_agent ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                  ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 77    ; Signed Integer                                                                                                                                                                        ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                        ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                        ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                        ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                        ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                        ;
; PKT_ADDR_H                ; 55    ; Signed Integer                                                                                                                                                                        ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_LOCK            ; 60    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_COMPRESSED_READ ; 56    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_POSTED          ; 57    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_WRITE           ; 58    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_READ            ; 59    ; Signed Integer                                                                                                                                                                        ;
; PKT_SRC_ID_H              ; 82    ; Signed Integer                                                                                                                                                                        ;
; PKT_SRC_ID_L              ; 79    ; Signed Integer                                                                                                                                                                        ;
; PKT_DEST_ID_H             ; 86    ; Signed Integer                                                                                                                                                                        ;
; PKT_DEST_ID_L             ; 83    ; Signed Integer                                                                                                                                                                        ;
; PKT_BURSTWRAP_H           ; 69    ; Signed Integer                                                                                                                                                                        ;
; PKT_BURSTWRAP_L           ; 67    ; Signed Integer                                                                                                                                                                        ;
; PKT_BYTE_CNT_H            ; 66    ; Signed Integer                                                                                                                                                                        ;
; PKT_BYTE_CNT_L            ; 62    ; Signed Integer                                                                                                                                                                        ;
; PKT_PROTECTION_H          ; 90    ; Signed Integer                                                                                                                                                                        ;
; PKT_PROTECTION_L          ; 88    ; Signed Integer                                                                                                                                                                        ;
; PKT_RESPONSE_STATUS_H     ; 96    ; Signed Integer                                                                                                                                                                        ;
; PKT_RESPONSE_STATUS_L     ; 95    ; Signed Integer                                                                                                                                                                        ;
; PKT_BURST_SIZE_H          ; 72    ; Signed Integer                                                                                                                                                                        ;
; PKT_BURST_SIZE_L          ; 70    ; Signed Integer                                                                                                                                                                        ;
; PKT_ORI_BURST_SIZE_L      ; 97    ; Signed Integer                                                                                                                                                                        ;
; PKT_ORI_BURST_SIZE_H      ; 99    ; Signed Integer                                                                                                                                                                        ;
; ST_DATA_W                 ; 100   ; Signed Integer                                                                                                                                                                        ;
; ST_CHANNEL_W              ; 14    ; Signed Integer                                                                                                                                                                        ;
; ADDR_W                    ; 20    ; Signed Integer                                                                                                                                                                        ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                        ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                        ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                        ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                        ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                        ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                        ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                        ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                        ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                        ;
; FIFO_DATA_W               ; 101   ; Signed Integer                                                                                                                                                                        ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                        ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:nios2_debug_mem_slave_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                           ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 20    ; Signed Integer                                                                                                                                                                                                                                 ;
; BURSTWRAP_W    ; 3     ; Signed Integer                                                                                                                                                                                                                                 ;
; BYTE_CNT_W     ; 5     ; Signed Integer                                                                                                                                                                                                                                 ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                 ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                 ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                             ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                   ;
; BITS_PER_SYMBOL     ; 101   ; Signed Integer                                                                                                                                                                                   ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                   ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                   ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                   ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                   ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                   ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                   ;
; DATA_WIDTH          ; 101   ; Signed Integer                                                                                                                                                                                   ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                   ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_descriptor_slave_agent ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                            ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 185   ; Signed Integer                                                                                                                                                                                  ;
; PKT_DATA_H                ; 127   ; Signed Integer                                                                                                                                                                                  ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                  ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                                  ;
; PKT_BYTEEN_H              ; 143   ; Signed Integer                                                                                                                                                                                  ;
; PKT_BYTEEN_L              ; 128   ; Signed Integer                                                                                                                                                                                  ;
; PKT_ADDR_H                ; 163   ; Signed Integer                                                                                                                                                                                  ;
; PKT_ADDR_L                ; 144   ; Signed Integer                                                                                                                                                                                  ;
; PKT_TRANS_LOCK            ; 168   ; Signed Integer                                                                                                                                                                                  ;
; PKT_TRANS_COMPRESSED_READ ; 164   ; Signed Integer                                                                                                                                                                                  ;
; PKT_TRANS_POSTED          ; 165   ; Signed Integer                                                                                                                                                                                  ;
; PKT_TRANS_WRITE           ; 166   ; Signed Integer                                                                                                                                                                                  ;
; PKT_TRANS_READ            ; 167   ; Signed Integer                                                                                                                                                                                  ;
; PKT_SRC_ID_H              ; 190   ; Signed Integer                                                                                                                                                                                  ;
; PKT_SRC_ID_L              ; 187   ; Signed Integer                                                                                                                                                                                  ;
; PKT_DEST_ID_H             ; 194   ; Signed Integer                                                                                                                                                                                  ;
; PKT_DEST_ID_L             ; 191   ; Signed Integer                                                                                                                                                                                  ;
; PKT_BURSTWRAP_H           ; 177   ; Signed Integer                                                                                                                                                                                  ;
; PKT_BURSTWRAP_L           ; 175   ; Signed Integer                                                                                                                                                                                  ;
; PKT_BYTE_CNT_H            ; 174   ; Signed Integer                                                                                                                                                                                  ;
; PKT_BYTE_CNT_L            ; 170   ; Signed Integer                                                                                                                                                                                  ;
; PKT_PROTECTION_H          ; 198   ; Signed Integer                                                                                                                                                                                  ;
; PKT_PROTECTION_L          ; 196   ; Signed Integer                                                                                                                                                                                  ;
; PKT_RESPONSE_STATUS_H     ; 204   ; Signed Integer                                                                                                                                                                                  ;
; PKT_RESPONSE_STATUS_L     ; 203   ; Signed Integer                                                                                                                                                                                  ;
; PKT_BURST_SIZE_H          ; 180   ; Signed Integer                                                                                                                                                                                  ;
; PKT_BURST_SIZE_L          ; 178   ; Signed Integer                                                                                                                                                                                  ;
; PKT_ORI_BURST_SIZE_L      ; 205   ; Signed Integer                                                                                                                                                                                  ;
; PKT_ORI_BURST_SIZE_H      ; 207   ; Signed Integer                                                                                                                                                                                  ;
; ST_DATA_W                 ; 208   ; Signed Integer                                                                                                                                                                                  ;
; ST_CHANNEL_W              ; 14    ; Signed Integer                                                                                                                                                                                  ;
; ADDR_W                    ; 20    ; Signed Integer                                                                                                                                                                                  ;
; AVS_DATA_W                ; 128   ; Signed Integer                                                                                                                                                                                  ;
; AVS_BURSTCOUNT_W          ; 5     ; Signed Integer                                                                                                                                                                                  ;
; PKT_SYMBOLS               ; 16    ; Signed Integer                                                                                                                                                                                  ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                                  ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                                  ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                                  ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                                  ;
; AVS_BE_W                  ; 16    ; Signed Integer                                                                                                                                                                                  ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                                  ;
; FIFO_DATA_W               ; 209   ; Signed Integer                                                                                                                                                                                  ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                                  ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_descriptor_slave_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                     ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 20    ; Signed Integer                                                                                                                                                                                                                                           ;
; BURSTWRAP_W    ; 3     ; Signed Integer                                                                                                                                                                                                                                           ;
; BYTE_CNT_W     ; 5     ; Signed Integer                                                                                                                                                                                                                                           ;
; PKT_SYMBOLS    ; 16    ; Signed Integer                                                                                                                                                                                                                                           ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                           ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo ;
+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                       ;
+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                             ;
; BITS_PER_SYMBOL     ; 209   ; Signed Integer                                                                                                                                                                                             ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                             ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                             ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                             ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                             ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                             ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                             ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                             ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                             ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                             ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                             ;
; DATA_WIDTH          ; 209   ; Signed Integer                                                                                                                                                                                             ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                             ;
+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fabric_if_if_bridge_slave_agent ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                      ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 77    ; Signed Integer                                                                                                                                                                            ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                            ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                            ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                            ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                            ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                            ;
; PKT_ADDR_H                ; 55    ; Signed Integer                                                                                                                                                                            ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                            ;
; PKT_TRANS_LOCK            ; 60    ; Signed Integer                                                                                                                                                                            ;
; PKT_TRANS_COMPRESSED_READ ; 56    ; Signed Integer                                                                                                                                                                            ;
; PKT_TRANS_POSTED          ; 57    ; Signed Integer                                                                                                                                                                            ;
; PKT_TRANS_WRITE           ; 58    ; Signed Integer                                                                                                                                                                            ;
; PKT_TRANS_READ            ; 59    ; Signed Integer                                                                                                                                                                            ;
; PKT_SRC_ID_H              ; 82    ; Signed Integer                                                                                                                                                                            ;
; PKT_SRC_ID_L              ; 79    ; Signed Integer                                                                                                                                                                            ;
; PKT_DEST_ID_H             ; 86    ; Signed Integer                                                                                                                                                                            ;
; PKT_DEST_ID_L             ; 83    ; Signed Integer                                                                                                                                                                            ;
; PKT_BURSTWRAP_H           ; 69    ; Signed Integer                                                                                                                                                                            ;
; PKT_BURSTWRAP_L           ; 67    ; Signed Integer                                                                                                                                                                            ;
; PKT_BYTE_CNT_H            ; 66    ; Signed Integer                                                                                                                                                                            ;
; PKT_BYTE_CNT_L            ; 62    ; Signed Integer                                                                                                                                                                            ;
; PKT_PROTECTION_H          ; 90    ; Signed Integer                                                                                                                                                                            ;
; PKT_PROTECTION_L          ; 88    ; Signed Integer                                                                                                                                                                            ;
; PKT_RESPONSE_STATUS_H     ; 96    ; Signed Integer                                                                                                                                                                            ;
; PKT_RESPONSE_STATUS_L     ; 95    ; Signed Integer                                                                                                                                                                            ;
; PKT_BURST_SIZE_H          ; 72    ; Signed Integer                                                                                                                                                                            ;
; PKT_BURST_SIZE_L          ; 70    ; Signed Integer                                                                                                                                                                            ;
; PKT_ORI_BURST_SIZE_L      ; 97    ; Signed Integer                                                                                                                                                                            ;
; PKT_ORI_BURST_SIZE_H      ; 99    ; Signed Integer                                                                                                                                                                            ;
; ST_DATA_W                 ; 100   ; Signed Integer                                                                                                                                                                            ;
; ST_CHANNEL_W              ; 14    ; Signed Integer                                                                                                                                                                            ;
; ADDR_W                    ; 20    ; Signed Integer                                                                                                                                                                            ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                            ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                            ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                            ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                            ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                            ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                            ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                            ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                            ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                            ;
; FIFO_DATA_W               ; 101   ; Signed Integer                                                                                                                                                                            ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                            ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fabric_if_if_bridge_slave_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                               ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 20    ; Signed Integer                                                                                                                                                                                                                                     ;
; BURSTWRAP_W    ; 3     ; Signed Integer                                                                                                                                                                                                                                     ;
; BYTE_CNT_W     ; 5     ; Signed Integer                                                                                                                                                                                                                                     ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                     ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                     ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo ;
+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                 ;
+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                       ;
; BITS_PER_SYMBOL     ; 101   ; Signed Integer                                                                                                                                                                                       ;
; FIFO_DEPTH          ; 5     ; Signed Integer                                                                                                                                                                                       ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                       ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                       ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                       ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                       ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                       ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                       ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                       ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                       ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                       ;
; DATA_WIDTH          ; 101   ; Signed Integer                                                                                                                                                                                       ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                       ;
+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_agent ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                           ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 77    ; Signed Integer                                                                                                                                                                 ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                 ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                 ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                 ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                 ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                 ;
; PKT_ADDR_H                ; 55    ; Signed Integer                                                                                                                                                                 ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                 ;
; PKT_TRANS_LOCK            ; 60    ; Signed Integer                                                                                                                                                                 ;
; PKT_TRANS_COMPRESSED_READ ; 56    ; Signed Integer                                                                                                                                                                 ;
; PKT_TRANS_POSTED          ; 57    ; Signed Integer                                                                                                                                                                 ;
; PKT_TRANS_WRITE           ; 58    ; Signed Integer                                                                                                                                                                 ;
; PKT_TRANS_READ            ; 59    ; Signed Integer                                                                                                                                                                 ;
; PKT_SRC_ID_H              ; 82    ; Signed Integer                                                                                                                                                                 ;
; PKT_SRC_ID_L              ; 79    ; Signed Integer                                                                                                                                                                 ;
; PKT_DEST_ID_H             ; 86    ; Signed Integer                                                                                                                                                                 ;
; PKT_DEST_ID_L             ; 83    ; Signed Integer                                                                                                                                                                 ;
; PKT_BURSTWRAP_H           ; 69    ; Signed Integer                                                                                                                                                                 ;
; PKT_BURSTWRAP_L           ; 67    ; Signed Integer                                                                                                                                                                 ;
; PKT_BYTE_CNT_H            ; 66    ; Signed Integer                                                                                                                                                                 ;
; PKT_BYTE_CNT_L            ; 62    ; Signed Integer                                                                                                                                                                 ;
; PKT_PROTECTION_H          ; 90    ; Signed Integer                                                                                                                                                                 ;
; PKT_PROTECTION_L          ; 88    ; Signed Integer                                                                                                                                                                 ;
; PKT_RESPONSE_STATUS_H     ; 96    ; Signed Integer                                                                                                                                                                 ;
; PKT_RESPONSE_STATUS_L     ; 95    ; Signed Integer                                                                                                                                                                 ;
; PKT_BURST_SIZE_H          ; 72    ; Signed Integer                                                                                                                                                                 ;
; PKT_BURST_SIZE_L          ; 70    ; Signed Integer                                                                                                                                                                 ;
; PKT_ORI_BURST_SIZE_L      ; 97    ; Signed Integer                                                                                                                                                                 ;
; PKT_ORI_BURST_SIZE_H      ; 99    ; Signed Integer                                                                                                                                                                 ;
; ST_DATA_W                 ; 100   ; Signed Integer                                                                                                                                                                 ;
; ST_CHANNEL_W              ; 14    ; Signed Integer                                                                                                                                                                 ;
; ADDR_W                    ; 20    ; Signed Integer                                                                                                                                                                 ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                 ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                 ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                 ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                 ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                 ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                 ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                 ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                 ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                 ;
; FIFO_DATA_W               ; 101   ; Signed Integer                                                                                                                                                                 ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                 ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                    ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 20    ; Signed Integer                                                                                                                                                                                                                          ;
; BURSTWRAP_W    ; 3     ; Signed Integer                                                                                                                                                                                                                          ;
; BYTE_CNT_W     ; 5     ; Signed Integer                                                                                                                                                                                                                          ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                          ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                          ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo ;
+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                      ;
+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                            ;
; BITS_PER_SYMBOL     ; 101   ; Signed Integer                                                                                                                                                                            ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                            ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                            ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                            ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                            ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                            ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                            ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                            ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                            ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                            ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                            ;
; DATA_WIDTH          ; 101   ; Signed Integer                                                                                                                                                                            ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                            ;
+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_csr_agent ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                               ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 77    ; Signed Integer                                                                                                                                                                     ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                     ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                     ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                     ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                     ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                     ;
; PKT_ADDR_H                ; 55    ; Signed Integer                                                                                                                                                                     ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                     ;
; PKT_TRANS_LOCK            ; 60    ; Signed Integer                                                                                                                                                                     ;
; PKT_TRANS_COMPRESSED_READ ; 56    ; Signed Integer                                                                                                                                                                     ;
; PKT_TRANS_POSTED          ; 57    ; Signed Integer                                                                                                                                                                     ;
; PKT_TRANS_WRITE           ; 58    ; Signed Integer                                                                                                                                                                     ;
; PKT_TRANS_READ            ; 59    ; Signed Integer                                                                                                                                                                     ;
; PKT_SRC_ID_H              ; 82    ; Signed Integer                                                                                                                                                                     ;
; PKT_SRC_ID_L              ; 79    ; Signed Integer                                                                                                                                                                     ;
; PKT_DEST_ID_H             ; 86    ; Signed Integer                                                                                                                                                                     ;
; PKT_DEST_ID_L             ; 83    ; Signed Integer                                                                                                                                                                     ;
; PKT_BURSTWRAP_H           ; 69    ; Signed Integer                                                                                                                                                                     ;
; PKT_BURSTWRAP_L           ; 67    ; Signed Integer                                                                                                                                                                     ;
; PKT_BYTE_CNT_H            ; 66    ; Signed Integer                                                                                                                                                                     ;
; PKT_BYTE_CNT_L            ; 62    ; Signed Integer                                                                                                                                                                     ;
; PKT_PROTECTION_H          ; 90    ; Signed Integer                                                                                                                                                                     ;
; PKT_PROTECTION_L          ; 88    ; Signed Integer                                                                                                                                                                     ;
; PKT_RESPONSE_STATUS_H     ; 96    ; Signed Integer                                                                                                                                                                     ;
; PKT_RESPONSE_STATUS_L     ; 95    ; Signed Integer                                                                                                                                                                     ;
; PKT_BURST_SIZE_H          ; 72    ; Signed Integer                                                                                                                                                                     ;
; PKT_BURST_SIZE_L          ; 70    ; Signed Integer                                                                                                                                                                     ;
; PKT_ORI_BURST_SIZE_L      ; 97    ; Signed Integer                                                                                                                                                                     ;
; PKT_ORI_BURST_SIZE_H      ; 99    ; Signed Integer                                                                                                                                                                     ;
; ST_DATA_W                 ; 100   ; Signed Integer                                                                                                                                                                     ;
; ST_CHANNEL_W              ; 14    ; Signed Integer                                                                                                                                                                     ;
; ADDR_W                    ; 20    ; Signed Integer                                                                                                                                                                     ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                     ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                     ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                     ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                     ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                     ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                     ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                     ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                     ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                     ;
; FIFO_DATA_W               ; 101   ; Signed Integer                                                                                                                                                                     ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                     ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_csr_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                        ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 20    ; Signed Integer                                                                                                                                                                                                                              ;
; BURSTWRAP_W    ; 3     ; Signed Integer                                                                                                                                                                                                                              ;
; BYTE_CNT_W     ; 5     ; Signed Integer                                                                                                                                                                                                                              ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                              ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                              ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                          ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                ;
; BITS_PER_SYMBOL     ; 101   ; Signed Integer                                                                                                                                                                                ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                ;
; DATA_WIDTH          ; 101   ; Signed Integer                                                                                                                                                                                ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_response_agent ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                    ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 77    ; Signed Integer                                                                                                                                                                          ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                          ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                          ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                          ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                          ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                          ;
; PKT_ADDR_H                ; 55    ; Signed Integer                                                                                                                                                                          ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                          ;
; PKT_TRANS_LOCK            ; 60    ; Signed Integer                                                                                                                                                                          ;
; PKT_TRANS_COMPRESSED_READ ; 56    ; Signed Integer                                                                                                                                                                          ;
; PKT_TRANS_POSTED          ; 57    ; Signed Integer                                                                                                                                                                          ;
; PKT_TRANS_WRITE           ; 58    ; Signed Integer                                                                                                                                                                          ;
; PKT_TRANS_READ            ; 59    ; Signed Integer                                                                                                                                                                          ;
; PKT_SRC_ID_H              ; 82    ; Signed Integer                                                                                                                                                                          ;
; PKT_SRC_ID_L              ; 79    ; Signed Integer                                                                                                                                                                          ;
; PKT_DEST_ID_H             ; 86    ; Signed Integer                                                                                                                                                                          ;
; PKT_DEST_ID_L             ; 83    ; Signed Integer                                                                                                                                                                          ;
; PKT_BURSTWRAP_H           ; 69    ; Signed Integer                                                                                                                                                                          ;
; PKT_BURSTWRAP_L           ; 67    ; Signed Integer                                                                                                                                                                          ;
; PKT_BYTE_CNT_H            ; 66    ; Signed Integer                                                                                                                                                                          ;
; PKT_BYTE_CNT_L            ; 62    ; Signed Integer                                                                                                                                                                          ;
; PKT_PROTECTION_H          ; 90    ; Signed Integer                                                                                                                                                                          ;
; PKT_PROTECTION_L          ; 88    ; Signed Integer                                                                                                                                                                          ;
; PKT_RESPONSE_STATUS_H     ; 96    ; Signed Integer                                                                                                                                                                          ;
; PKT_RESPONSE_STATUS_L     ; 95    ; Signed Integer                                                                                                                                                                          ;
; PKT_BURST_SIZE_H          ; 72    ; Signed Integer                                                                                                                                                                          ;
; PKT_BURST_SIZE_L          ; 70    ; Signed Integer                                                                                                                                                                          ;
; PKT_ORI_BURST_SIZE_L      ; 97    ; Signed Integer                                                                                                                                                                          ;
; PKT_ORI_BURST_SIZE_H      ; 99    ; Signed Integer                                                                                                                                                                          ;
; ST_DATA_W                 ; 100   ; Signed Integer                                                                                                                                                                          ;
; ST_CHANNEL_W              ; 14    ; Signed Integer                                                                                                                                                                          ;
; ADDR_W                    ; 20    ; Signed Integer                                                                                                                                                                          ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                          ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                          ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                          ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                          ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                          ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                          ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                          ;
; FIFO_DATA_W               ; 101   ; Signed Integer                                                                                                                                                                          ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                          ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_response_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                             ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 20    ; Signed Integer                                                                                                                                                                                                                                   ;
; BURSTWRAP_W    ; 3     ; Signed Integer                                                                                                                                                                                                                                   ;
; BYTE_CNT_W     ; 5     ; Signed Integer                                                                                                                                                                                                                                   ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                   ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                   ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                               ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                     ;
; BITS_PER_SYMBOL     ; 101   ; Signed Integer                                                                                                                                                                                     ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                     ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                     ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                     ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                     ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                     ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                     ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                     ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                     ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                     ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                     ;
; DATA_WIDTH          ; 101   ; Signed Integer                                                                                                                                                                                     ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                     ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:onchip_mem_s1_agent ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                          ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 77    ; Signed Integer                                                                                                                                                                ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                ;
; PKT_ADDR_H                ; 55    ; Signed Integer                                                                                                                                                                ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                ;
; PKT_TRANS_LOCK            ; 60    ; Signed Integer                                                                                                                                                                ;
; PKT_TRANS_COMPRESSED_READ ; 56    ; Signed Integer                                                                                                                                                                ;
; PKT_TRANS_POSTED          ; 57    ; Signed Integer                                                                                                                                                                ;
; PKT_TRANS_WRITE           ; 58    ; Signed Integer                                                                                                                                                                ;
; PKT_TRANS_READ            ; 59    ; Signed Integer                                                                                                                                                                ;
; PKT_SRC_ID_H              ; 82    ; Signed Integer                                                                                                                                                                ;
; PKT_SRC_ID_L              ; 79    ; Signed Integer                                                                                                                                                                ;
; PKT_DEST_ID_H             ; 86    ; Signed Integer                                                                                                                                                                ;
; PKT_DEST_ID_L             ; 83    ; Signed Integer                                                                                                                                                                ;
; PKT_BURSTWRAP_H           ; 69    ; Signed Integer                                                                                                                                                                ;
; PKT_BURSTWRAP_L           ; 67    ; Signed Integer                                                                                                                                                                ;
; PKT_BYTE_CNT_H            ; 66    ; Signed Integer                                                                                                                                                                ;
; PKT_BYTE_CNT_L            ; 62    ; Signed Integer                                                                                                                                                                ;
; PKT_PROTECTION_H          ; 90    ; Signed Integer                                                                                                                                                                ;
; PKT_PROTECTION_L          ; 88    ; Signed Integer                                                                                                                                                                ;
; PKT_RESPONSE_STATUS_H     ; 96    ; Signed Integer                                                                                                                                                                ;
; PKT_RESPONSE_STATUS_L     ; 95    ; Signed Integer                                                                                                                                                                ;
; PKT_BURST_SIZE_H          ; 72    ; Signed Integer                                                                                                                                                                ;
; PKT_BURST_SIZE_L          ; 70    ; Signed Integer                                                                                                                                                                ;
; PKT_ORI_BURST_SIZE_L      ; 97    ; Signed Integer                                                                                                                                                                ;
; PKT_ORI_BURST_SIZE_H      ; 99    ; Signed Integer                                                                                                                                                                ;
; ST_DATA_W                 ; 100   ; Signed Integer                                                                                                                                                                ;
; ST_CHANNEL_W              ; 14    ; Signed Integer                                                                                                                                                                ;
; ADDR_W                    ; 20    ; Signed Integer                                                                                                                                                                ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                ;
; FIFO_DATA_W               ; 101   ; Signed Integer                                                                                                                                                                ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                ;
+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:onchip_mem_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 20    ; Signed Integer                                                                                                                                                                                                                         ;
; BURSTWRAP_W    ; 3     ; Signed Integer                                                                                                                                                                                                                         ;
; BYTE_CNT_W     ; 5     ; Signed Integer                                                                                                                                                                                                                         ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                         ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                         ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo ;
+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                     ;
+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                           ;
; BITS_PER_SYMBOL     ; 101   ; Signed Integer                                                                                                                                                                           ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                           ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                           ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                           ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                           ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                           ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                           ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                           ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                           ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                           ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                           ;
; DATA_WIDTH          ; 101   ; Signed Integer                                                                                                                                                                           ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                           ;
+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_tx_dpram_s1_agent ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                  ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 77    ; Signed Integer                                                                                                                                                                        ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                        ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                        ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                        ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                        ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                        ;
; PKT_ADDR_H                ; 55    ; Signed Integer                                                                                                                                                                        ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_LOCK            ; 60    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_COMPRESSED_READ ; 56    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_POSTED          ; 57    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_WRITE           ; 58    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_READ            ; 59    ; Signed Integer                                                                                                                                                                        ;
; PKT_SRC_ID_H              ; 82    ; Signed Integer                                                                                                                                                                        ;
; PKT_SRC_ID_L              ; 79    ; Signed Integer                                                                                                                                                                        ;
; PKT_DEST_ID_H             ; 86    ; Signed Integer                                                                                                                                                                        ;
; PKT_DEST_ID_L             ; 83    ; Signed Integer                                                                                                                                                                        ;
; PKT_BURSTWRAP_H           ; 69    ; Signed Integer                                                                                                                                                                        ;
; PKT_BURSTWRAP_L           ; 67    ; Signed Integer                                                                                                                                                                        ;
; PKT_BYTE_CNT_H            ; 66    ; Signed Integer                                                                                                                                                                        ;
; PKT_BYTE_CNT_L            ; 62    ; Signed Integer                                                                                                                                                                        ;
; PKT_PROTECTION_H          ; 90    ; Signed Integer                                                                                                                                                                        ;
; PKT_PROTECTION_L          ; 88    ; Signed Integer                                                                                                                                                                        ;
; PKT_RESPONSE_STATUS_H     ; 96    ; Signed Integer                                                                                                                                                                        ;
; PKT_RESPONSE_STATUS_L     ; 95    ; Signed Integer                                                                                                                                                                        ;
; PKT_BURST_SIZE_H          ; 72    ; Signed Integer                                                                                                                                                                        ;
; PKT_BURST_SIZE_L          ; 70    ; Signed Integer                                                                                                                                                                        ;
; PKT_ORI_BURST_SIZE_L      ; 97    ; Signed Integer                                                                                                                                                                        ;
; PKT_ORI_BURST_SIZE_H      ; 99    ; Signed Integer                                                                                                                                                                        ;
; ST_DATA_W                 ; 100   ; Signed Integer                                                                                                                                                                        ;
; ST_CHANNEL_W              ; 14    ; Signed Integer                                                                                                                                                                        ;
; ADDR_W                    ; 20    ; Signed Integer                                                                                                                                                                        ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                        ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                        ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                        ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                        ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                        ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                        ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                        ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                        ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                        ;
; FIFO_DATA_W               ; 101   ; Signed Integer                                                                                                                                                                        ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                        ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_tx_dpram_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                           ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 20    ; Signed Integer                                                                                                                                                                                                                                 ;
; BURSTWRAP_W    ; 3     ; Signed Integer                                                                                                                                                                                                                                 ;
; BYTE_CNT_W     ; 5     ; Signed Integer                                                                                                                                                                                                                                 ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                 ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                 ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                             ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                   ;
; BITS_PER_SYMBOL     ; 101   ; Signed Integer                                                                                                                                                                                   ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                   ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                   ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                   ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                   ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                   ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                   ;
; DATA_WIDTH          ; 101   ; Signed Integer                                                                                                                                                                                   ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                   ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_ctrl_s1_agent ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                       ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 77    ; Signed Integer                                                                                                                                                             ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                             ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                             ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                             ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                             ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                             ;
; PKT_ADDR_H                ; 55    ; Signed Integer                                                                                                                                                             ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                             ;
; PKT_TRANS_LOCK            ; 60    ; Signed Integer                                                                                                                                                             ;
; PKT_TRANS_COMPRESSED_READ ; 56    ; Signed Integer                                                                                                                                                             ;
; PKT_TRANS_POSTED          ; 57    ; Signed Integer                                                                                                                                                             ;
; PKT_TRANS_WRITE           ; 58    ; Signed Integer                                                                                                                                                             ;
; PKT_TRANS_READ            ; 59    ; Signed Integer                                                                                                                                                             ;
; PKT_SRC_ID_H              ; 82    ; Signed Integer                                                                                                                                                             ;
; PKT_SRC_ID_L              ; 79    ; Signed Integer                                                                                                                                                             ;
; PKT_DEST_ID_H             ; 86    ; Signed Integer                                                                                                                                                             ;
; PKT_DEST_ID_L             ; 83    ; Signed Integer                                                                                                                                                             ;
; PKT_BURSTWRAP_H           ; 69    ; Signed Integer                                                                                                                                                             ;
; PKT_BURSTWRAP_L           ; 67    ; Signed Integer                                                                                                                                                             ;
; PKT_BYTE_CNT_H            ; 66    ; Signed Integer                                                                                                                                                             ;
; PKT_BYTE_CNT_L            ; 62    ; Signed Integer                                                                                                                                                             ;
; PKT_PROTECTION_H          ; 90    ; Signed Integer                                                                                                                                                             ;
; PKT_PROTECTION_L          ; 88    ; Signed Integer                                                                                                                                                             ;
; PKT_RESPONSE_STATUS_H     ; 96    ; Signed Integer                                                                                                                                                             ;
; PKT_RESPONSE_STATUS_L     ; 95    ; Signed Integer                                                                                                                                                             ;
; PKT_BURST_SIZE_H          ; 72    ; Signed Integer                                                                                                                                                             ;
; PKT_BURST_SIZE_L          ; 70    ; Signed Integer                                                                                                                                                             ;
; PKT_ORI_BURST_SIZE_L      ; 97    ; Signed Integer                                                                                                                                                             ;
; PKT_ORI_BURST_SIZE_H      ; 99    ; Signed Integer                                                                                                                                                             ;
; ST_DATA_W                 ; 100   ; Signed Integer                                                                                                                                                             ;
; ST_CHANNEL_W              ; 14    ; Signed Integer                                                                                                                                                             ;
; ADDR_W                    ; 20    ; Signed Integer                                                                                                                                                             ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                             ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                             ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                             ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                             ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                             ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                             ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                             ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                             ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                             ;
; FIFO_DATA_W               ; 101   ; Signed Integer                                                                                                                                                             ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                             ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_ctrl_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 20    ; Signed Integer                                                                                                                                                                                                                      ;
; BURSTWRAP_W    ; 3     ; Signed Integer                                                                                                                                                                                                                      ;
; BYTE_CNT_W     ; 5     ; Signed Integer                                                                                                                                                                                                                      ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                      ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                      ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                  ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                        ;
; BITS_PER_SYMBOL     ; 101   ; Signed Integer                                                                                                                                                                        ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                        ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                        ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                        ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                        ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                        ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                        ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                        ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                        ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                        ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                        ;
; DATA_WIDTH          ; 101   ; Signed Integer                                                                                                                                                                        ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                        ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_status_s1_agent ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                         ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 77    ; Signed Integer                                                                                                                                                               ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                               ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                               ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                               ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                               ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                               ;
; PKT_ADDR_H                ; 55    ; Signed Integer                                                                                                                                                               ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                               ;
; PKT_TRANS_LOCK            ; 60    ; Signed Integer                                                                                                                                                               ;
; PKT_TRANS_COMPRESSED_READ ; 56    ; Signed Integer                                                                                                                                                               ;
; PKT_TRANS_POSTED          ; 57    ; Signed Integer                                                                                                                                                               ;
; PKT_TRANS_WRITE           ; 58    ; Signed Integer                                                                                                                                                               ;
; PKT_TRANS_READ            ; 59    ; Signed Integer                                                                                                                                                               ;
; PKT_SRC_ID_H              ; 82    ; Signed Integer                                                                                                                                                               ;
; PKT_SRC_ID_L              ; 79    ; Signed Integer                                                                                                                                                               ;
; PKT_DEST_ID_H             ; 86    ; Signed Integer                                                                                                                                                               ;
; PKT_DEST_ID_L             ; 83    ; Signed Integer                                                                                                                                                               ;
; PKT_BURSTWRAP_H           ; 69    ; Signed Integer                                                                                                                                                               ;
; PKT_BURSTWRAP_L           ; 67    ; Signed Integer                                                                                                                                                               ;
; PKT_BYTE_CNT_H            ; 66    ; Signed Integer                                                                                                                                                               ;
; PKT_BYTE_CNT_L            ; 62    ; Signed Integer                                                                                                                                                               ;
; PKT_PROTECTION_H          ; 90    ; Signed Integer                                                                                                                                                               ;
; PKT_PROTECTION_L          ; 88    ; Signed Integer                                                                                                                                                               ;
; PKT_RESPONSE_STATUS_H     ; 96    ; Signed Integer                                                                                                                                                               ;
; PKT_RESPONSE_STATUS_L     ; 95    ; Signed Integer                                                                                                                                                               ;
; PKT_BURST_SIZE_H          ; 72    ; Signed Integer                                                                                                                                                               ;
; PKT_BURST_SIZE_L          ; 70    ; Signed Integer                                                                                                                                                               ;
; PKT_ORI_BURST_SIZE_L      ; 97    ; Signed Integer                                                                                                                                                               ;
; PKT_ORI_BURST_SIZE_H      ; 99    ; Signed Integer                                                                                                                                                               ;
; ST_DATA_W                 ; 100   ; Signed Integer                                                                                                                                                               ;
; ST_CHANNEL_W              ; 14    ; Signed Integer                                                                                                                                                               ;
; ADDR_W                    ; 20    ; Signed Integer                                                                                                                                                               ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                               ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                               ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                               ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                               ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                               ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                               ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                               ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                               ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                               ;
; FIFO_DATA_W               ; 101   ; Signed Integer                                                                                                                                                               ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                               ;
+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                  ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 20    ; Signed Integer                                                                                                                                                                                                                        ;
; BURSTWRAP_W    ; 3     ; Signed Integer                                                                                                                                                                                                                        ;
; BYTE_CNT_W     ; 5     ; Signed Integer                                                                                                                                                                                                                        ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                        ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                        ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                    ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                          ;
; BITS_PER_SYMBOL     ; 101   ; Signed Integer                                                                                                                                                                          ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                          ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                          ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                          ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                          ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                          ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                          ;
; DATA_WIDTH          ; 101   ; Signed Integer                                                                                                                                                                          ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                          ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_rx_dpram_s1_agent ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                  ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 77    ; Signed Integer                                                                                                                                                                        ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                        ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                        ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                        ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                        ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                        ;
; PKT_ADDR_H                ; 55    ; Signed Integer                                                                                                                                                                        ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_LOCK            ; 60    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_COMPRESSED_READ ; 56    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_POSTED          ; 57    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_WRITE           ; 58    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_READ            ; 59    ; Signed Integer                                                                                                                                                                        ;
; PKT_SRC_ID_H              ; 82    ; Signed Integer                                                                                                                                                                        ;
; PKT_SRC_ID_L              ; 79    ; Signed Integer                                                                                                                                                                        ;
; PKT_DEST_ID_H             ; 86    ; Signed Integer                                                                                                                                                                        ;
; PKT_DEST_ID_L             ; 83    ; Signed Integer                                                                                                                                                                        ;
; PKT_BURSTWRAP_H           ; 69    ; Signed Integer                                                                                                                                                                        ;
; PKT_BURSTWRAP_L           ; 67    ; Signed Integer                                                                                                                                                                        ;
; PKT_BYTE_CNT_H            ; 66    ; Signed Integer                                                                                                                                                                        ;
; PKT_BYTE_CNT_L            ; 62    ; Signed Integer                                                                                                                                                                        ;
; PKT_PROTECTION_H          ; 90    ; Signed Integer                                                                                                                                                                        ;
; PKT_PROTECTION_L          ; 88    ; Signed Integer                                                                                                                                                                        ;
; PKT_RESPONSE_STATUS_H     ; 96    ; Signed Integer                                                                                                                                                                        ;
; PKT_RESPONSE_STATUS_L     ; 95    ; Signed Integer                                                                                                                                                                        ;
; PKT_BURST_SIZE_H          ; 72    ; Signed Integer                                                                                                                                                                        ;
; PKT_BURST_SIZE_L          ; 70    ; Signed Integer                                                                                                                                                                        ;
; PKT_ORI_BURST_SIZE_L      ; 97    ; Signed Integer                                                                                                                                                                        ;
; PKT_ORI_BURST_SIZE_H      ; 99    ; Signed Integer                                                                                                                                                                        ;
; ST_DATA_W                 ; 100   ; Signed Integer                                                                                                                                                                        ;
; ST_CHANNEL_W              ; 14    ; Signed Integer                                                                                                                                                                        ;
; ADDR_W                    ; 20    ; Signed Integer                                                                                                                                                                        ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                        ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                        ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                        ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                        ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                        ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                        ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                        ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                        ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                        ;
; FIFO_DATA_W               ; 101   ; Signed Integer                                                                                                                                                                        ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                        ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_rx_dpram_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                           ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 20    ; Signed Integer                                                                                                                                                                                                                                 ;
; BURSTWRAP_W    ; 3     ; Signed Integer                                                                                                                                                                                                                                 ;
; BYTE_CNT_W     ; 5     ; Signed Integer                                                                                                                                                                                                                                 ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                 ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                 ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                             ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                   ;
; BITS_PER_SYMBOL     ; 101   ; Signed Integer                                                                                                                                                                                   ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                   ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                   ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                   ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                   ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                   ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                   ;
; DATA_WIDTH          ; 101   ; Signed Integer                                                                                                                                                                                   ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                   ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router:router|nios2_mm_interconnect_0_router_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                          ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 9     ; Signed Integer                                                                                                                                                                                                                                ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                ;
; DEFAULT_DESTID     ; 13    ; Signed Integer                                                                                                                                                                                                                                ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_001:router_001|nios2_mm_interconnect_0_router_001_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 1     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 13    ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_002|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_003|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_004|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_005:router_005|nios2_mm_interconnect_0_router_005_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_006:router_006|nios2_mm_interconnect_0_router_006_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_007|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_008|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_009|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_010|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_005:router_011|nios2_mm_interconnect_0_router_005_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_012|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_013|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_014|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_015|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003|altera_merlin_arbitrator:arb ;
+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value       ; Type                                                                                                                                                                                                              ;
+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; NUM_REQUESTERS ; 2           ; Signed Integer                                                                                                                                                                                                    ;
; SCHEME         ; round-robin ; String                                                                                                                                                                                                            ;
; PIPELINE       ; 1           ; Signed Integer                                                                                                                                                                                                    ;
+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                  ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; WIDTH          ; 4     ; Signed Integer                                                                                                                                                                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_009|altera_merlin_arbitrator:arb ;
+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value       ; Type                                                                                                                                                                                                              ;
+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; NUM_REQUESTERS ; 2           ; Signed Integer                                                                                                                                                                                                    ;
; SCHEME         ; round-robin ; String                                                                                                                                                                                                            ;
; PIPELINE       ; 1           ; Signed Integer                                                                                                                                                                                                    ;
+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_009|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                  ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; WIDTH          ; 4     ; Signed Integer                                                                                                                                                                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb ;
+----------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                                                                                                                                                           ;
+----------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; NUM_REQUESTERS ; 14     ; Signed Integer                                                                                                                                                                                                 ;
; SCHEME         ; no-arb ; String                                                                                                                                                                                                         ;
; PIPELINE       ; 0      ; Signed Integer                                                                                                                                                                                                 ;
+----------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                          ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; WIDTH          ; 28    ; Signed Integer                                                                                                                                                                                                                                ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux_001:rsp_mux_001|altera_merlin_arbitrator:arb ;
+----------------+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                                                                                                                                                                   ;
+----------------+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; NUM_REQUESTERS ; 2      ; Signed Integer                                                                                                                                                                                                         ;
; SCHEME         ; no-arb ; String                                                                                                                                                                                                                 ;
; PIPELINE       ; 0      ; Signed Integer                                                                                                                                                                                                         ;
+----------------+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux_001:rsp_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                  ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; WIDTH          ; 4     ; Signed Integer                                                                                                                                                                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter ;
+-------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                ; Value ; Type                                                                                                                                                                                                      ;
+-------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; IN_PKT_ADDR_L                 ; 36    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_ADDR_H                 ; 55    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_DATA_L                 ; 0     ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_DATA_H                 ; 31    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BYTEEN_L               ; 32    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BYTEEN_H               ; 35    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_TRANS_COMPRESSED_READ  ; 56    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BYTE_CNT_L             ; 62    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BYTE_CNT_H             ; 66    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BURSTWRAP_L            ; 67    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BURSTWRAP_H            ; 69    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BURST_SIZE_L           ; 70    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BURST_SIZE_H           ; 72    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_RESPONSE_STATUS_L      ; 95    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_RESPONSE_STATUS_H      ; 96    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_TRANS_EXCLUSIVE        ; 61    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BURST_TYPE_L           ; 73    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BURST_TYPE_H           ; 74    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_ORI_BURST_SIZE_L       ; 97    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_ORI_BURST_SIZE_H       ; 99    ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_TRANS_WRITE            ; 58    ; Signed Integer                                                                                                                                                                                            ;
; IN_ST_DATA_W                  ; 100   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_ADDR_L                ; 144   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_ADDR_H                ; 163   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_DATA_H                ; 127   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_BYTEEN_L              ; 128   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_BYTEEN_H              ; 143   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_TRANS_COMPRESSED_READ ; 164   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_BYTE_CNT_L            ; 170   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_BYTE_CNT_H            ; 174   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_BURST_SIZE_L          ; 178   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_BURST_SIZE_H          ; 180   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_RESPONSE_STATUS_L     ; 203   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_RESPONSE_STATUS_H     ; 204   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_TRANS_EXCLUSIVE       ; 169   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_BURST_TYPE_L          ; 181   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_BURST_TYPE_H          ; 182   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_ORI_BURST_SIZE_L      ; 205   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_ORI_BURST_SIZE_H      ; 207   ; Signed Integer                                                                                                                                                                                            ;
; OUT_ST_DATA_W                 ; 208   ; Signed Integer                                                                                                                                                                                            ;
; ST_CHANNEL_W                  ; 14    ; Signed Integer                                                                                                                                                                                            ;
; OPTIMIZE_FOR_RSP              ; 0     ; Signed Integer                                                                                                                                                                                            ;
; PACKING                       ; 1     ; Signed Integer                                                                                                                                                                                            ;
; CONSTANT_BURST_SIZE           ; 1     ; Signed Integer                                                                                                                                                                                            ;
; RESPONSE_PATH                 ; 0     ; Signed Integer                                                                                                                                                                                            ;
; ENABLE_ADDRESS_ALIGNMENT      ; 0     ; Signed Integer                                                                                                                                                                                            ;
+-------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                   ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 20    ; Signed Integer                                                                                                                                                                                                                                                         ;
; BURSTWRAP_W    ; 3     ; Signed Integer                                                                                                                                                                                                                                                         ;
; BYTE_CNT_W     ; 5     ; Signed Integer                                                                                                                                                                                                                                                         ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                                         ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                                         ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_rsp_width_adapter ;
+-------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                ; Value ; Type                                                                                                                                                                                                      ;
+-------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; IN_PKT_ADDR_L                 ; 144   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_ADDR_H                 ; 163   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_DATA_L                 ; 0     ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_DATA_H                 ; 127   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BYTEEN_L               ; 128   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BYTEEN_H               ; 143   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_TRANS_COMPRESSED_READ  ; 164   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BYTE_CNT_L             ; 170   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BYTE_CNT_H             ; 174   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BURSTWRAP_L            ; 175   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BURSTWRAP_H            ; 177   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BURST_SIZE_L           ; 178   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BURST_SIZE_H           ; 180   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_RESPONSE_STATUS_L      ; 203   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_RESPONSE_STATUS_H      ; 204   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_TRANS_EXCLUSIVE        ; 169   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BURST_TYPE_L           ; 181   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_BURST_TYPE_H           ; 182   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_ORI_BURST_SIZE_L       ; 205   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_ORI_BURST_SIZE_H       ; 207   ; Signed Integer                                                                                                                                                                                            ;
; IN_PKT_TRANS_WRITE            ; 166   ; Signed Integer                                                                                                                                                                                            ;
; IN_ST_DATA_W                  ; 208   ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_ADDR_H                ; 55    ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_TRANS_COMPRESSED_READ ; 56    ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_BYTE_CNT_L            ; 62    ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_BYTE_CNT_H            ; 66    ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_BURST_SIZE_L          ; 70    ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_BURST_SIZE_H          ; 72    ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_RESPONSE_STATUS_L     ; 95    ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_RESPONSE_STATUS_H     ; 96    ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_TRANS_EXCLUSIVE       ; 61    ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_BURST_TYPE_L          ; 73    ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_BURST_TYPE_H          ; 74    ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_ORI_BURST_SIZE_L      ; 97    ; Signed Integer                                                                                                                                                                                            ;
; OUT_PKT_ORI_BURST_SIZE_H      ; 99    ; Signed Integer                                                                                                                                                                                            ;
; OUT_ST_DATA_W                 ; 100   ; Signed Integer                                                                                                                                                                                            ;
; ST_CHANNEL_W                  ; 14    ; Signed Integer                                                                                                                                                                                            ;
; OPTIMIZE_FOR_RSP              ; 1     ; Signed Integer                                                                                                                                                                                            ;
; PACKING                       ; 1     ; Signed Integer                                                                                                                                                                                            ;
; CONSTANT_BURST_SIZE           ; 1     ; Signed Integer                                                                                                                                                                                            ;
; RESPONSE_PATH                 ; 1     ; Signed Integer                                                                                                                                                                                            ;
; ENABLE_ADDRESS_ALIGNMENT      ; 0     ; Signed Integer                                                                                                                                                                                            ;
+-------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter ;
+-----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                  ;
+-----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                        ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                        ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                        ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                        ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                        ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                        ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                        ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                        ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                        ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                        ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                        ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                        ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                        ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                        ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                        ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                        ;
+-----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                      ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                            ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                            ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                      ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                            ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                            ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                      ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                            ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                            ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter_004:avalon_st_adapter_004 ;
+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                          ;
+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 130   ; Signed Integer                                                                                                                                                                                                ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                                ;
; inDataWidth     ; 130   ; Signed Integer                                                                                                                                                                                                ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                                ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                                ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                                ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                                ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                                ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                                ;
; outDataWidth    ; 130   ; Signed Integer                                                                                                                                                                                                ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                                ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                                ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                                ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                                ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                                ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                                ;
+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                      ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                            ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                            ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                      ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                            ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                            ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                      ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                            ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                            ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                      ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                            ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                            ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                      ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                            ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                            ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                      ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                            ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                            ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                      ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                            ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                            ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                      ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                            ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                            ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                      ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                            ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                            ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_translator:enet_tx_msgdma_mm_read_translator ;
+-----------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name              ; Value ; Type                                                                                                                                                                                            ;
+-----------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                ; 14    ; Signed Integer                                                                                                                                                                                  ;
; AV_DATA_W                   ; 32    ; Signed Integer                                                                                                                                                                                  ;
; AV_BURSTCOUNT_W             ; 1     ; Signed Integer                                                                                                                                                                                  ;
; AV_BYTEENABLE_W             ; 4     ; Signed Integer                                                                                                                                                                                  ;
; UAV_ADDRESS_W               ; 14    ; Signed Integer                                                                                                                                                                                  ;
; UAV_BURSTCOUNT_W            ; 3     ; Signed Integer                                                                                                                                                                                  ;
; USE_BURSTCOUNT              ; 0     ; Signed Integer                                                                                                                                                                                  ;
; USE_BEGINBURSTTRANSFER      ; 0     ; Signed Integer                                                                                                                                                                                  ;
; USE_BEGINTRANSFER           ; 0     ; Signed Integer                                                                                                                                                                                  ;
; USE_CHIPSELECT              ; 0     ; Signed Integer                                                                                                                                                                                  ;
; USE_READ                    ; 1     ; Signed Integer                                                                                                                                                                                  ;
; USE_READDATAVALID           ; 1     ; Signed Integer                                                                                                                                                                                  ;
; USE_WRITE                   ; 0     ; Signed Integer                                                                                                                                                                                  ;
; USE_WAITREQUEST             ; 1     ; Signed Integer                                                                                                                                                                                  ;
; USE_WRITERESPONSE           ; 0     ; Signed Integer                                                                                                                                                                                  ;
; USE_READRESPONSE            ; 0     ; Signed Integer                                                                                                                                                                                  ;
; AV_REGISTERINCOMINGSIGNALS  ; 0     ; Signed Integer                                                                                                                                                                                  ;
; AV_SYMBOLS_PER_WORD         ; 4     ; Signed Integer                                                                                                                                                                                  ;
; AV_ADDRESS_SYMBOLS          ; 1     ; Signed Integer                                                                                                                                                                                  ;
; AV_CONSTANT_BURST_BEHAVIOR  ; 0     ; Signed Integer                                                                                                                                                                                  ;
; UAV_CONSTANT_BURST_BEHAVIOR ; 0     ; Signed Integer                                                                                                                                                                                  ;
; AV_BURSTCOUNT_SYMBOLS       ; 0     ; Signed Integer                                                                                                                                                                                  ;
; AV_LINEWRAPBURSTS           ; 0     ; Signed Integer                                                                                                                                                                                  ;
+-----------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_nios_tx_dpram_s2_translator ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                       ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 9     ; Signed Integer                                                                                                                                                                             ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                             ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                             ;
; AV_BYTEENABLE_W                ; 4     ; Signed Integer                                                                                                                                                                             ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                             ;
; AV_READLATENCY                 ; 1     ; Signed Integer                                                                                                                                                                             ;
; AV_READ_WAIT_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                             ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                             ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                             ;
; UAV_ADDRESS_W                  ; 14    ; Signed Integer                                                                                                                                                                             ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                             ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                             ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                             ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                             ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                             ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_udp_dpram_s2_translator ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                   ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 10    ; Signed Integer                                                                                                                                                                         ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                         ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                         ;
; AV_BYTEENABLE_W                ; 4     ; Signed Integer                                                                                                                                                                         ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                         ;
; AV_READLATENCY                 ; 1     ; Signed Integer                                                                                                                                                                         ;
; AV_READ_WAIT_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                         ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                         ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                         ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                         ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                         ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                         ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                         ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                         ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                         ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                         ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                         ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                         ;
; UAV_ADDRESS_W                  ; 14    ; Signed Integer                                                                                                                                                                         ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                         ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                         ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                         ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                         ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                         ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                         ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                         ;
+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_agent:enet_tx_msgdma_mm_read_agent ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                    ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_QOS_H                 ; 68    ; Signed Integer                                                                                                                                                                          ;
; PKT_QOS_L                 ; 68    ; Signed Integer                                                                                                                                                                          ;
; PKT_DATA_SIDEBAND_H       ; 66    ; Signed Integer                                                                                                                                                                          ;
; PKT_DATA_SIDEBAND_L       ; 66    ; Signed Integer                                                                                                                                                                          ;
; PKT_ADDR_SIDEBAND_H       ; 65    ; Signed Integer                                                                                                                                                                          ;
; PKT_ADDR_SIDEBAND_L       ; 65    ; Signed Integer                                                                                                                                                                          ;
; PKT_CACHE_H               ; 78    ; Signed Integer                                                                                                                                                                          ;
; PKT_CACHE_L               ; 75    ; Signed Integer                                                                                                                                                                          ;
; PKT_THREAD_ID_H           ; 71    ; Signed Integer                                                                                                                                                                          ;
; PKT_THREAD_ID_L           ; 71    ; Signed Integer                                                                                                                                                                          ;
; PKT_BEGIN_BURST           ; 67    ; Signed Integer                                                                                                                                                                          ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                          ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                          ;
; PKT_BURSTWRAP_H           ; 59    ; Signed Integer                                                                                                                                                                          ;
; PKT_BURSTWRAP_L           ; 59    ; Signed Integer                                                                                                                                                                          ;
; PKT_BYTE_CNT_H            ; 58    ; Signed Integer                                                                                                                                                                          ;
; PKT_BYTE_CNT_L            ; 56    ; Signed Integer                                                                                                                                                                          ;
; PKT_ADDR_H                ; 49    ; Signed Integer                                                                                                                                                                          ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                          ;
; PKT_BURST_SIZE_H          ; 62    ; Signed Integer                                                                                                                                                                          ;
; PKT_BURST_SIZE_L          ; 60    ; Signed Integer                                                                                                                                                                          ;
; PKT_BURST_TYPE_H          ; 64    ; Signed Integer                                                                                                                                                                          ;
; PKT_BURST_TYPE_L          ; 63    ; Signed Integer                                                                                                                                                                          ;
; PKT_TRANS_EXCLUSIVE       ; 55    ; Signed Integer                                                                                                                                                                          ;
; PKT_TRANS_LOCK            ; 54    ; Signed Integer                                                                                                                                                                          ;
; PKT_TRANS_COMPRESSED_READ ; 50    ; Signed Integer                                                                                                                                                                          ;
; PKT_TRANS_POSTED          ; 51    ; Signed Integer                                                                                                                                                                          ;
; PKT_TRANS_WRITE           ; 52    ; Signed Integer                                                                                                                                                                          ;
; PKT_TRANS_READ            ; 53    ; Signed Integer                                                                                                                                                                          ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                          ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                          ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                          ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                          ;
; PKT_SRC_ID_H              ; 69    ; Signed Integer                                                                                                                                                                          ;
; PKT_SRC_ID_L              ; 69    ; Signed Integer                                                                                                                                                                          ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                          ;
; PKT_DEST_ID_L             ; 70    ; Signed Integer                                                                                                                                                                          ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                          ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                          ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                          ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                          ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                          ;
; ST_CHANNEL_W              ; 2     ; Signed Integer                                                                                                                                                                          ;
; AV_BURSTCOUNT_W           ; 3     ; Signed Integer                                                                                                                                                                          ;
; ID                        ; 0     ; Signed Integer                                                                                                                                                                          ;
; SUPPRESS_0_BYTEEN_RSP     ; 0     ; Signed Integer                                                                                                                                                                          ;
; BURSTWRAP_VALUE           ; 1     ; Signed Integer                                                                                                                                                                          ;
; CACHE_VALUE               ; 0     ; Signed Integer                                                                                                                                                                          ;
; SECURE_ACCESS_BIT         ; 1     ; Signed Integer                                                                                                                                                                          ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                          ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                          ;
; PKT_BURSTWRAP_W           ; 1     ; Signed Integer                                                                                                                                                                          ;
; PKT_BYTE_CNT_W            ; 3     ; Signed Integer                                                                                                                                                                          ;
; PKT_PROTECTION_W          ; 3     ; Signed Integer                                                                                                                                                                          ;
; PKT_ADDR_W                ; 14    ; Signed Integer                                                                                                                                                                          ;
; PKT_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                          ;
; PKT_BYTEEN_W              ; 4     ; Signed Integer                                                                                                                                                                          ;
; PKT_SRC_ID_W              ; 1     ; Signed Integer                                                                                                                                                                          ;
; PKT_DEST_ID_W             ; 1     ; Signed Integer                                                                                                                                                                          ;
; PKT_BURST_SIZE_W          ; 3     ; Signed Integer                                                                                                                                                                          ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_nios_tx_dpram_s2_agent ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                  ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 67    ; Signed Integer                                                                                                                                                                        ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                        ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                        ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                        ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                        ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                        ;
; PKT_ADDR_H                ; 49    ; Signed Integer                                                                                                                                                                        ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_LOCK            ; 54    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_COMPRESSED_READ ; 50    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_POSTED          ; 51    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_WRITE           ; 52    ; Signed Integer                                                                                                                                                                        ;
; PKT_TRANS_READ            ; 53    ; Signed Integer                                                                                                                                                                        ;
; PKT_SRC_ID_H              ; 69    ; Signed Integer                                                                                                                                                                        ;
; PKT_SRC_ID_L              ; 69    ; Signed Integer                                                                                                                                                                        ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                        ;
; PKT_DEST_ID_L             ; 70    ; Signed Integer                                                                                                                                                                        ;
; PKT_BURSTWRAP_H           ; 59    ; Signed Integer                                                                                                                                                                        ;
; PKT_BURSTWRAP_L           ; 59    ; Signed Integer                                                                                                                                                                        ;
; PKT_BYTE_CNT_H            ; 58    ; Signed Integer                                                                                                                                                                        ;
; PKT_BYTE_CNT_L            ; 56    ; Signed Integer                                                                                                                                                                        ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                        ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                        ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                        ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                        ;
; PKT_BURST_SIZE_H          ; 62    ; Signed Integer                                                                                                                                                                        ;
; PKT_BURST_SIZE_L          ; 60    ; Signed Integer                                                                                                                                                                        ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                        ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                        ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                        ;
; ST_CHANNEL_W              ; 2     ; Signed Integer                                                                                                                                                                        ;
; ADDR_W                    ; 14    ; Signed Integer                                                                                                                                                                        ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                        ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                        ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                        ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                        ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                        ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                        ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                        ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                        ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                        ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                        ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                        ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_nios_tx_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                           ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 14    ; Signed Integer                                                                                                                                                                                                                                 ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                                 ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                                 ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                                 ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                                 ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                             ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                   ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                                   ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                                   ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                                   ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                                   ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                                   ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                                   ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                                   ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                                   ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                                   ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_udp_dpram_s2_agent ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                              ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 67    ; Signed Integer                                                                                                                                                                    ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                                                    ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                                                    ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                                                    ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                    ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                    ;
; PKT_ADDR_H                ; 49    ; Signed Integer                                                                                                                                                                    ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                                                    ;
; PKT_TRANS_LOCK            ; 54    ; Signed Integer                                                                                                                                                                    ;
; PKT_TRANS_COMPRESSED_READ ; 50    ; Signed Integer                                                                                                                                                                    ;
; PKT_TRANS_POSTED          ; 51    ; Signed Integer                                                                                                                                                                    ;
; PKT_TRANS_WRITE           ; 52    ; Signed Integer                                                                                                                                                                    ;
; PKT_TRANS_READ            ; 53    ; Signed Integer                                                                                                                                                                    ;
; PKT_SRC_ID_H              ; 69    ; Signed Integer                                                                                                                                                                    ;
; PKT_SRC_ID_L              ; 69    ; Signed Integer                                                                                                                                                                    ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                    ;
; PKT_DEST_ID_L             ; 70    ; Signed Integer                                                                                                                                                                    ;
; PKT_BURSTWRAP_H           ; 59    ; Signed Integer                                                                                                                                                                    ;
; PKT_BURSTWRAP_L           ; 59    ; Signed Integer                                                                                                                                                                    ;
; PKT_BYTE_CNT_H            ; 58    ; Signed Integer                                                                                                                                                                    ;
; PKT_BYTE_CNT_L            ; 56    ; Signed Integer                                                                                                                                                                    ;
; PKT_PROTECTION_H          ; 74    ; Signed Integer                                                                                                                                                                    ;
; PKT_PROTECTION_L          ; 72    ; Signed Integer                                                                                                                                                                    ;
; PKT_RESPONSE_STATUS_H     ; 80    ; Signed Integer                                                                                                                                                                    ;
; PKT_RESPONSE_STATUS_L     ; 79    ; Signed Integer                                                                                                                                                                    ;
; PKT_BURST_SIZE_H          ; 62    ; Signed Integer                                                                                                                                                                    ;
; PKT_BURST_SIZE_L          ; 60    ; Signed Integer                                                                                                                                                                    ;
; PKT_ORI_BURST_SIZE_L      ; 81    ; Signed Integer                                                                                                                                                                    ;
; PKT_ORI_BURST_SIZE_H      ; 83    ; Signed Integer                                                                                                                                                                    ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                    ;
; ST_CHANNEL_W              ; 2     ; Signed Integer                                                                                                                                                                    ;
; ADDR_W                    ; 14    ; Signed Integer                                                                                                                                                                    ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                                                    ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                                                    ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                                                    ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                                                    ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                                                    ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                                                    ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                                                    ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                                                    ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                                                    ;
; FIFO_DATA_W               ; 85    ; Signed Integer                                                                                                                                                                    ;
; ECC_ENABLE                ; 0     ; Signed Integer                                                                                                                                                                    ;
+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_udp_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                       ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 14    ; Signed Integer                                                                                                                                                                                                                             ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                                                             ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                                                             ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                                                             ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                                                             ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                         ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                               ;
; BITS_PER_SYMBOL     ; 85    ; Signed Integer                                                                                                                                                                               ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                                               ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                                               ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                               ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                                               ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                                               ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                                               ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                                               ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                                               ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                                               ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                                               ;
; DATA_WIDTH          ; 85    ; Signed Integer                                                                                                                                                                               ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                                               ;
+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router:router|nios2_mm_interconnect_1_router_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                          ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                ;
; DEFAULT_DESTID     ; 1     ; Signed Integer                                                                                                                                                                                                                                ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router_001:router_001|nios2_mm_interconnect_1_router_001_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router_001:router_002|nios2_mm_interconnect_1_router_001_default_decode:the_default_decode ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                                                                      ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                                                                            ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                                                                            ;
+--------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_traffic_limiter:enet_tx_msgdma_mm_read_limiter ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                                                         ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_TRANS_POSTED          ; 51    ; Signed Integer                                                                                                                                                                               ;
; PKT_DEST_ID_H             ; 70    ; Signed Integer                                                                                                                                                                               ;
; PKT_DEST_ID_L             ; 70    ; Signed Integer                                                                                                                                                                               ;
; PKT_SRC_ID_H              ; 69    ; Signed Integer                                                                                                                                                                               ;
; PKT_SRC_ID_L              ; 69    ; Signed Integer                                                                                                                                                                               ;
; PKT_BYTE_CNT_H            ; 58    ; Signed Integer                                                                                                                                                                               ;
; PKT_BYTE_CNT_L            ; 56    ; Signed Integer                                                                                                                                                                               ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                                                               ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                                                               ;
; PKT_TRANS_WRITE           ; 52    ; Signed Integer                                                                                                                                                                               ;
; PKT_TRANS_READ            ; 0     ; Signed Integer                                                                                                                                                                               ;
; ST_DATA_W                 ; 84    ; Signed Integer                                                                                                                                                                               ;
; ST_CHANNEL_W              ; 2     ; Signed Integer                                                                                                                                                                               ;
; MAX_OUTSTANDING_RESPONSES ; 1     ; Signed Integer                                                                                                                                                                               ;
; PIPELINED                 ; 0     ; Signed Integer                                                                                                                                                                               ;
; ENFORCE_ORDER             ; 1     ; Signed Integer                                                                                                                                                                               ;
; VALID_WIDTH               ; 2     ; Signed Integer                                                                                                                                                                               ;
; PREVENT_HAZARDS           ; 0     ; Signed Integer                                                                                                                                                                               ;
; SUPPORTS_POSTED_WRITES    ; 1     ; Signed Integer                                                                                                                                                                               ;
; SUPPORTS_NONPOSTED_WRITES ; 0     ; Signed Integer                                                                                                                                                                               ;
; REORDER                   ; 0     ; Signed Integer                                                                                                                                                                               ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb ;
+----------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                                                                                                                                                           ;
+----------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; NUM_REQUESTERS ; 2      ; Signed Integer                                                                                                                                                                                                 ;
; SCHEME         ; no-arb ; String                                                                                                                                                                                                         ;
; PIPELINE       ; 0      ; Signed Integer                                                                                                                                                                                                 ;
+----------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                          ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; WIDTH          ; 4     ; Signed Integer                                                                                                                                                                                                                                ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter ;
+-----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                  ;
+-----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                        ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                        ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                        ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                        ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                        ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                        ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                        ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                        ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                        ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                        ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                        ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                        ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                        ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                        ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                        ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                        ;
+-----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001 ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                                                                                      ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inUsePackets    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inDataWidth     ; 34    ; Signed Integer                                                                                                                                                                                            ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inErrorWidth    ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseEmptyPort  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                                                                                            ;
; inReadyLatency  ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outDataWidth    ; 34    ; Signed Integer                                                                                                                                                                                            ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outErrorWidth   ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseEmptyPort ; 0     ; Signed Integer                                                                                                                                                                                            ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                                                                                            ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                                                                                            ;
+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_2:mm_interconnect_2|altera_merlin_master_translator:enet_rx_msgdma_mm_write_translator ;
+-----------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name              ; Value ; Type                                                                                                                                                                                             ;
+-----------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                ; 11    ; Signed Integer                                                                                                                                                                                   ;
; AV_DATA_W                   ; 32    ; Signed Integer                                                                                                                                                                                   ;
; AV_BURSTCOUNT_W             ; 1     ; Signed Integer                                                                                                                                                                                   ;
; AV_BYTEENABLE_W             ; 4     ; Signed Integer                                                                                                                                                                                   ;
; UAV_ADDRESS_W               ; 11    ; Signed Integer                                                                                                                                                                                   ;
; UAV_BURSTCOUNT_W            ; 3     ; Signed Integer                                                                                                                                                                                   ;
; USE_BURSTCOUNT              ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_BEGINBURSTTRANSFER      ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_BEGINTRANSFER           ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_CHIPSELECT              ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_READ                    ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_READDATAVALID           ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_WRITE                   ; 1     ; Signed Integer                                                                                                                                                                                   ;
; USE_WAITREQUEST             ; 1     ; Signed Integer                                                                                                                                                                                   ;
; USE_WRITERESPONSE           ; 0     ; Signed Integer                                                                                                                                                                                   ;
; USE_READRESPONSE            ; 0     ; Signed Integer                                                                                                                                                                                   ;
; AV_REGISTERINCOMINGSIGNALS  ; 0     ; Signed Integer                                                                                                                                                                                   ;
; AV_SYMBOLS_PER_WORD         ; 4     ; Signed Integer                                                                                                                                                                                   ;
; AV_ADDRESS_SYMBOLS          ; 1     ; Signed Integer                                                                                                                                                                                   ;
; AV_CONSTANT_BURST_BEHAVIOR  ; 0     ; Signed Integer                                                                                                                                                                                   ;
; UAV_CONSTANT_BURST_BEHAVIOR ; 0     ; Signed Integer                                                                                                                                                                                   ;
; AV_BURSTCOUNT_SYMBOLS       ; 0     ; Signed Integer                                                                                                                                                                                   ;
; AV_LINEWRAPBURSTS           ; 0     ; Signed Integer                                                                                                                                                                                   ;
+-----------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_2:mm_interconnect_2|altera_merlin_slave_translator:enet_nios_rx_dpram_s2_translator ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                                                                                       ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 9     ; Signed Integer                                                                                                                                                                             ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                                                                                             ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                                                                                             ;
; AV_BYTEENABLE_W                ; 4     ; Signed Integer                                                                                                                                                                             ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                                                                                             ;
; AV_READLATENCY                 ; 1     ; Signed Integer                                                                                                                                                                             ;
; AV_READ_WAIT_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                                                                                             ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                                                                                             ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                                                                                             ;
; UAV_ADDRESS_W                  ; 11    ; Signed Integer                                                                                                                                                                             ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                                                                                             ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                                                                                             ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                                                                                             ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                                                                                             ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                                                                                             ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                                                                                             ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                                                                                             ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter ;
+-----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                                                      ;
+-----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+
; inBitsPerSymbol ; 8     ; Signed Integer                                                                                                                            ;
; inUsePackets    ; 1     ; Signed Integer                                                                                                                            ;
; inDataWidth     ; 32    ; Signed Integer                                                                                                                            ;
; inChannelWidth  ; 0     ; Signed Integer                                                                                                                            ;
; inErrorWidth    ; 6     ; Signed Integer                                                                                                                            ;
; inUseEmptyPort  ; 1     ; Signed Integer                                                                                                                            ;
; inUseValid      ; 1     ; Signed Integer                                                                                                                            ;
; inUseReady      ; 1     ; Signed Integer                                                                                                                            ;
; inReadyLatency  ; 2     ; Signed Integer                                                                                                                            ;
; outDataWidth    ; 32    ; Signed Integer                                                                                                                            ;
; outChannelWidth ; 0     ; Signed Integer                                                                                                                            ;
; outErrorWidth   ; 6     ; Signed Integer                                                                                                                            ;
; outUseEmptyPort ; 1     ; Signed Integer                                                                                                                            ;
; outUseValid     ; 1     ; Signed Integer                                                                                                                            ;
; outUseReady     ; 1     ; Signed Integer                                                                                                                            ;
; outReadyLatency ; 0     ; Signed Integer                                                                                                                            ;
+-----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                                             ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEPTH          ; 16    ; Signed Integer                                                                                                                                                                                                                                                                                   ;
; DATA_WIDTH     ; 42    ; Signed Integer                                                                                                                                                                                                                                                                                   ;
; ADDR_WIDTH     ; 4     ; Signed Integer                                                                                                                                                                                                                                                                                   ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller ;
+---------------------------+----------+---------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value    ; Type                                                                                                                      ;
+---------------------------+----------+---------------------------------------------------------------------------------------------------------------------------+
; NUM_RESET_INPUTS          ; 1        ; Signed Integer                                                                                                            ;
; USE_RESET_REQUEST_IN0     ; 0        ; Signed Integer                                                                                                            ;
; USE_RESET_REQUEST_IN1     ; 0        ; Signed Integer                                                                                                            ;
; USE_RESET_REQUEST_IN2     ; 0        ; Signed Integer                                                                                                            ;
; USE_RESET_REQUEST_IN3     ; 0        ; Signed Integer                                                                                                            ;
; USE_RESET_REQUEST_IN4     ; 0        ; Signed Integer                                                                                                            ;
; USE_RESET_REQUEST_IN5     ; 0        ; Signed Integer                                                                                                            ;
; USE_RESET_REQUEST_IN6     ; 0        ; Signed Integer                                                                                                            ;
; USE_RESET_REQUEST_IN7     ; 0        ; Signed Integer                                                                                                            ;
; USE_RESET_REQUEST_IN8     ; 0        ; Signed Integer                                                                                                            ;
; USE_RESET_REQUEST_IN9     ; 0        ; Signed Integer                                                                                                            ;
; USE_RESET_REQUEST_IN10    ; 0        ; Signed Integer                                                                                                            ;
; USE_RESET_REQUEST_IN11    ; 0        ; Signed Integer                                                                                                            ;
; USE_RESET_REQUEST_IN12    ; 0        ; Signed Integer                                                                                                            ;
; USE_RESET_REQUEST_IN13    ; 0        ; Signed Integer                                                                                                            ;
; USE_RESET_REQUEST_IN14    ; 0        ; Signed Integer                                                                                                            ;
; USE_RESET_REQUEST_IN15    ; 0        ; Signed Integer                                                                                                            ;
; OUTPUT_RESET_SYNC_EDGES   ; deassert ; String                                                                                                                    ;
; SYNC_DEPTH                ; 2        ; Signed Integer                                                                                                            ;
; RESET_REQUEST_PRESENT     ; 1        ; Signed Integer                                                                                                            ;
; RESET_REQ_WAIT_TIME       ; 1        ; Signed Integer                                                                                                            ;
; MIN_RST_ASSERTION_TIME    ; 3        ; Signed Integer                                                                                                            ;
; RESET_REQ_EARLY_DSRT_TIME ; 1        ; Signed Integer                                                                                                            ;
; ADAPT_RESET_REQUEST       ; 0        ; Signed Integer                                                                                                            ;
+---------------------------+----------+---------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                               ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ASYNC_RESET    ; 1     ; Unsigned Binary                                                                                                                                                                    ;
; DEPTH          ; 2     ; Signed Integer                                                                                                                                                                     ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ASYNC_RESET    ; 0     ; Signed Integer                                                                                                                                                                         ;
; DEPTH          ; 2     ; Signed Integer                                                                                                                                                                         ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001 ;
+---------------------------+----------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value    ; Type                                                                                                                          ;
+---------------------------+----------+-------------------------------------------------------------------------------------------------------------------------------+
; NUM_RESET_INPUTS          ; 1        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN0     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN1     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN2     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN3     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN4     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN5     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN6     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN7     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN8     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN9     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN10    ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN11    ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN12    ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN13    ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN14    ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN15    ; 0        ; Signed Integer                                                                                                                ;
; OUTPUT_RESET_SYNC_EDGES   ; deassert ; String                                                                                                                        ;
; SYNC_DEPTH                ; 2        ; Signed Integer                                                                                                                ;
; RESET_REQUEST_PRESENT     ; 1        ; Signed Integer                                                                                                                ;
; RESET_REQ_WAIT_TIME       ; 1        ; Signed Integer                                                                                                                ;
; MIN_RST_ASSERTION_TIME    ; 3        ; Signed Integer                                                                                                                ;
; RESET_REQ_EARLY_DSRT_TIME ; 1        ; Signed Integer                                                                                                                ;
; ADAPT_RESET_REQUEST       ; 0        ; Signed Integer                                                                                                                ;
+---------------------------+----------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ASYNC_RESET    ; 1     ; Unsigned Binary                                                                                                                                                                        ;
; DEPTH          ; 2     ; Signed Integer                                                                                                                                                                         ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                       ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ASYNC_RESET    ; 0     ; Signed Integer                                                                                                                                                                             ;
; DEPTH          ; 2     ; Signed Integer                                                                                                                                                                             ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002 ;
+---------------------------+----------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value    ; Type                                                                                                                          ;
+---------------------------+----------+-------------------------------------------------------------------------------------------------------------------------------+
; NUM_RESET_INPUTS          ; 2        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN0     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN1     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN2     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN3     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN4     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN5     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN6     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN7     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN8     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN9     ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN10    ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN11    ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN12    ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN13    ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN14    ; 0        ; Signed Integer                                                                                                                ;
; USE_RESET_REQUEST_IN15    ; 0        ; Signed Integer                                                                                                                ;
; OUTPUT_RESET_SYNC_EDGES   ; deassert ; String                                                                                                                        ;
; SYNC_DEPTH                ; 2        ; Signed Integer                                                                                                                ;
; RESET_REQUEST_PRESENT     ; 1        ; Signed Integer                                                                                                                ;
; RESET_REQ_WAIT_TIME       ; 1        ; Signed Integer                                                                                                                ;
; MIN_RST_ASSERTION_TIME    ; 3        ; Signed Integer                                                                                                                ;
; RESET_REQ_EARLY_DSRT_TIME ; 1        ; Signed Integer                                                                                                                ;
; ADAPT_RESET_REQUEST       ; 0        ; Signed Integer                                                                                                                ;
+---------------------------+----------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_sync_uq1 ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ASYNC_RESET    ; 1     ; Unsigned Binary                                                                                                                                                                        ;
; DEPTH          ; 2     ; Signed Integer                                                                                                                                                                         ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                       ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ASYNC_RESET    ; 0     ; Signed Integer                                                                                                                                                                             ;
; DEPTH          ; 2     ; Signed Integer                                                                                                                                                                             ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+--------------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                                     ;
+------------------------+--------------+--------------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                               ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                                             ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                                             ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                                           ;
; WIDTH                  ; 1            ; Signed Integer                                                                                                           ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                                  ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                                  ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                                  ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                                  ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                                  ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                                  ;
+------------------------+--------------+--------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER ;
+-----------------------+------------------+-------------------------------------------------------------------------------------------------------+
; Parameter Name        ; Value            ; Type                                                                                                  ;
+-----------------------+------------------+-------------------------------------------------------------------------------------------------------+
; x_reset_active        ; '0'              ; Enumerated                                                                                            ;
; x_sc_timeout          ; 0000001111100111 ; Unsigned Binary                                                                                       ;
; x_sc_fifo_xfer_level  ; 50               ; Signed Integer                                                                                        ;
; x_sc_fifo_depth_size  ; 7                ; Signed Integer                                                                                        ;
; x_daq_timeout         ; 0001001110000111 ; Unsigned Binary                                                                                       ;
; x_daq_fifo_xfer_level ; 300              ; Signed Integer                                                                                        ;
; x_daq_fifo_depth_size ; 16               ; Signed Integer                                                                                        ;
+-----------------------+------------------+-------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_CSR_SM:C_MSGDMA_CSR_SM ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                      ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                                                                                                ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                                                                                                  ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                                            ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                                      ;
; x_dpram_addr_size ; 10    ; Signed Integer                                                                                                                                  ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DISPATCHER:C_MSGDMA_DISPATCHER ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                              ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component ;
+-------------------------+-----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value     ; Type                                                                                                                                                              ;
+-------------------------+-----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON        ; AUTO_CARRY                                                                                                                                                        ;
; IGNORE_CARRY_BUFFERS    ; OFF       ; IGNORE_CARRY                                                                                                                                                      ;
; AUTO_CASCADE_CHAINS     ; ON        ; AUTO_CASCADE                                                                                                                                                      ;
; IGNORE_CASCADE_BUFFERS  ; OFF       ; IGNORE_CASCADE                                                                                                                                                    ;
; lpm_width               ; 3         ; Signed Integer                                                                                                                                                    ;
; LPM_NUMWORDS            ; 4         ; Signed Integer                                                                                                                                                    ;
; LPM_WIDTHU              ; 2         ; Signed Integer                                                                                                                                                    ;
; LPM_SHOWAHEAD           ; OFF       ; Untyped                                                                                                                                                           ;
; UNDERFLOW_CHECKING      ; ON        ; Untyped                                                                                                                                                           ;
; OVERFLOW_CHECKING       ; ON        ; Untyped                                                                                                                                                           ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF       ; Untyped                                                                                                                                                           ;
; ADD_RAM_OUTPUT_REGISTER ; OFF       ; Untyped                                                                                                                                                           ;
; ALMOST_FULL_VALUE       ; 0         ; Untyped                                                                                                                                                           ;
; ALMOST_EMPTY_VALUE      ; 0         ; Untyped                                                                                                                                                           ;
; ENABLE_ECC              ; FALSE     ; Untyped                                                                                                                                                           ;
; USE_EAB                 ; OFF       ; Untyped                                                                                                                                                           ;
; MAXIMIZE_SPEED          ; 5         ; Untyped                                                                                                                                                           ;
; DEVICE_FAMILY           ; Cyclone V ; Untyped                                                                                                                                                           ;
; OPTIMIZE_FOR_SPEED      ; 5         ; Untyped                                                                                                                                                           ;
; CBXI_PARAMETER          ; NOTHING   ; Untyped                                                                                                                                                           ;
+-------------------------+-----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFO_CHECK:C_SC_FIFO_CHECK ;
+-------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value            ; Type                                                                                                                                     ;
+-------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'              ; Enumerated                                                                                                                               ;
; x_timeout         ; 0000001111100111 ; Unsigned Binary                                                                                                                          ;
; x_fifo_xfer_level ; 50               ; Signed Integer                                                                                                                           ;
; x_fifo_depth_size ; 7                ; Signed Integer                                                                                                                           ;
+-------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFO_CHECK:C_DAQ_FIFO_CHECK ;
+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value            ; Type                                                                                                                                      ;
+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'              ; Enumerated                                                                                                                                ;
; x_timeout         ; 0001001110000111 ; Unsigned Binary                                                                                                                           ;
; x_fifo_xfer_level ; 300              ; Signed Integer                                                                                                                            ;
; x_fifo_depth_size ; 16               ; Signed Integer                                                                                                                            ;
+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                       ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                    ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                 ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                               ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                               ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                             ;
; LPM_WIDTH               ; 32          ; Signed Integer                                                                             ;
; LPM_NUMWORDS            ; 128         ; Signed Integer                                                                             ;
; LPM_WIDTHU              ; 7           ; Signed Integer                                                                             ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                    ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                    ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                    ;
; USE_EAB                 ; ON          ; Untyped                                                                                    ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                    ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                    ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                    ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                    ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                             ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                             ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                    ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                    ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                    ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                    ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                    ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                    ;
; CBXI_PARAMETER          ; dcfifo_p6n1 ; Untyped                                                                                    ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                       ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                 ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                               ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                               ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                             ;
; lpm_width               ; 32          ; Signed Integer                                                                             ;
; LPM_NUMWORDS            ; 64          ; Signed Integer                                                                             ;
; LPM_WIDTHU              ; 6           ; Signed Integer                                                                             ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                    ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                    ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                    ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                                    ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                    ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                                                    ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                                    ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                    ;
; USE_EAB                 ; ON          ; Untyped                                                                                    ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                    ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                    ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                                                    ;
; CBXI_PARAMETER          ; scfifo_7l91 ; Untyped                                                                                    ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC ;
+----------------+-------+------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                     ;
+----------------+-------+------------------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                               ;
+----------------+-------+------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC ;
+-----------------+-------+-------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                  ;
+-----------------+-------+-------------------------------------------------------------------------------------------------------+
; x_reset_active  ; '0'   ; Enumerated                                                                                            ;
; x_din_byte_nb   ; 2     ; Signed Integer                                                                                        ;
; x_crc_din_width ; 4     ; Signed Integer                                                                                        ;
; x_crc_width     ; 16    ; Signed Integer                                                                                        ;
+-----------------+-------+-------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER ;
+-------------------------+-------+-------------------------------------------------------------------------+
; Parameter Name          ; Value ; Type                                                                    ;
+-------------------------+-------+-------------------------------------------------------------------------+
; x_reset_active          ; '0'   ; Enumerated                                                              ;
; x_nb_config_word16      ; 1     ; Signed Integer                                                          ;
; x_nb_config_word16_size ; 1     ; Signed Integer                                                          ;
; x_nb_dpram_size         ; 1     ; Signed Integer                                                          ;
; x_nb_devices_size       ; 0     ; Signed Integer                                                          ;
; x_fifo_tx_size          ; 7     ; Signed Integer                                                          ;
; x_fifo_tx_wr_duration   ; 00    ; Unsigned Binary                                                         ;
; x_enable_timeout        ; '1'   ; Enumerated                                                              ;
; x_timeout_ms_size       ; 10    ; Signed Integer                                                          ;
; x_timeout_ms            ; 500   ; Signed Integer                                                          ;
+-------------------------+-------+-------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER ;
+-----------------------------+-------+----------------------------------------------------------------+
; Parameter Name              ; Value ; Type                                                           ;
+-----------------------------+-------+----------------------------------------------------------------+
; x_reset_active              ; '0'   ; Enumerated                                                     ;
; x_nb_config_word16          ; 1     ; Signed Integer                                                 ;
; x_nb_dpram_size             ; 1     ; Signed Integer                                                 ;
; x_nb_devices_size           ; 0     ; Signed Integer                                                 ;
; x_chain_en                  ; '0'   ; Enumerated                                                     ;
; x_fifo_rx_rd_duration       ; 00    ; Unsigned Binary                                                ;
; x_enable_timeout            ; '1'   ; Enumerated                                                     ;
; x_timeout_prescaler_ms_size ; 16    ; Signed Integer                                                 ;
; x_timeout_prescaler_ms_nb   ; 39998 ; Signed Integer                                                 ;
; x_timeout_ms_size           ; 10    ; Signed Integer                                                 ;
; x_timeout_ms                ; 500   ; Signed Integer                                                 ;
+-----------------------------+-------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component ;
+-------------------------+-------------+----------------------------------------------------+
; Parameter Name          ; Value       ; Type                                               ;
+-------------------------+-------------+----------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                            ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                         ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                       ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                       ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                     ;
; LPM_WIDTH               ; 33          ; Signed Integer                                     ;
; LPM_NUMWORDS            ; 65536       ; Signed Integer                                     ;
; LPM_WIDTHU              ; 16          ; Signed Integer                                     ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                            ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                            ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                            ;
; USE_EAB                 ; ON          ; Untyped                                            ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                            ;
; ENABLE_ECC              ; FALSE       ; Untyped                                            ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                            ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                            ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                     ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                     ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                            ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                            ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                            ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                            ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                            ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                            ;
; CBXI_PARAMETER          ; dcfifo_kvr1 ; Untyped                                            ;
+-------------------------+-------------+----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS ;
+----------------+-------+--------------------------------------------+
; Parameter Name ; Value ; Type                                       ;
+----------------+-------+--------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                 ;
+----------------+-------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET ;
+---------------------+-------+----------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                       ;
+---------------------+-------+----------------------------------------------------------------------------+
; x_reset_active      ; '0'   ; Enumerated                                                                 ;
; x_nb_addr_bits      ; 1     ; Signed Integer                                                             ;
; x_nb_data_word      ; 2     ; Signed Integer                                                             ;
; x_user_set_cmd_size ; 16    ; Signed Integer                                                             ;
+---------------------+-------+----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET ;
+---------------------+-------+----------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                       ;
+---------------------+-------+----------------------------------------------------------------------------+
; x_reset_active      ; '0'   ; Enumerated                                                                 ;
; x_nb_addr_bits      ; 1     ; Signed Integer                                                             ;
; x_nb_data_word      ; 2     ; Signed Integer                                                             ;
; x_user_get_cmd_size ; 4     ; Signed Integer                                                             ;
+---------------------+-------+----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET ;
+---------------------+-------+-----------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                        ;
+---------------------+-------+-----------------------------------------------------------------------------+
; x_reset_active      ; '0'   ; Enumerated                                                                  ;
; x_nb_addr_bits      ; 4     ; Signed Integer                                                              ;
; x_nb_data_word      ; 10    ; Signed Integer                                                              ;
; x_user_set_cmd_size ; 16    ; Signed Integer                                                              ;
+---------------------+-------+-----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET ;
+---------------------+-------+-----------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                        ;
+---------------------+-------+-----------------------------------------------------------------------------+
; x_reset_active      ; '0'   ; Enumerated                                                                  ;
; x_nb_addr_bits      ; 4     ; Signed Integer                                                              ;
; x_nb_data_word      ; 10    ; Signed Integer                                                              ;
; x_user_get_cmd_size ; 4     ; Signed Integer                                                              ;
+---------------------+-------+-----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET ;
+---------------------+-------+-------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                          ;
+---------------------+-------+-------------------------------------------------------------------------------+
; x_reset_active      ; '0'   ; Enumerated                                                                    ;
; x_nb_addr_bits      ; 2     ; Signed Integer                                                                ;
; x_nb_data_word      ; 3     ; Signed Integer                                                                ;
; x_user_set_cmd_size ; 16    ; Signed Integer                                                                ;
+---------------------+-------+-------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET ;
+---------------------+-------+-------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                          ;
+---------------------+-------+-------------------------------------------------------------------------------+
; x_reset_active      ; '0'   ; Enumerated                                                                    ;
; x_nb_addr_bits      ; 2     ; Signed Integer                                                                ;
; x_nb_data_word      ; 3     ; Signed Integer                                                                ;
; x_user_get_cmd_size ; 4     ; Signed Integer                                                                ;
+---------------------+-------+-------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET ;
+---------------------+-------+-------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                          ;
+---------------------+-------+-------------------------------------------------------------------------------+
; x_reset_active      ; '0'   ; Enumerated                                                                    ;
; x_nb_addr_bits      ; 4     ; Signed Integer                                                                ;
; x_nb_data_word      ; 15    ; Signed Integer                                                                ;
; x_user_set_cmd_size ; 16    ; Signed Integer                                                                ;
+---------------------+-------+-------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SETGET_ACK:C_GET_ACK ;
+----------------+-------+--------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                     ;
+----------------+-------+--------------------------------------------------------------------------+
; x_user_nb      ; 3     ; Signed Integer                                                           ;
+----------------+-------+--------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER ;
+----------------------+-------+------------------------------------------+
; Parameter Name       ; Value ; Type                                     ;
+----------------------+-------+------------------------------------------+
; x_reset_active       ; '0'   ; Enumerated                               ;
; x_l2_fifo_depth_size ; 16    ; Signed Integer                           ;
; x_l2_fifo_not_full   ; 53248 ; Signed Integer                           ;
; x_l1_fifo_depth_size ; 11    ; Signed Integer                           ;
; x_nbmodules          ; 8     ; Signed Integer                           ;
+----------------------+-------+------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM ;
+----------------------+-------+------------------------------------------------------------+
; Parameter Name       ; Value ; Type                                                       ;
+----------------------+-------+------------------------------------------------------------+
; x_reset_active       ; '0'   ; Enumerated                                                 ;
; x_l2_fifo_depth_size ; 16    ; Signed Integer                                             ;
; x_l2_fifo_not_full   ; 53248 ; Signed Integer                                             ;
; x_nbmodules          ; 8     ; Signed Integer                                             ;
+----------------------+-------+------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM ;
+-------------------+-------+----------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                       ;
+-------------------+-------+----------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                 ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                             ;
; x_nbmodules       ; 8     ; Signed Integer                                                             ;
+-------------------+-------+----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                          ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                    ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                          ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                    ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                          ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                    ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                          ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                    ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                          ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                    ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                          ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                    ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                          ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                    ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                          ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                    ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                            ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                      ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                  ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                            ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                      ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                  ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                            ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                      ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                  ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                            ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                      ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                  ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                            ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                      ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                  ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                            ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                      ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                  ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                            ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                      ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                  ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                            ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                      ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                  ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                         ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                      ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                               ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                               ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                               ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                               ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                      ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                      ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                      ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                      ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                      ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                      ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                      ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                      ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                      ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                      ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                      ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                         ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                      ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                               ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                               ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                               ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                               ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                      ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                      ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                      ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                      ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                      ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                      ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                      ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                      ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                      ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                      ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                      ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                         ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                      ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                               ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                               ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                               ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                               ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                      ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                      ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                      ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                      ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                      ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                      ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                      ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                      ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                      ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                      ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                      ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                         ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                      ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                               ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                               ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                               ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                               ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                      ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                      ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                      ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                      ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                      ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                      ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                      ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                      ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                      ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                      ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                      ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                         ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                      ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                               ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                               ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                               ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                               ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                      ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                      ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                      ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                      ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                      ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                      ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                      ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                      ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                      ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                      ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                      ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                         ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                      ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                               ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                               ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                               ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                               ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                      ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                      ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                      ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                      ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                      ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                      ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                      ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                      ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                      ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                      ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                      ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                         ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                      ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                               ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                               ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                               ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                               ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                      ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                      ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                      ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                      ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                      ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                      ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                      ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                      ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                      ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                      ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                      ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                         ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                      ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                               ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                               ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                               ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                               ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                      ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                      ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                      ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                      ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                      ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                      ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                      ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                      ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                      ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                      ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                      ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                           ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                        ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                 ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                                 ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                 ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                        ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                        ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                        ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                        ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                        ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                        ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                        ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                        ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                           ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                        ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                 ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                                 ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                 ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                        ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                        ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                        ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                        ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                        ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                        ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                        ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                        ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                           ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                        ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                 ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                                 ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                 ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                        ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                        ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                        ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                        ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                        ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                        ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                        ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                        ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                           ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                        ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                 ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                                 ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                 ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                        ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                        ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                        ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                        ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                        ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                        ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                        ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                        ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                           ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                        ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                 ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                                 ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                 ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                        ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                        ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                        ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                        ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                        ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                        ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                        ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                        ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                           ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                        ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                 ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                                 ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                 ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                        ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                        ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                        ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                        ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                        ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                        ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                        ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                        ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                           ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                        ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                 ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                                 ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                 ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                        ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                        ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                        ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                        ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                        ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                        ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                        ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                        ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                           ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                        ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                 ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                                 ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                 ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                        ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                        ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                        ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                        ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                        ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                        ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                        ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                        ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC ;
+----------------+-------+-------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                    ;
+----------------+-------+-------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                              ;
+----------------+-------+-------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                  ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                                            ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0 ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                                                          ;
; x_module_nb    ; 4     ; Signed Integer                                                                                                      ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1 ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                                                          ;
; x_module_nb    ; 4     ; Signed Integer                                                                                                      ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo|altsyncram:mem_rtl_0 ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                                                                                                                                                                                                                                   ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                                                                                                                                                                                                                ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                                                                                                                                                                                                             ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                                                                                                                                                                                                           ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                                                                                                                                                                                                           ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                                                                                                                                                                                                         ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                                                                                                                                                                                                                ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                                                                                                                                                                                                                                ;
; WIDTH_A                            ; 42                   ; Untyped                                                                                                                                                                                                                                                                                ;
; WIDTHAD_A                          ; 4                    ; Untyped                                                                                                                                                                                                                                                                                ;
; NUMWORDS_A                         ; 16                   ; Untyped                                                                                                                                                                                                                                                                                ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                                                                                                                ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                ;
; WIDTH_B                            ; 42                   ; Untyped                                                                                                                                                                                                                                                                                ;
; WIDTHAD_B                          ; 4                    ; Untyped                                                                                                                                                                                                                                                                                ;
; NUMWORDS_B                         ; 16                   ; Untyped                                                                                                                                                                                                                                                                                ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                                                                                                                                                                                                                                ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                                                                                                                                                                                                                                ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                                                                                                                                                                                                                                ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                                                                                                                                                                                                                                ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                                                                                                                                                                                                                                ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                                                                                                                                                                                                                                ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                                                                                                                                                                                                                ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                                                                                                                                                                                                                                ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                                                                                                                                                                                                                                ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                                                                                                                                                                                                                ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                                                                                                                                                                                                                                ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                                                                                                                                                                                                                                                ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                                                                                                                ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                                                                                                                                                                                                                ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                                                                                                                                                                                                                                                ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                                                                                                                                                                                                                ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                                                                                                                                                                                                                                                                ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                                                                                                                                                                                                                ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                                                                                                                                                                                                                ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                                                                                                                                                                                                                ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                                                                                                                                                                                                                ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                                                                                                                ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                                                                                                                                                                                                                ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                                                                                                                                                                                                                ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                                                                                                                                                                                                                                                                ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                                                                                                                                                                                                                                ;
; DEVICE_FAMILY                      ; Cyclone V            ; Untyped                                                                                                                                                                                                                                                                                ;
; CBXI_PARAMETER                     ; altsyncram_23n1      ; Untyped                                                                                                                                                                                                                                                                                ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; dcfifo Parameter Settings by Entity Instance                                                                                                                                                                                                                                ;
+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name                       ; Value                                                                                                                                                                                                                                          ;
+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Number of entity instances ; 19                                                                                                                                                                                                                                             ;
; Entity Instance            ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 32                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component                                                                                                                                                          ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 32                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 128                                                                                                                                                                                                                                            ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component                                                                                                                                                                                                  ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 33                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 65536                                                                                                                                                                                                                                          ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                        ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 26                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                        ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 26                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                        ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 26                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                        ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 26                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                        ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 26                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                        ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 26                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                        ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 26                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                        ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 26                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                      ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 26                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                      ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 26                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                      ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 26                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                      ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 26                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                      ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 26                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                      ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 26                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                      ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 26                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                      ;
;     -- FIFO Type           ; Dual Clock                                                                                                                                                                                                                                     ;
;     -- LPM_WIDTH           ; 26                                                                                                                                                                                                                                             ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                                                                                                                                           ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                                                            ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                                                             ;
+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; scfifo Parameter Settings by Entity Instance                                                                                                                                                                                            ;
+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name                       ; Value                                                                                                                                                                                                      ;
+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Number of entity instances ; 7                                                                                                                                                                                                          ;
; Entity Instance            ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO ;
;     -- FIFO Type           ; Single Clock                                                                                                                                                                                               ;
;     -- lpm_width           ; 41                                                                                                                                                                                                         ;
;     -- LPM_NUMWORDS        ; 32                                                                                                                                                                                                         ;
;     -- LPM_SHOWAHEAD       ; ON                                                                                                                                                                                                         ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                         ;
; Entity Instance            ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo                             ;
;     -- FIFO Type           ; Single Clock                                                                                                                                                                                               ;
;     -- lpm_width           ; 42                                                                                                                                                                                                         ;
;     -- LPM_NUMWORDS        ; 32                                                                                                                                                                                                         ;
;     -- LPM_SHOWAHEAD       ; ON                                                                                                                                                                                                         ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                         ;
; Entity Instance            ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo                               ;
;     -- FIFO Type           ; Single Clock                                                                                                                                                                                               ;
;     -- lpm_width           ; 45                                                                                                                                                                                                         ;
;     -- LPM_NUMWORDS        ; 32                                                                                                                                                                                                         ;
;     -- LPM_SHOWAHEAD       ; ON                                                                                                                                                                                                         ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                         ;
; Entity Instance            ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo                          ;
;     -- FIFO Type           ; Single Clock                                                                                                                                                                                               ;
;     -- lpm_width           ; 8                                                                                                                                                                                                          ;
;     -- LPM_NUMWORDS        ; 64                                                                                                                                                                                                         ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                        ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                         ;
; Entity Instance            ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r|scfifo:rfifo                          ;
;     -- FIFO Type           ; Single Clock                                                                                                                                                                                               ;
;     -- lpm_width           ; 8                                                                                                                                                                                                          ;
;     -- LPM_NUMWORDS        ; 64                                                                                                                                                                                                         ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                        ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                         ;
; Entity Instance            ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component                                                 ;
;     -- FIFO Type           ; Single Clock                                                                                                                                                                                               ;
;     -- lpm_width           ; 3                                                                                                                                                                                                          ;
;     -- LPM_NUMWORDS        ; 4                                                                                                                                                                                                          ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                        ;
;     -- USE_EAB             ; OFF                                                                                                                                                                                                        ;
; Entity Instance            ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component                                                                                                                      ;
;     -- FIFO Type           ; Single Clock                                                                                                                                                                                               ;
;     -- lpm_width           ; 32                                                                                                                                                                                                         ;
;     -- LPM_NUMWORDS        ; 64                                                                                                                                                                                                         ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                                                                                                        ;
;     -- USE_EAB             ; ON                                                                                                                                                                                                         ;
+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance                                                                                                                                                                                                                                                                                                                                  ;
+-------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name                                      ; Value                                                                                                                                                                                                                                                                                                                                 ;
+-------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Number of entity instances                ; 12                                                                                                                                                                                                                                                                                                                                    ;
; Entity Instance                           ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram|altsyncram:the_altsyncram                                                                                                                                                                                    ;
;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                                                                                                                                                                                                                                       ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                                                                                                                                                    ;
;     -- NUMWORDS_A                         ; 512                                                                                                                                                                                                                                                                                                                                   ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- WIDTH_B                            ; 32                                                                                                                                                                                                                                                                                                                                    ;
;     -- NUMWORDS_B                         ; 512                                                                                                                                                                                                                                                                                                                                   ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                                                                                                                                                ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                                                                                                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                                                                                                                                             ;
; Entity Instance                           ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_tx_dpram:enet_nios_tx_dpram|altsyncram:the_altsyncram                                                                                                                                                                                    ;
;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                                                                                                                                                                                                                                       ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                                                                                                                                                    ;
;     -- NUMWORDS_A                         ; 512                                                                                                                                                                                                                                                                                                                                   ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- WIDTH_B                            ; 32                                                                                                                                                                                                                                                                                                                                    ;
;     -- NUMWORDS_B                         ; 512                                                                                                                                                                                                                                                                                                                                   ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                                                                                                                                                ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                                                                                                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                                                                                                                                             ;
; Entity Instance                           ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram                                                                           ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                                                                                                                                             ;
;     -- WIDTH_A                            ; 128                                                                                                                                                                                                                                                                                                                                   ;
;     -- NUMWORDS_A                         ; 16                                                                                                                                                                                                                                                                                                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- WIDTH_B                            ; 128                                                                                                                                                                                                                                                                                                                                   ;
;     -- NUMWORDS_B                         ; 16                                                                                                                                                                                                                                                                                                                                    ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                                                                                                                                                ;
;     -- OUTDATA_REG_B                      ; CLOCK0                                                                                                                                                                                                                                                                                                                                ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                                                                                                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                                                                                                                                             ;
; Entity Instance                           ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram                                                                          ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                                                                                                                                             ;
;     -- WIDTH_A                            ; 128                                                                                                                                                                                                                                                                                                                                   ;
;     -- NUMWORDS_A                         ; 16                                                                                                                                                                                                                                                                                                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- WIDTH_B                            ; 128                                                                                                                                                                                                                                                                                                                                   ;
;     -- NUMWORDS_B                         ; 16                                                                                                                                                                                                                                                                                                                                    ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                                                                                                                                                ;
;     -- OUTDATA_REG_B                      ; CLOCK0                                                                                                                                                                                                                                                                                                                                ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                                                                                                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                                                                                                                                             ;
; Entity Instance                           ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram                                                                           ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                                                                                                                                             ;
;     -- WIDTH_A                            ; 128                                                                                                                                                                                                                                                                                                                                   ;
;     -- NUMWORDS_A                         ; 16                                                                                                                                                                                                                                                                                                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- WIDTH_B                            ; 128                                                                                                                                                                                                                                                                                                                                   ;
;     -- NUMWORDS_B                         ; 16                                                                                                                                                                                                                                                                                                                                    ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                                                                                                                                                ;
;     -- OUTDATA_REG_B                      ; CLOCK0                                                                                                                                                                                                                                                                                                                                ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                                                                                                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                                                                                                                                             ;
; Entity Instance                           ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram                                                                          ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                                                                                                                                             ;
;     -- WIDTH_A                            ; 128                                                                                                                                                                                                                                                                                                                                   ;
;     -- NUMWORDS_A                         ; 16                                                                                                                                                                                                                                                                                                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- WIDTH_B                            ; 128                                                                                                                                                                                                                                                                                                                                   ;
;     -- NUMWORDS_B                         ; 16                                                                                                                                                                                                                                                                                                                                    ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                                                                                                                                                ;
;     -- OUTDATA_REG_B                      ; CLOCK0                                                                                                                                                                                                                                                                                                                                ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                                                                                                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                                                                                                                                             ;
; Entity Instance                           ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram|altsyncram:the_altsyncram                                                                                                                                                                                            ;
;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                                                                                                                                                                                                                                       ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                                                                                                                                                    ;
;     -- NUMWORDS_A                         ; 1024                                                                                                                                                                                                                                                                                                                                  ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- WIDTH_B                            ; 32                                                                                                                                                                                                                                                                                                                                    ;
;     -- NUMWORDS_B                         ; 1024                                                                                                                                                                                                                                                                                                                                  ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                                                                                                                                                ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                                                                                                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                                                                                                                                             ;
; Entity Instance                           ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a|altsyncram:the_altsyncram                                                                                                                   ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                                                                                                                                             ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                                                                                                                                                    ;
;     -- NUMWORDS_A                         ; 32                                                                                                                                                                                                                                                                                                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- WIDTH_B                            ; 32                                                                                                                                                                                                                                                                                                                                    ;
;     -- NUMWORDS_B                         ; 32                                                                                                                                                                                                                                                                                                                                    ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                                                                                                                                                ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                                                                                                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                                                                                                                                             ;
; Entity Instance                           ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_b_module:nios2_nios2_cpu_register_bank_b|altsyncram:the_altsyncram                                                                                                                   ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                                                                                                                                             ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                                                                                                                                                    ;
;     -- NUMWORDS_A                         ; 32                                                                                                                                                                                                                                                                                                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- WIDTH_B                            ; 32                                                                                                                                                                                                                                                                                                                                    ;
;     -- NUMWORDS_B                         ; 32                                                                                                                                                                                                                                                                                                                                    ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                                                                                                                                                ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                                                                                                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                                                                                                                                             ;
; Entity Instance                           ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram|altsyncram:the_altsyncram ;
;     -- OPERATION_MODE                     ; SINGLE_PORT                                                                                                                                                                                                                                                                                                                           ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                                                                                                                                                    ;
;     -- NUMWORDS_A                         ; 256                                                                                                                                                                                                                                                                                                                                   ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- WIDTH_B                            ; 1                                                                                                                                                                                                                                                                                                                                     ;
;     -- NUMWORDS_B                         ; 1                                                                                                                                                                                                                                                                                                                                     ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                                                                                                                                                                                                                                                ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                                                                                                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                                                                                                                                             ;
; Entity Instance                           ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram                                                                                                                                                                                                    ;
;     -- OPERATION_MODE                     ; SINGLE_PORT                                                                                                                                                                                                                                                                                                                           ;
;     -- WIDTH_A                            ; 32                                                                                                                                                                                                                                                                                                                                    ;
;     -- NUMWORDS_A                         ; 32768                                                                                                                                                                                                                                                                                                                                 ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- WIDTH_B                            ; 1                                                                                                                                                                                                                                                                                                                                     ;
;     -- NUMWORDS_B                         ; 1                                                                                                                                                                                                                                                                                                                                     ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                                                                                                                                                                                                                                                ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                                                                                                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                                                                                                                                                                                                                                             ;
; Entity Instance                           ; ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo|altsyncram:mem_rtl_0                                     ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                                                                                                                                                                                                                                                             ;
;     -- WIDTH_A                            ; 42                                                                                                                                                                                                                                                                                                                                    ;
;     -- NUMWORDS_A                         ; 16                                                                                                                                                                                                                                                                                                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- WIDTH_B                            ; 42                                                                                                                                                                                                                                                                                                                                    ;
;     -- NUMWORDS_B                         ; 16                                                                                                                                                                                                                                                                                                                                    ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                                                                                                                                                                                                                                                                ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                                                                                                                                                                                                                                          ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                                                                                                                                                                                                                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                                                                                                                                                                                                                                                                              ;
+-------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX"          ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX"          ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX"          ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX"          ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX"          ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX"          ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX"          ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX"          ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED"            ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED"            ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED"            ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED"            ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED"            ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED"            ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED"            ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED"            ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER"                                                                        ;
+---------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                ; Type   ; Severity ; Details                                                                             ;
+---------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_sct_cmd1_0_g      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_detect_state0_g   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_rx_detect_reset_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_pcsm_state0_g     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_pcsm_ack01_g      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_pcsm_state_ack_g  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_loopready_g       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fifo_full_g       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_pcsm_busy0_g      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------------------+--------+----------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET"                                   ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                             ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_sel_user_set_cmd ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_user_set_cmd     ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_busy             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET" ;
+--------------------------+-------+----------+----------------------------------------------+
; Port                     ; Type  ; Severity ; Details                                      ;
+--------------------------+-------+----------+----------------------------------------------+
; x_sel_user_get_cmd[3..1] ; Input ; Info     ; Stuck at GND                                 ;
; x_sel_user_get_cmd[0]    ; Input ; Info     ; Stuck at VCC                                 ;
+--------------------------+-------+----------+----------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET"                                   ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                             ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_sel_user_set_cmd ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_user_set_cmd     ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_busy             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET" ;
+--------------------------+-------+----------+--------------------------------------------+
; Port                     ; Type  ; Severity ; Details                                    ;
+--------------------------+-------+----------+--------------------------------------------+
; x_sel_user_get_cmd[3..2] ; Input ; Info     ; Stuck at GND                               ;
; x_sel_user_get_cmd[1]    ; Input ; Info     ; Stuck at VCC                               ;
; x_sel_user_get_cmd[0]    ; Input ; Info     ; Stuck at GND                               ;
+--------------------------+-------+----------+--------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET"                                     ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                             ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_sel_user_set_cmd ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_user_set_cmd     ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_busy             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET" ;
+--------------------+-------+----------+-------------------------------------------------+
; Port               ; Type  ; Severity ; Details                                         ;
+--------------------+-------+----------+-------------------------------------------------+
; x_sel_user_get_cmd ; Input ; Info     ; Stuck at GND                                    ;
+--------------------+-------+----------+-------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET"                                      ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                             ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_sel_user_set_cmd ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_user_set_cmd     ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_busy             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS"                                                                                ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                    ; Type   ; Severity ; Details                                                                             ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_phase_regs[29..24]    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_config_regs[119..109] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_soft_cnt_regs[41..36] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_L2_FIFO:C_L2_FIFO"                                                               ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; Port  ; Type   ; Severity ; Details                                                                             ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; q[32] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------+--------+----------+-------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER"                                       ;
+-----------------+--------+----------+-------------------------------------------------------------------------------------+
; Port            ; Type   ; Severity ; Details                                                                             ;
+-----------------+--------+----------+-------------------------------------------------------------------------------------+
; x_fifo_rx_reset ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-----------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER"                                          ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                    ; Type   ; Severity ; Details                                                                             ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_board_id_ans_dis      ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_lib_fw_version[1..0]  ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_lib_fw_version[15..9] ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_lib_fw_version[7..2]  ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_lib_fw_version[8]     ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_fifo_tx_wr_lsb        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC" ;
+-----------------------+-------+----------+---------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                             ;
+-----------------------+-------+----------+---------------------------------------------------------------------+
; x_crc_init            ; Input ; Info     ; Stuck at VCC                                                        ;
; x_crc_final           ; Input ; Info     ; Stuck at GND                                                        ;
; x_crc_din_msb_1st     ; Input ; Info     ; Stuck at GND                                                        ;
; x_crc_reflect_crc_din ; Input ; Info     ; Stuck at VCC                                                        ;
; x_crc_reflect_crc     ; Input ; Info     ; Stuck at GND                                                        ;
+-----------------------+-------+----------+---------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX"                       ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; Port  ; Type   ; Severity ; Details                                                                             ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; usedw ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------+--------+----------+-------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO" ;
+-------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------+
; Port  ; Type   ; Severity ; Details                                                                                                                            ;
+-------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------+
; usedw ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                ;
+-------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK" ;
+----------+-------+----------+---------------------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                                         ;
+----------+-------+----------+---------------------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at VCC                                                                    ;
; datain_l ; Input ; Info     ; Stuck at GND                                                                    ;
+----------+-------+----------+---------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002|altera_reset_synchronizer:alt_rst_req_sync_uq1" ;
+----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                                                                                                                              ;
+----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; reset_in ; Input ; Info     ; Stuck at GND                                                                                                                                                         ;
+----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002" ;
+----------------+-------+----------+-----------------------------------------------------------------------------------------------------------------+
; Port           ; Type  ; Severity ; Details                                                                                                         ;
+----------------+-------+----------+-----------------------------------------------------------------------------------------------------------------+
; reset_req_in0  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in1  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in2      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in2  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in3      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in3  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in4      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in4  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in5      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in5  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in6      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in6  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in7      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in7  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in8      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in8  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in9      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in9  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in10     ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in10 ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in11     ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in11 ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in12     ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in12 ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in13     ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in13 ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in14     ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in14 ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in15     ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in15 ; Input ; Info     ; Stuck at GND                                                                                                    ;
+----------------+-------+----------+-----------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_001" ;
+----------------+-------+----------+-----------------------------------------------------------------------------------------------------------------+
; Port           ; Type  ; Severity ; Details                                                                                                         ;
+----------------+-------+----------+-----------------------------------------------------------------------------------------------------------------+
; reset_req_in0  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in1      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in1  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in2      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in2  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in3      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in3  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in4      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in4  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in5      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in5  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in6      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in6  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in7      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in7  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in8      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in8  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in9      ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in9  ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in10     ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in10 ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in11     ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in11 ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in12     ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in12 ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in13     ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in13 ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in14     ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in14 ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_in15     ; Input ; Info     ; Stuck at GND                                                                                                    ;
; reset_req_in15 ; Input ; Info     ; Stuck at GND                                                                                                    ;
+----------------+-------+----------+-----------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" ;
+----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                                                                                                                          ;
+----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; reset_in ; Input ; Info     ; Stuck at GND                                                                                                                                                     ;
+----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller" ;
+----------------+-------+----------+-------------------------------------------------------------------------------------------------------------+
; Port           ; Type  ; Severity ; Details                                                                                                     ;
+----------------+-------+----------+-------------------------------------------------------------------------------------------------------------+
; reset_req_in0  ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_in1      ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_req_in1  ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_in2      ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_req_in2  ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_in3      ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_req_in3  ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_in4      ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_req_in4  ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_in5      ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_req_in5  ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_in6      ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_req_in6  ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_in7      ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_req_in7  ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_in8      ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_req_in8  ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_in9      ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_req_in9  ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_in10     ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_req_in10 ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_in11     ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_req_in11 ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_in12     ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_req_in12 ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_in13     ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_req_in13 ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_in14     ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_req_in14 ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_in15     ; Input ; Info     ; Stuck at GND                                                                                                ;
; reset_req_in15 ; Input ; Info     ; Stuck at GND                                                                                                ;
+----------------+-------+----------+-------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo" ;
+----------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port     ; Type   ; Severity ; Details                                                                                                                                                                                                                                                                   ;
+----------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; in_ready ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                                                                    ;
+----------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_2:mm_interconnect_2|altera_merlin_slave_translator:enet_nios_rx_dpram_s2_translator" ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                               ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_2:mm_interconnect_2|altera_merlin_master_translator:enet_rx_msgdma_mm_write_translator" ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                  ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_burstcount          ; Input  ; Info     ; Stuck at VCC                                                                                                                                                             ;
; av_beginbursttransfer  ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; av_begintransfer       ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; av_chipselect          ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; av_read                ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; av_readdata            ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; av_readdatavalid       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; av_lock                ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; av_debugaccess         ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; uav_clken              ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; av_clken               ; Input  ; Info     ; Stuck at VCC                                                                                                                                                             ;
; uav_response           ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; av_response            ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; uav_writeresponsevalid ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; av_writeresponsevalid  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router_001:router_001|nios2_mm_interconnect_1_router_001_default_decode:the_default_decode" ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                                                  ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; default_destination_id ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                   ;
; default_wr_channel     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                   ;
; default_rd_channel     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                   ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router:router|nios2_mm_interconnect_1_router_default_decode:the_default_decode" ;
+--------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                                                                                                                                                          ;
+--------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; default_wr_channel ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                           ;
; default_rd_channel ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                           ;
+--------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_udp_dpram_s2_agent_rsp_fifo" ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                           ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                      ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                      ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                      ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                            ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                      ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                            ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                            ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                      ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                            ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                      ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                            ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                      ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                            ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_udp_dpram_s2_agent" ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                   ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                              ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                              ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:enet_nios_tx_dpram_s2_agent_rsp_fifo" ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                               ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_nios_tx_dpram_s2_agent" ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                       ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                  ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                  ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_agent:enet_tx_msgdma_mm_read_agent" ;
+-----------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type   ; Severity ; Details                                                                                                                                                        ;
+-----------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; av_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
+-----------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_udp_dpram_s2_translator" ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                           ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                            ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                            ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                            ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                            ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                      ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                      ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                            ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                            ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                      ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                            ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                            ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                            ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                      ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                            ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                      ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_nios_tx_dpram_s2_translator" ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                               ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_translator:enet_tx_msgdma_mm_read_translator" ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                 ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_burstcount          ; Input  ; Info     ; Stuck at VCC                                                                                                                                                            ;
; av_beginbursttransfer  ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; av_begintransfer       ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; av_chipselect          ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; av_write               ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; av_writedata           ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; av_lock                ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; av_debugaccess         ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; uav_clken              ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; av_clken               ; Input  ; Info     ; Stuck at VCC                                                                                                                                                            ;
; uav_response           ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; av_response            ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; uav_writeresponsevalid ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; av_writeresponsevalid  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_rsp_width_adapter" ;
+----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                 ; Type  ; Severity ; Details                                                                                                                                                                                ;
+----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; in_command_size_data ; Input ; Info     ; Stuck at GND                                                                                                                                                                           ;
+----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor" ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                 ; Type   ; Severity ; Details                                                                                                                                                                                                                             ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; sink_ready           ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                                 ;
; sink_is_compressed   ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                                                                        ;
; sink_burstsize[2]    ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                                                        ;
; sink_burstsize[1]    ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                                                                        ;
; sink_burstsize[0]    ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                                                        ;
; source_burstwrap     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                              ;
; source_is_compressed ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                              ;
; source_burstsize     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                              ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter" ;
+----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                 ; Type  ; Severity ; Details                                                                                                                                                                                ;
+----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; in_command_size_data ; Input ; Info     ; Stuck at GND                                                                                                                                                                           ;
+----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux_001:rsp_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ;
+---------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                                                                                                                                         ;
+---------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; b[3..1] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                                                    ;
; b[0]    ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                                                                    ;
; sum     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                             ;
+---------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ;
+----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port     ; Type   ; Severity ; Details                                                                                                                                                                                                                ;
+----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; b[27..1] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                                           ;
; b[0]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                                                           ;
; sum      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                    ;
+----------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ;
+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port    ; Type  ; Severity ; Details                                                                                                                                                                                                                          ;
+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; b[3..2] ; Input ; Info     ; Stuck at GND                                                                                                                                                                                                                     ;
+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_006:router_006|nios2_mm_interconnect_0_router_006_default_decode:the_default_decode" ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                                                  ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; default_destination_id ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                   ;
; default_wr_channel     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                   ;
; default_rd_channel     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                   ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_005:router_005|nios2_mm_interconnect_0_router_005_default_decode:the_default_decode" ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                                                  ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; default_destination_id ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                   ;
; default_wr_channel     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                   ;
; default_rd_channel     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                   ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_002|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode" ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                                                  ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; default_destination_id ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                   ;
; default_wr_channel     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                   ;
; default_rd_channel     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                   ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_001:router_001|nios2_mm_interconnect_0_router_001_default_decode:the_default_decode" ;
+--------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                                                                                                                                                                      ;
+--------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; default_wr_channel ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                       ;
; default_rd_channel ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                       ;
+--------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router:router|nios2_mm_interconnect_0_router_default_decode:the_default_decode" ;
+--------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                                                                                                                                                          ;
+--------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; default_wr_channel ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                           ;
; default_rd_channel ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                           ;
+--------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_rx_dpram_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                               ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_rx_dpram_s1_agent" ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                       ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                  ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                  ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_status_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                      ;
+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                 ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                 ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                 ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                 ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                 ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                 ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                 ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_status_s1_agent" ;
+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                              ;
+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                         ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                         ;
+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:tx_ctrl_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                    ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                               ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                               ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                               ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                               ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                               ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                               ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                               ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:tx_ctrl_s1_agent" ;
+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                            ;
+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                       ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                       ;
+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_nios_tx_dpram_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                               ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_nios_tx_dpram_s1_agent" ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                       ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                  ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                  ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:onchip_mem_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                       ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                  ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                  ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                  ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                        ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                  ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                        ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                        ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                  ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                        ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                  ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                        ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                  ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                        ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:onchip_mem_s1_agent" ;
+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                               ;
+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                          ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                          ;
+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_response_agent_rsp_fifo" ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                 ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_response_agent" ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                         ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                    ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                    ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_csr_agent_rsp_fifo" ;
+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                            ;
+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_csr_agent" ;
+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                    ;
+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                               ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                               ;
+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:ser_fifo_rx_in_agent_rsp_fifo" ;
+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                        ;
+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:ser_fifo_rx_in_agent" ;
+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                ;
+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                           ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                           ;
+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo" ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                   ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fabric_if_if_bridge_slave_agent" ;
+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                           ;
+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                      ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                      ;
+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo" ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                         ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_descriptor_slave_agent" ;
+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                                 ;
+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                            ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                            ;
+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:nios2_debug_mem_slave_agent_rsp_fifo" ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                               ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:nios2_debug_mem_slave_agent" ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                       ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                  ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                  ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_csr_agent_rsp_fifo" ;
+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                            ;
+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_csr_agent" ;
+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                    ;
+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                               ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                               ;
+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:eth_tse_mac_control_port_agent_rsp_fifo" ;
+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                  ;
+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:eth_tse_mac_control_port_agent" ;
+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                          ;
+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                     ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                     ;
+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo" ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                       ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                  ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                  ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                  ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                  ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                  ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                  ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                  ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent" ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                               ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                          ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                          ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_instruction_master_agent" ;
+-----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type   ; Severity ; Details                                                                                                                                                          ;
+-----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                           ;
; av_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                           ;
+-----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_data_master_agent" ;
+-----------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type   ; Severity ; Details                                                                                                                                                   ;
+-----------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                    ;
; av_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                    ;
+-----------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_rx_dpram_s1_translator" ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                               ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_status_s1_translator" ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                      ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_write               ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; av_writedata           ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                 ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                 ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; av_chipselect          ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                 ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                 ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                       ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                 ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_ctrl_s1_translator" ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                    ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                               ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                               ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                               ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                               ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                     ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                               ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_tx_dpram_s1_translator" ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                               ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:onchip_mem_s1_translator" ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                       ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                        ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                        ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                        ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                        ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                  ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                  ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                        ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                        ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                  ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                        ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                        ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                        ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                  ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                        ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                  ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_response_translator" ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                 ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_write               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; av_writedata           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; av_chipselect          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                  ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                            ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator" ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                            ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_chipselect          ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator" ;
+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                        ;
+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; av_readdata[31..30]    ; Input  ; Info     ; Stuck at VCC                                                                                                                                                   ;
; av_readdata[28..25]    ; Input  ; Info     ; Stuck at VCC                                                                                                                                                   ;
; av_readdata[19..18]    ; Input  ; Info     ; Stuck at VCC                                                                                                                                                   ;
; av_readdata[16..14]    ; Input  ; Info     ; Stuck at VCC                                                                                                                                                   ;
; av_readdata[12..9]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                   ;
; av_readdata[3..2]      ; Input  ; Info     ; Stuck at VCC                                                                                                                                                   ;
; av_readdata[29]        ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; av_readdata[24]        ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; av_readdata[23]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                   ;
; av_readdata[22]        ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; av_readdata[21]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                   ;
; av_readdata[20]        ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; av_readdata[17]        ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; av_readdata[13]        ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; av_readdata[8]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; av_readdata[7]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                   ;
; av_readdata[6]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; av_readdata[5]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                   ;
; av_readdata[4]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; av_readdata[1]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; av_readdata[0]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                   ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; av_chipselect          ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                         ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                   ;
+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fabric_if_if_bridge_slave_translator" ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                   ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; av_chipselect          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator" ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                         ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_address             ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; av_readdata[31..30]    ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                    ;
; av_readdata[28..25]    ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                    ;
; av_readdata[19..18]    ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                    ;
; av_readdata[16..14]    ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                    ;
; av_readdata[12..9]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                    ;
; av_readdata[3..2]      ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                    ;
; av_readdata[127..32]   ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; av_readdata[29]        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; av_readdata[24]        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; av_readdata[23]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                    ;
; av_readdata[22]        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; av_readdata[21]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                    ;
; av_readdata[20]        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; av_readdata[17]        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; av_readdata[13]        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; av_readdata[8]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; av_readdata[7]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                    ;
; av_readdata[6]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; av_readdata[5]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                    ;
; av_readdata[4]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; av_readdata[1]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; av_readdata[0]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                    ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; av_chipselect          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                          ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                    ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:nios2_debug_mem_slave_translator" ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                               ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_chipselect          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                          ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_csr_translator" ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                            ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_chipselect          ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:eth_tse_mac_control_port_translator" ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                  ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; av_chipselect          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                   ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                             ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator" ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                       ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                  ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                  ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                  ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                        ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                  ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_instruction_master_translator" ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                   ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_burstcount          ; Input  ; Info     ; Stuck at VCC                                                                                                                                                              ;
; av_byteenable          ; Input  ; Info     ; Stuck at VCC                                                                                                                                                              ;
; av_beginbursttransfer  ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; av_begintransfer       ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; av_chipselect          ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; av_readdatavalid       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; av_write               ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; av_writedata           ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; av_lock                ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; av_debugaccess         ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; uav_clken              ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; av_clken               ; Input  ; Info     ; Stuck at VCC                                                                                                                                                              ;
; uav_response           ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; av_response            ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
; uav_writeresponsevalid ; Input  ; Info     ; Stuck at GND                                                                                                                                                              ;
; av_writeresponsevalid  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                    ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_data_master_translator" ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                            ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_burstcount          ; Input  ; Info     ; Stuck at VCC                                                                                                                                                       ;
; av_beginbursttransfer  ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; av_begintransfer       ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; av_chipselect          ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; av_readdatavalid       ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_lock                ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; uav_clken              ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; av_clken               ; Input  ; Info     ; Stuck at VCC                                                                                                                                                       ;
; uav_response           ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; av_response            ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
; uav_writeresponsevalid ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; av_writeresponsevalid  ; Output ; Info     ; Explicitly unconnected                                                                                                                                             ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_pll_enet:pll_enet|altera_pll:altera_pll_i"                             ;
+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                      ;
+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
; fboutclk          ; Output ; Info     ; Explicitly unconnected                                                                                                                       ;
; fbclk             ; Input  ; Info     ; Stuck at GND                                                                                                                                 ;
; refclk1           ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; phase_en          ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; updn              ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; num_phase_shifts  ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; scanclk           ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; cntsel            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; reconfig_to_pll   ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; extswitch         ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; adjpllin          ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; cclk              ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; phase_done        ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; reconfig_from_pll ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; activeclk         ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; clkbad            ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; phout             ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; lvds_clk          ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; loaden            ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; extclk_out        ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; cascade_out       ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; zdbfbclk          ; Bidir  ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem" ;
+--------+-------+----------+----------------------------------------------------------------------------------------------------------+
; Port   ; Type  ; Severity ; Details                                                                                                  ;
+--------+-------+----------+----------------------------------------------------------------------------------------------------------+
; freeze ; Input ; Info     ; Stuck at GND                                                                                             ;
+--------+-------+----------+----------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:nios2_nios2_cpu_debug_slave_phy" ;
+--------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                                                                                                                                                                                                                                          ;
+--------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; virtual_state_e1dr ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; virtual_state_pdr  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; virtual_state_e2dr ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; virtual_state_cir  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; tms                ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; jtag_state_tlr     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; jtag_state_sdrs    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; jtag_state_cdr     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; jtag_state_sdr     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; jtag_state_e1dr    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; jtag_state_pdr     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; jtag_state_e2dr    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; jtag_state_udr     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; jtag_state_sirs    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; jtag_state_cir     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; jtag_state_sir     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; jtag_state_e1ir    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; jtag_state_pir     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; jtag_state_e2ir    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
; jtag_state_uir     ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                         ;
+--------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4" ;
+---------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port    ; Type  ; Severity ; Details                                                                                                                                                                                                                                                                                                                                                                              ;
+---------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; reset_n ; Input ; Info     ; Stuck at VCC                                                                                                                                                                                                                                                                                                                                                                         ;
+---------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3" ;
+---------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port    ; Type  ; Severity ; Details                                                                                                                                                                                                                                                                                                                                                                              ;
+---------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; reset_n ; Input ; Info     ; Stuck at VCC                                                                                                                                                                                                                                                                                                                                                                         ;
+---------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_pib:the_nios2_nios2_cpu_nios2_oci_pib" ;
+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                                                                                                                                                  ;
+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tr_data ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                                      ;
+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_fifo:the_nios2_nios2_cpu_nios2_oci_fifo|nios2_nios2_cpu_nios2_oci_fifo_wrptr_inc:the_nios2_nios2_cpu_nios2_oci_fifo_wrptr_inc" ;
+----------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port           ; Type   ; Severity ; Details                                                                                                                                                                                                                                                                                                                   ;
+----------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; fifo_wrptr_inc ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                                                                       ;
+----------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_dtrace:the_nios2_nios2_cpu_nios2_oci_dtrace|nios2_nios2_cpu_nios2_oci_td_mode:nios2_nios2_cpu_nios2_oci_trc_ctrl_td_mode" ;
+---------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                                                                                                                                                                                                                                     ;
+---------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; td_mode ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                                                                         ;
+---------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_itrace:the_nios2_nios2_cpu_nios2_oci_itrace" ;
+------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type  ; Severity ; Details                                                                                                                                                                                                                                            ;
+------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; jdo  ; Input ; Warning  ; Input port expression (38 bits) is wider than the input port (16 bits) it drives.  The 22 most-significant bit(s) in the expression will be dangling if they have no other fanouts.                                                                ;
+------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_dbrk:the_nios2_nios2_cpu_nios2_oci_dbrk" ;
+--------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port         ; Type   ; Severity ; Details                                                                                                                                                                                                                               ;
+--------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; dbrk_trigout ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                                   ;
+--------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_xbrk:the_nios2_nios2_cpu_nios2_oci_xbrk" ;
+--------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port         ; Type   ; Severity ; Details                                                                                                                                                                                                                               ;
+--------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; xbrk_trigout ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                                   ;
+--------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_debug:the_nios2_nios2_cpu_nios2_oci_debug" ;
+----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                                                                                                                                                                                                      ;
+----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; debugreq ; Input ; Info     ; Stuck at GND                                                                                                                                                                                                                                 ;
+----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci" ;
+--------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                                                                                                       ;
+--------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; oci_ienable[31..3] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                           ;
; oci_ienable[1]     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                           ;
+--------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_test_bench:the_nios2_nios2_cpu_test_bench" ;
+-----------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port            ; Type   ; Severity ; Details                                                                                                                                                            ;
+-----------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; F_pcb[1..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; i_address[1..0] ; Input  ; Info     ; Stuck at GND                                                                                                                                                       ;
; test_has_ended  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                ;
+-----------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2" ;
+---------------+--------+----------+----------------------------------------------------------------------------------------+
; Port          ; Type   ; Severity ; Details                                                                                ;
+---------------+--------+----------+----------------------------------------------------------------------------------------+
; dummy_ci_port ; Output ; Info     ; Explicitly unconnected                                                                 ;
+---------------+--------+----------+----------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic" ;
+----------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port           ; Type   ; Severity ; Details                                                                                                                                                 ;
+----------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; raw_tck        ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND.            ;
; tdi            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND.            ;
; jtag_state_rti ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND.            ;
; usr1           ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND.            ;
; clr            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND.            ;
; ena            ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND.            ;
; ir_in          ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND.            ;
; tdo            ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                ;
; ir_out         ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                ;
; jtag_state_cdr ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND.            ;
; jtag_state_sdr ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND.            ;
; jtag_state_udr ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND.            ;
+----------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0"       ;
+---------------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port          ; Type   ; Severity ; Details                                                                                                  ;
+---------------+--------+----------+----------------------------------------------------------------------------------------------------------+
; dataavailable ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
; readyfordata  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------------+--------+----------+----------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" ;
+----------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                                                                                                                                                    ;
+----------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; reset_in ; Input ; Info     ; Stuck at GND                                                                                                                                                                               ;
+----------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller" ;
+----------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------+
; Port           ; Type   ; Severity ; Details                                                                                                                              ;
+----------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------+
; reset_req      ; Output ; Info     ; Explicitly unconnected                                                                                                               ;
; reset_req_in0  ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_in1      ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_req_in1  ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_in2      ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_req_in2  ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_in3      ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_req_in3  ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_in4      ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_req_in4  ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_in5      ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_req_in5  ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_in6      ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_req_in6  ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_in7      ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_req_in7  ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_in8      ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_req_in8  ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_in9      ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_req_in9  ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_in10     ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_req_in10 ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_in11     ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_req_in11 ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_in12     ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_req_in12 ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_in13     ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_req_in13 ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_in14     ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_req_in14 ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_in15     ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
; reset_req_in15 ; Input  ; Info     ; Stuck at GND                                                                                                                         ;
+----------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ;
+----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port     ; Type   ; Severity ; Details                                                                                                                                                                                                                                                              ;
+----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; b[29..1] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                                                                                         ;
; b[0]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                                                                                                         ;
; sum      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                                                                  ;
+----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_001|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode" ;
+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                                                                                                          ;
+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; default_destination_id ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                                                                           ;
; default_wr_channel     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                                                                           ;
; default_rd_channel     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                                                                           ;
+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router:router|nios2_fabric_if_mm_interconnect_0_router_default_decode:the_default_decode" ;
+--------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                                                                                                                                                                                                                  ;
+--------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; default_wr_channel ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                                                                   ;
; default_rd_channel ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                                                                   ;
+--------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_in_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                                                  ;
+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_in_s1_agent" ;
+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                                                          ;
+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                                                     ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                                                     ;
+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_in_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                                                  ;
+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_in_s1_agent" ;
+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                                                          ;
+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                                                     ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                                                     ;
+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_in_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                                               ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_in_s1_agent" ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                                                       ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                                                  ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                                                  ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:version_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                                        ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:version_s1_agent" ;
+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                                                ;
+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                                           ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                                           ;
+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:testing_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                                        ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:testing_s1_agent" ;
+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                                                ;
+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                                           ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                                           ;
+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_h_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                                                    ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_h_s1_agent" ;
+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                                                            ;
+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                                                       ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                                                       ;
+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_mac_addr_l_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                                                    ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_mac_addr_l_s1_agent" ;
+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                                                            ;
+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                                                       ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                                                       ;
+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_h_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                                                   ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_h_s1_agent" ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                                                           ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                                                      ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_mac_addr_l_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                                                   ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_mac_addr_l_s1_agent" ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                                                           ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                                                      ;
+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:rot_switch_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                                           ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:rot_switch_s1_agent" ;
+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                                                   ;
+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                                              ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                                              ;
+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sc_dest_ip_addr_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                                                ;
+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                           ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                           ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                           ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                           ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                           ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                           ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                           ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:sc_dest_ip_addr_s1_agent" ;
+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                                                        ;
+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                                                   ;
+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:daq_dest_ip_addr_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                                                 ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                            ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                            ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                            ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                            ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                            ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                            ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                            ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:daq_dest_ip_addr_s1_agent" ;
+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                                                         ;
+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                                                    ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                                                    ;
+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_ip_addr_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                                            ;
+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                       ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                       ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                       ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                       ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                       ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                       ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                       ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_ip_addr_s1_agent" ;
+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                                                    ;
+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                                               ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                                               ;
+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_h_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                                               ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_h_s1_agent" ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                                                       ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                                                  ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                                                  ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo" ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                                               ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_s1_agent" ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                                                                                                                                                       ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; m0_response           ; Input ; Info     ; Stuck at GND                                                                                                                                                                                  ;
; m0_writeresponsevalid ; Input ; Info     ; Stuck at GND                                                                                                                                                                                  ;
+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:if_bridge_m0_agent" ;
+-----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type   ; Severity ; Details                                                                                                                                                                                  ;
+-----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                   ;
; av_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                   ;
+-----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_in_s1_translator" ;
+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                                  ;
+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_write               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_writedata           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_chipselect          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_in_s1_translator" ;
+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                                  ;
+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_write               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_writedata           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_chipselect          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                   ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                             ;
+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_in_s1_translator" ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                               ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_write               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_writedata           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_chipselect          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:version_s1_translator" ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                        ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:testing_s1_translator" ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                        ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                         ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                   ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_h_s1_translator" ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                                    ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_mac_addr_l_s1_translator" ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                                    ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                     ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                               ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_h_s1_translator" ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                                   ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_mac_addr_l_s1_translator" ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                                   ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                    ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                              ;
+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:rot_switch_s1_translator" ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                           ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_write               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; av_writedata           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; av_chipselect          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sc_dest_ip_addr_s1_translator" ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                                ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                           ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                           ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                           ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                           ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                 ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                           ;
+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:daq_dest_ip_addr_s1_translator" ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                                 ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                            ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                            ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                            ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                            ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                  ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                            ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_ip_addr_s1_translator" ;
+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                            ;
+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                       ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                       ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                       ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                       ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                             ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                       ;
+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_h_s1_translator" ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                               ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_s1_translator" ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                               ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_read                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_begintransfer       ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_beginbursttransfer  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_burstcount          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_byteenable          ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_readdatavalid       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; av_waitrequest         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; av_writebyteenable     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_lock                ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_clken               ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; uav_clken              ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; av_debugaccess         ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_outputenable        ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; uav_response           ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_response            ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
; uav_writeresponsevalid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                ;
; av_writeresponsevalid  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                          ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:if_bridge_m0_translator" ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                           ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; av_beginbursttransfer  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; av_begintransfer       ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; av_chipselect          ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; av_lock                ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; uav_clken              ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; av_clken               ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                                      ;
; uav_response           ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; av_response            ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
; uav_writeresponsevalid ; Input  ; Info     ; Stuck at GND                                                                                                                                                                                      ;
; av_writeresponsevalid  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                            ;
+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_avalon_mm_bridge:if_bridge" ;
+-------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------+
; Port        ; Type   ; Severity ; Details                                                                                                                            ;
+-------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------+
; s0_response ; Output ; Info     ; Explicitly unconnected                                                                                                             ;
; m0_response ; Input  ; Info     ; Stuck at GND                                                                                                                       ;
+-------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac" ;
+-----------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+
; Port            ; Type   ; Severity ; Details                                                                                                                       ;
+-----------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+
; magic_sleep_n   ; Input  ; Info     ; Stuck at VCC                                                                                                                  ;
; rx_clkena       ; Input  ; Info     ; Stuck at VCC                                                                                                                  ;
; tx_clkena       ; Input  ; Info     ; Stuck at VCC                                                                                                                  ;
; xon_gen         ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; xoff_gen        ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; magic_wakeup    ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; mac_eccstatus   ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; gm_rx_d         ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; gm_rx_dv        ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; gm_rx_err       ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; gm_tx_d         ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; gm_tx_en        ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; gm_tx_err       ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; rgmii_out1_aclr ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; rgmii_out1_din  ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; rgmii_in1_dout  ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; rgmii_in1_ck    ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; rgmii_out4_din  ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; rgmii_out4_ck   ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; rgmii_in1_pad   ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; rgmii_out4_aclr ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; rgmii_out1_pad  ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; rgmii_out1_ck   ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; rgmii_in4_dout  ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; rgmii_in4_pad   ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; rgmii_out4_pad  ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; rgmii_in4_ck    ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; m_rx_d          ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; m_rx_en         ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; m_rx_err        ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; m_tx_d          ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; m_tx_en         ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; m_tx_err        ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; m_rx_crs        ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; m_rx_col        ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
+-----------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram" ;
+--------+-------+----------+------------------------------------------------------------------------------------------------------------------+
; Port   ; Type  ; Severity ; Details                                                                                                          ;
+--------+-------+----------+------------------------------------------------------------------------------------------------------------------+
; freeze ; Input ; Info     ; Stuck at GND                                                                                                     ;
+--------+-------+----------+------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|read_burst_control:the_read_burst_control" ;
+------------------------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                               ; Type  ; Severity ; Details                                                                                                                                                       ;
+------------------------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; address[1..0]                      ; Input ; Info     ; Stuck at GND                                                                                                                                                  ;
; maximum_burst_count                ; Input ; Info     ; Stuck at VCC                                                                                                                                                  ;
; short_first_access_enable          ; Input ; Info     ; Stuck at GND                                                                                                                                                  ;
; short_first_and_last_access_enable ; Input ; Info     ; Stuck at GND                                                                                                                                                  ;
+------------------------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal" ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                             ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------+
; master_burstcount ; Output ; Info     ; Explicitly unconnected                                                                                                              ;
; src_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                              ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block" ;
+------------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                         ; Type   ; Severity ; Details                                                                                                                                          ;
+------------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; stopped_on_error             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                              ;
; stopped_on_early_termination ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                              ;
; stop_on_error                ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                              ;
; stop_on_early_termination    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                              ;
; descriptor_watermark[31..21] ; Input  ; Info     ; Stuck at GND                                                                                                                                     ;
; descriptor_watermark[15..5]  ; Input  ; Info     ; Stuck at GND                                                                                                                                     ;
+------------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO" ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type  ; Severity ; Details                                                                                                                                                                                                                                  ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; push ; Input ; Info     ; Stuck at GND                                                                                                                                                                                                                             ;
; pop  ; Input ; Info     ; Stuck at GND                                                                                                                                                                                                                             ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|read_signal_breakout:the_read_signal_breakout" ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                                                                                ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; read_address           ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                    ;
; read_length            ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                    ;
; read_transmit_channel  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                    ;
; read_generate_sop      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                    ;
; read_generate_eop      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                    ;
; read_burst_count       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                    ;
; read_stride            ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                    ;
; read_transmit_error    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                    ;
; read_early_done_enable ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                    ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|write_signal_breakout:the_write_signal_breakout" ;
+----------------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                             ; Type   ; Severity ; Details                                                                                                                                                                                                        ;
+----------------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; write_address                    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                            ;
; write_length                     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                            ;
; write_park                       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                            ;
; write_end_on_eop                 ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                            ;
; write_transfer_complete_IRQ_mask ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                            ;
; write_early_termination_IRQ_mask ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                            ;
; write_error_IRQ_mask             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                            ;
; write_burst_count                ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                            ;
; write_stride                     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                            ;
; write_sequence_number            ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                            ;
+----------------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal" ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+
; Port                    ; Type   ; Severity ; Details                                                                                                                       ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+
; src_response_data       ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; src_response_valid      ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; src_response_ready      ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; snk_descriptor_data     ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; snk_descriptor_valid    ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; snk_descriptor_ready    ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; mm_response_waitrequest ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; mm_response_byteenable  ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; mm_response_address     ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; mm_response_readdata    ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; mm_response_read        ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; src_write_master_data   ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; src_write_master_valid  ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
; src_write_master_ready  ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; snk_write_master_data   ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; snk_write_master_valid  ; Input  ; Info     ; Stuck at GND                                                                                                                  ;
; snk_write_master_ready  ; Output ; Info     ; Explicitly unconnected                                                                                                        ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|write_burst_control:the_write_burst_control" ;
+------------------------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                               ; Type  ; Severity ; Details                                                                                                                                                           ;
+------------------------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; address_in[1..0]                   ; Input ; Info     ; Stuck at GND                                                                                                                                                      ;
; short_first_access_enable          ; Input ; Info     ; Stuck at GND                                                                                                                                                      ;
; short_first_and_last_access_enable ; Input ; Info     ; Stuck at GND                                                                                                                                                      ;
+------------------------------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|byte_enable_generator:the_byte_enable_generator" ;
+------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port             ; Type  ; Severity ; Details                                                                                                                                                                                 ;
+------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; byteenable_in[0] ; Input ; Info     ; Stuck at VCC                                                                                                                                                                            ;
+------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal" ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                               ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------+
; master_burstcount ; Output ; Info     ; Explicitly unconnected                                                                                                                ;
+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block" ;
+------------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                         ; Type   ; Severity ; Details                                                                                                                                          ;
+------------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; stopped_on_error             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                              ;
; stopped_on_early_termination ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                              ;
; stop_on_error                ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                              ;
; stop_on_early_termination    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                              ;
; descriptor_watermark[31..21] ; Input  ; Info     ; Stuck at GND                                                                                                                                     ;
; descriptor_watermark[15..5]  ; Input  ; Info     ; Stuck at GND                                                                                                                                     ;
+------------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO" ;
+------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type  ; Severity ; Details                                                                                                                                                                                                                                 ;
+------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; push ; Input ; Info     ; Stuck at GND                                                                                                                                                                                                                            ;
; pop  ; Input ; Info     ; Stuck at GND                                                                                                                                                                                                                            ;
+------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|read_signal_breakout:the_read_signal_breakout" ;
+---------------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                            ; Type   ; Severity ; Details                                                                                                                                                                                                       ;
+---------------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; read_address                    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                           ;
; read_length                     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                           ;
; read_transmit_channel           ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                           ;
; read_generate_sop               ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                           ;
; read_generate_eop               ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                           ;
; read_park                       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                           ;
; read_transfer_complete_IRQ_mask ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                           ;
; read_burst_count                ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                           ;
; read_stride                     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                           ;
; read_sequence_number            ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                           ;
; read_transmit_error             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                           ;
; read_early_done_enable          ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                           ;
+---------------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|write_signal_breakout:the_write_signal_breakout" ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                                                                                                                       ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; write_address     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                           ;
; write_length      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                           ;
; write_end_on_eop  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                           ;
; write_burst_count ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                           ;
; write_stride      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                                                           ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal" ;
+-----------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------+
; Port                  ; Type   ; Severity ; Details                                                                                                                         ;
+-----------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------+
; src_response_data     ; Output ; Info     ; Explicitly unconnected                                                                                                          ;
; src_response_valid    ; Output ; Info     ; Explicitly unconnected                                                                                                          ;
; src_response_ready    ; Input  ; Info     ; Stuck at GND                                                                                                                    ;
; snk_descriptor_data   ; Input  ; Info     ; Stuck at GND                                                                                                                    ;
; snk_descriptor_valid  ; Input  ; Info     ; Stuck at GND                                                                                                                    ;
; snk_descriptor_ready  ; Output ; Info     ; Explicitly unconnected                                                                                                          ;
; src_read_master_data  ; Output ; Info     ; Explicitly unconnected                                                                                                          ;
; src_read_master_valid ; Output ; Info     ; Explicitly unconnected                                                                                                          ;
; src_read_master_ready ; Input  ; Info     ; Stuck at GND                                                                                                                    ;
; snk_read_master_data  ; Input  ; Info     ; Stuck at GND                                                                                                                    ;
; snk_read_master_valid ; Input  ; Info     ; Stuck at GND                                                                                                                    ;
; snk_read_master_ready ; Output ; Info     ; Explicitly unconnected                                                                                                          ;
+-----------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_tx_dpram:enet_nios_tx_dpram" ;
+--------+-------+----------+--------------------------------------------------------------------------------------------------------------------------+
; Port   ; Type  ; Severity ; Details                                                                                                                  ;
+--------+-------+----------+--------------------------------------------------------------------------------------------------------------------------+
; freeze ; Input ; Info     ; Stuck at GND                                                                                                             ;
+--------+-------+----------+--------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram" ;
+--------+-------+----------+--------------------------------------------------------------------------------------------------------------------------+
; Port   ; Type  ; Severity ; Details                                                                                                                  ;
+--------+-------+----------+--------------------------------------------------------------------------------------------------------------------------+
; freeze ; Input ; Info     ; Stuck at GND                                                                                                             ;
+--------+-------+----------+--------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS"                                                                                        ;
+------------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
; Port                         ; Type   ; Severity ; Details                                                                                                                                      ;
+------------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
; tse_mac_misc_ff_tx_crc_fwd   ; Input  ; Info     ; Stuck at GND                                                                                                                                 ;
; tse_mac_misc_ff_tx_septy     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                          ;
; tse_mac_misc_tx_ff_uflow     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                          ;
; tse_mac_misc_ff_tx_a_full    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                          ;
; tse_mac_misc_ff_tx_a_empty   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                          ;
; tse_mac_misc_rx_err_stat     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                          ;
; tse_mac_misc_rx_frm_type     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                          ;
; tse_mac_misc_ff_rx_dsav      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                          ;
; tse_mac_misc_ff_rx_a_full    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                          ;
; tse_mac_misc_ff_rx_a_empty   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                          ;
; tse_mac_status_set_10        ; Input  ; Info     ; Stuck at GND                                                                                                                                 ;
; tse_mac_status_set_1000      ; Input  ; Info     ; Stuck at VCC                                                                                                                                 ;
; tse_mac_status_eth_mode      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                          ;
; tse_mac_status_ena_10        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                          ;
; x_tx_ctrl_out_export[12..9]  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                          ;
; x_tx_status_in_export[12..3] ; Input  ; Info     ; Stuck at GND                                                                                                                                 ;
; pll_enet_locked_export       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                          ;
; x_rot_switch_in_export       ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
+------------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER"                                            ;
+--------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                     ; Type   ; Severity ; Details                                                                             ;
+--------------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_version                ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_desc_sm_state_g        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_disp_state_irq_g       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_xfer_dpram_used_g      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_ftdsm_state_g          ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_ftdsm_xfer_dpram_msb_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------------------+--------+----------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER"                                                                      ;
+--------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                     ; Type   ; Severity ; Details                                                                             ;
+--------------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_nios_testing           ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_dhcp_on                ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_ip_from_fabric         ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_mac_from_fabric        ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_sc_config              ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_board_id[6..4]         ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_status[15..7]          ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_fw_version[4..1]       ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_fw_version[15..9]      ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_fw_version[7..5]       ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_fw_version[8]          ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_fw_version[0]          ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_hw_version             ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_product_id[15..3]      ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_product_id[2]          ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_product_id[1]          ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_product_id[0]          ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_dpram_data_rd          ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_dpram_addr_rd          ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_dpram_data_wr          ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_dpram_addr_wr          ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_dpram_wr               ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_device_load_req        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_device_load_ack        ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_device_load_error      ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_device_valid_word      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_user_set_req[7..6]     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_user_set_ack[7..6]     ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_user_set_error[7..6]   ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_user_set_cmd_req       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_user_set_cmd           ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_user_set_cmd_ack       ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_user_set_cmd_error     ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_user_set_cmd_error_d   ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_user_get_cmd[15..4]    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_sc_fifo_rx_empty_g     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_sc_fifo_rx_out_ready_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_sc_fifo_tx_wr_g        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_disp_state_rq_g        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_irq_clear_rq_g         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_irq_clear_ack_g        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_ftdsm_xfer_start_rq_g  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_ftdsm_xfer_ready_g     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_sc_fifo_xfer_rq_g      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_sc_fifo_xfer_ack_g     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_daq_fifo_xfer_rq_g     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_daq_fifo_xfer_ack_g    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------------------+--------+----------+-------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_CLK_WRAPPER:C_CLK_WRAPPER"                                                                  ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port             ; Type   ; Severity ; Details                                                                             ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_clk32          ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_phase_state_g  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_switch_state_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_pll4_locked_g  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------------+-----------------------+
; Type                        ; Count                 ;
+-----------------------------+-----------------------+
; arriav_ddio_in              ; 5                     ;
; arriav_ddio_out             ; 38                    ;
; arriav_ff                   ; 9891                  ;
;     CLR                     ; 4577                  ;
;     CLR SCLR                ; 735                   ;
;     CLR SCLR SLD            ; 33                    ;
;     CLR SLD                 ; 82                    ;
;     ENA                     ; 129                   ;
;     ENA CLR                 ; 2713                  ;
;     ENA CLR SCLR            ; 562                   ;
;     ENA CLR SCLR SLD        ; 32                    ;
;     ENA CLR SLD             ; 569                   ;
;     ENA SCLR                ; 63                    ;
;     ENA SCLR SLD            ; 22                    ;
;     ENA SLD                 ; 9                     ;
;     SCLR                    ; 4                     ;
;     SLD                     ; 30                    ;
;     plain                   ; 331                   ;
; arriav_io_obuf              ; 33                    ;
; arriav_lcell_comb           ; 9986                  ;
;     arith                   ; 1123                  ;
;         0 data inputs       ; 4                     ;
;         1 data inputs       ; 909                   ;
;         2 data inputs       ; 138                   ;
;         3 data inputs       ; 31                    ;
;         4 data inputs       ; 3                     ;
;         5 data inputs       ; 38                    ;
;     extend                  ; 76                    ;
;         7 data inputs       ; 76                    ;
;     normal                  ; 8463                  ;
;         0 data inputs       ; 28                    ;
;         1 data inputs       ; 198                   ;
;         2 data inputs       ; 1490                  ;
;         3 data inputs       ; 1040                  ;
;         4 data inputs       ; 1918                  ;
;         5 data inputs       ; 1708                  ;
;         6 data inputs       ; 2081                  ;
;     shared                  ; 324                   ;
;         1 data inputs       ; 9                     ;
;         2 data inputs       ; 312                   ;
;         4 data inputs       ; 3                     ;
; boundary_port               ; 234                   ;
; cyclonev_fractional_pll     ; 1                     ;
; cyclonev_pll_output_counter ; 5                     ;
; cyclonev_pll_reconfig       ; 1                     ;
; cyclonev_pll_refclk_select  ; 1                     ;
; generic_pll                 ; 2                     ;
; stratixv_ram_block          ; 1422                  ;
;                             ;                       ;
; Max LUT depth               ; 9.00                  ;
; Average LUT depth           ; 3.05                  ;
+-----------------------------+-----------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:26     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition
    Info: Processing started: Mon Nov 30 09:45:02 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FTR_TOP -c FTR_TOP
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/u_util/exp/u_size.vhd
    Info (12022): Found design unit 1: U_Size File: J:/vhdl_db/trunk/lib/u_util/exp/u_size.vhd Line: 10
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/u_util/exp/u_util.vhd
    Info (12022): Found design unit 1: u_util File: J:/vhdl_db/trunk/lib/u_util/exp/u_util.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/u_util/src/u_onepulse.vhd
    Info (12022): Found design unit 1: U_OnePulse-A_behavioral File: J:/vhdl_db/trunk/lib/u_util/src/u_onepulse.vhd Line: 26
    Info (12023): Found entity 1: U_OnePulse File: J:/vhdl_db/trunk/lib/u_util/src/u_onepulse.vhd Line: 11
Info (12021): Found 2 design units, including 0 entities, in source file /vhdl_db/trunk/lib/usb_usb/exp/usb_usb.vhd
    Info (12022): Found design unit 1: usb_usb File: J:/vhdl_db/trunk/lib/usb_usb/exp/usb_usb.vhd Line: 11
    Info (12022): Found design unit 2: usb_usb-body File: J:/vhdl_db/trunk/lib/usb_usb/exp/usb_usb.vhd Line: 245
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/usb_uc_pclk.vhd
    Info (12022): Found design unit 1: usb_uc_pclk-SYN File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 53
    Info (12023): Found entity 1: USB_UC_PCLK File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 42
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/exp/ser_crc_pck.vhd
    Info (12022): Found design unit 1: ser_crc_pck File: J:/vhdl_db/trunk/lib/ser_serialCommunication/exp/ser_crc_pck.vhd Line: 9
Info (12021): Found 2 design units, including 0 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_crc_pck_polynomial.vhd
    Info (12022): Found design unit 1: ser_crc_pck_polynomial File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc_pck_polynomial.vhd Line: 13
    Info (12022): Found design unit 2: ser_crc_pck_polynomial-body File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc_pck_polynomial.vhd Line: 78
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_crc.vhd
    Info (12022): Found design unit 1: ser_crc-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc.vhd Line: 44
    Info (12023): Found entity 1: ser_crc File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc.vhd Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/crc_pol/ser_crc_pol16_din16_d4_1a2eb.vhd
    Info (12022): Found design unit 1: ser_crc_pol16_DIN16_D4_1a2eb-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/crc_pol/ser_crc_pol16_DIN16_D4_1a2eb.vhd Line: 32
    Info (12023): Found entity 1: ser_crc_pol16_DIN16_D4_1a2eb File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/crc_pol/ser_crc_pol16_DIN16_D4_1a2eb.vhd Line: 14
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/exp/ufp_protocol.vhd
    Info (12022): Found design unit 1: UFP_Protocol File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_Protocol.vhd Line: 14
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/exp/ufp_fw_version.vhd
    Info (12022): Found design unit 1: UFP_fw_version File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_fw_version.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_decoder.vhd
    Info (12022): Found design unit 1: UFP_DECODER-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Decoder.vhd Line: 75
    Info (12023): Found entity 1: UFP_DECODER File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Decoder.vhd Line: 9
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_encoder_uart.vhd
    Info (12022): Found design unit 1: UFP_ENCODER_UART-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Encoder_uart.vhd Line: 68
    Info (12023): Found entity 1: UFP_ENCODER_UART File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Encoder_uart.vhd Line: 10
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_user_get_config.vhd
    Info (12022): Found design unit 1: UFP_USER_GET_CONFIG-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_GET_CONFIG.vhd Line: 39
    Info (12023): Found entity 1: UFP_USER_GET_CONFIG File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_GET_CONFIG.vhd Line: 13
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_user_set_config.vhd
    Info (12022): Found design unit 1: UFP_USER_SET_CONFIG-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SET_CONFIG.vhd Line: 43
    Info (12023): Found entity 1: UFP_USER_SET_CONFIG File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SET_CONFIG.vhd Line: 17
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_user_setget_ack.vhd
    Info (12022): Found design unit 1: UFP_USER_SETGET_ACK-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SETGET_ACK.vhd Line: 22
    Info (12023): Found entity 1: UFP_USER_SETGET_ACK File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SETGET_ACK.vhd Line: 10
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/exp/eth_ethernet.vhd
    Info (12022): Found design unit 1: eth_ethernet File: J:/vhdl_db/trunk/lib/eth_ethernet/exp/ETH_ETHERNET.vhd Line: 12
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v
    Info (12023): Found entity 1: nios2 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 6
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_reset_controller.v
    Info (12023): Found entity 1: altera_reset_controller File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_reset_controller.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_reset_synchronizer.v
    Info (12023): Found entity 1: altera_reset_synchronizer File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_reset_synchronizer.v Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_avalon_st_adapter.v
    Info (12023): Found entity 1: nios2_avalon_st_adapter File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_avalon_st_adapter.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_avalon_st_adapter_timing_adapter_0.sv
    Info (12023): Found entity 1: nios2_avalon_st_adapter_timing_adapter_0 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_avalon_st_adapter_timing_adapter_0.sv Line: 60
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_avalon_st_adapter_timing_adapter_0_fifo.sv
    Info (12023): Found entity 1: nios2_avalon_st_adapter_timing_adapter_0_fifo File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_avalon_st_adapter_timing_adapter_0_fifo.sv Line: 53
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_irq_mapper.sv
    Info (12023): Found entity 1: nios2_irq_mapper File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_irq_mapper.sv Line: 31
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_2.v
    Info (12023): Found entity 1: nios2_mm_interconnect_2 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_2.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_slave_translator.sv
    Info (12023): Found entity 1: altera_merlin_slave_translator File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_slave_translator.sv Line: 35
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_master_translator.sv
    Info (12023): Found entity 1: altera_merlin_master_translator File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_master_translator.sv Line: 32
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1.v
    Info (12023): Found entity 1: nios2_mm_interconnect_1 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter.v
    Info (12023): Found entity 1: nios2_mm_interconnect_0_avalon_st_adapter File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Line: 66
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_rsp_mux.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_1_rsp_mux File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_rsp_mux.sv Line: 51
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_arbitrator.sv
    Info (12023): Found entity 1: altera_merlin_arbitrator File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_arbitrator.sv Line: 103
    Info (12023): Found entity 2: altera_merlin_arb_adder File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_arbitrator.sv Line: 228
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_rsp_demux.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_1_rsp_demux File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_rsp_demux.sv Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_cmd_mux.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_1_cmd_mux File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_cmd_mux.sv Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_cmd_demux.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_1_cmd_demux File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_cmd_demux.sv Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_traffic_limiter.sv
    Info (12023): Found entity 1: altera_merlin_traffic_limiter File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_traffic_limiter.sv Line: 49
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_reorder_memory.sv
    Info (12023): Found entity 1: altera_merlin_reorder_memory File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 28
    Info (12023): Found entity 2: memory_pointer_controller File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 185
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_avalon_sc_fifo.v
    Info (12023): Found entity 1: altera_avalon_sc_fifo File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_avalon_sc_fifo.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_avalon_st_pipeline_base.v
    Info (12023): Found entity 1: altera_avalon_st_pipeline_base File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_avalon_st_pipeline_base.v Line: 22
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_router_001.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_1_router_001_default_decode File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_router_001.sv Line: 45
    Info (12023): Found entity 2: nios2_mm_interconnect_1_router_001 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_router_001.sv Line: 84
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_router.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_1_router_default_decode File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_router.sv Line: 45
    Info (12023): Found entity 2: nios2_mm_interconnect_1_router File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_router.sv Line: 84
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_slave_agent.sv
    Info (12023): Found entity 1: altera_merlin_slave_agent File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_slave_agent.sv Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_burst_uncompressor.sv
    Info (12023): Found entity 1: altera_merlin_burst_uncompressor File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_burst_uncompressor.sv Line: 40
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_master_agent.sv
    Info (12023): Found entity 1: altera_merlin_master_agent File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_master_agent.sv Line: 28
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v
    Info (12023): Found entity 1: nios2_mm_interconnect_0 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter_004.v
    Info (12023): Found entity 1: nios2_mm_interconnect_0_avalon_st_adapter_004 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter_004.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0.sv Line: 66
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_width_adapter.sv
    Info (12023): Found entity 1: altera_merlin_width_adapter File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_width_adapter.sv Line: 25
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_address_alignment.sv
    Info (12023): Found entity 1: altera_merlin_address_alignment File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_address_alignment.sv Line: 26
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_mux_001.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_0_rsp_mux_001 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_mux_001.sv Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_mux.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_0_rsp_mux File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_mux.sv Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_demux.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_0_rsp_demux File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_demux.sv Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_mux_003.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_0_cmd_mux_003 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_mux_003.sv Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_mux.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_0_cmd_mux File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_mux.sv Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_demux_001.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_0_cmd_demux_001 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_demux_001.sv Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_demux.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_0_cmd_demux File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_demux.sv Line: 43
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_006.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_0_router_006_default_decode File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_006.sv Line: 45
    Info (12023): Found entity 2: nios2_mm_interconnect_0_router_006 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_006.sv Line: 84
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_005.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_0_router_005_default_decode File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_005.sv Line: 45
    Info (12023): Found entity 2: nios2_mm_interconnect_0_router_005 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_005.sv Line: 84
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_002.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_0_router_002_default_decode File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_002.sv Line: 45
    Info (12023): Found entity 2: nios2_mm_interconnect_0_router_002 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_002.sv Line: 84
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_001.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_0_router_001_default_decode File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_001.sv Line: 45
    Info (12023): Found entity 2: nios2_mm_interconnect_0_router_001 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_001.sv Line: 84
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router.sv
    Info (12023): Found entity 1: nios2_mm_interconnect_0_router_default_decode File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router.sv Line: 45
    Info (12023): Found entity 2: nios2_mm_interconnect_0_router File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router.sv Line: 84
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_pll_enet.v
    Info (12023): Found entity 1: nios2_pll_enet File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_pll_enet.v Line: 2
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_onchip_mem.v
    Info (12023): Found entity 1: nios2_onchip_mem File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_onchip_mem.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2.v
    Info (12023): Found entity 1: nios2_nios2 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2.v Line: 9
Info (12021): Found 21 design units, including 21 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v
    Info (12023): Found entity 1: nios2_nios2_cpu_register_bank_a_module File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 21
    Info (12023): Found entity 2: nios2_nios2_cpu_register_bank_b_module File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 87
    Info (12023): Found entity 3: nios2_nios2_cpu_nios2_oci_debug File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 153
    Info (12023): Found entity 4: nios2_nios2_cpu_nios2_oci_break File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 295
    Info (12023): Found entity 5: nios2_nios2_cpu_nios2_oci_xbrk File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 588
    Info (12023): Found entity 6: nios2_nios2_cpu_nios2_oci_dbrk File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 795
    Info (12023): Found entity 7: nios2_nios2_cpu_nios2_oci_itrace File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 982
    Info (12023): Found entity 8: nios2_nios2_cpu_nios2_oci_td_mode File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 1115
    Info (12023): Found entity 9: nios2_nios2_cpu_nios2_oci_dtrace File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 1183
    Info (12023): Found entity 10: nios2_nios2_cpu_nios2_oci_compute_input_tm_cnt File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 1265
    Info (12023): Found entity 11: nios2_nios2_cpu_nios2_oci_fifo_wrptr_inc File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 1337
    Info (12023): Found entity 12: nios2_nios2_cpu_nios2_oci_fifo_cnt_inc File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 1380
    Info (12023): Found entity 13: nios2_nios2_cpu_nios2_oci_fifo File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 1427
    Info (12023): Found entity 14: nios2_nios2_cpu_nios2_oci_pib File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 1913
    Info (12023): Found entity 15: nios2_nios2_cpu_nios2_oci_im File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 1936
    Info (12023): Found entity 16: nios2_nios2_cpu_nios2_performance_monitors File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2006
    Info (12023): Found entity 17: nios2_nios2_cpu_nios2_avalon_reg File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2023
    Info (12023): Found entity 18: nios2_nios2_cpu_ociram_sp_ram_module File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2116
    Info (12023): Found entity 19: nios2_nios2_cpu_nios2_ocimem File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2181
    Info (12023): Found entity 20: nios2_nios2_cpu_nios2_oci File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2362
    Info (12023): Found entity 21: nios2_nios2_cpu File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2834
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_sysclk.v
    Info (12023): Found entity 1: nios2_nios2_cpu_debug_slave_sysclk File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_sysclk.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_tck.v
    Info (12023): Found entity 1: nios2_nios2_cpu_debug_slave_tck File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_tck.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_wrapper.v
    Info (12023): Found entity 1: nios2_nios2_cpu_debug_slave_wrapper File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_wrapper.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_test_bench.v
    Info (12023): Found entity 1: nios2_nios2_cpu_test_bench File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_test_bench.v Line: 21
Info (12021): Found 5 design units, including 5 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_jtag_uart_0.v
    Info (12023): Found entity 1: nios2_jtag_uart_0_sim_scfifo_w File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_jtag_uart_0.v Line: 21
    Info (12023): Found entity 2: nios2_jtag_uart_0_scfifo_w File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_jtag_uart_0.v Line: 78
    Info (12023): Found entity 3: nios2_jtag_uart_0_sim_scfifo_r File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_jtag_uart_0.v Line: 164
    Info (12023): Found entity 4: nios2_jtag_uart_0_scfifo_r File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_jtag_uart_0.v Line: 243
    Info (12023): Found entity 5: nios2_jtag_uart_0 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_jtag_uart_0.v Line: 331
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if.v
    Info (12023): Found entity 1: nios2_fabric_if File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if.v Line: 6
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v
    Info (12023): Found entity 1: nios2_fabric_if_mm_interconnect_0 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_rsp_mux.sv
    Info (12023): Found entity 1: nios2_fabric_if_mm_interconnect_0_rsp_mux File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_rsp_mux.sv Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_rsp_demux.sv
    Info (12023): Found entity 1: nios2_fabric_if_mm_interconnect_0_rsp_demux File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_rsp_demux.sv Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_cmd_mux.sv
    Info (12023): Found entity 1: nios2_fabric_if_mm_interconnect_0_cmd_mux File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_cmd_mux.sv Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_cmd_demux.sv
    Info (12023): Found entity 1: nios2_fabric_if_mm_interconnect_0_cmd_demux File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_cmd_demux.sv Line: 43
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_router_001.sv
    Info (12023): Found entity 1: nios2_fabric_if_mm_interconnect_0_router_001_default_decode File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_router_001.sv Line: 45
    Info (12023): Found entity 2: nios2_fabric_if_mm_interconnect_0_router_001 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_router_001.sv Line: 84
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_router.sv
    Info (12023): Found entity 1: nios2_fabric_if_mm_interconnect_0_router_default_decode File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_router.sv Line: 45
    Info (12023): Found entity 2: nios2_fabric_if_mm_interconnect_0_router File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_router.sv Line: 84
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_rot_switch.v
    Info (12023): Found entity 1: nios2_fabric_if_rot_switch File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_rot_switch.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_tx_status.v
    Info (12023): Found entity 1: nios2_TX_STATUS File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_TX_STATUS.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_own_ip_addr_in.v
    Info (12023): Found entity 1: nios2_fabric_if_own_ip_addr_in File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_own_ip_addr_in.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_avalon_mm_bridge.v
    Info (12023): Found entity 1: altera_avalon_mm_bridge File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_avalon_mm_bridge.v Line: 25
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_daq_dest_ip_addr.v
    Info (12023): Found entity 1: nios2_fabric_if_daq_dest_ip_addr File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_daq_dest_ip_addr.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_tx_ctrl.v
    Info (12023): Found entity 1: nios2_TX_CTRL File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_TX_CTRL.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_eth_tse_mac.v
    Info (12023): Found entity 1: nios2_eth_tse_mac File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_eth_tse_mac.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_mac.v
    Info (12023): Found entity 1: altera_eth_tse_mac File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_mac.v Line: 44
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_clk_cntl.v
    Info (12023): Found entity 1: altera_tse_clk_cntl File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_clk_cntl.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc328checker.v
    Info (12023): Found entity 1: altera_tse_crc328checker File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc328checker.v Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc328generator.v
    Info (12023): Found entity 1: altera_tse_crc328generator File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc328generator.v Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc32ctl8.v
    Info (12023): Found entity 1: altera_tse_crc32ctl8 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc32ctl8.v Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc32galois8.v
    Info (12023): Found entity 1: altera_tse_crc32galois8 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc32galois8.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_gmii_io.v
    Info (12023): Found entity 1: altera_tse_gmii_io File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_gmii_io.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_lb_read_cntl.v
    Info (12023): Found entity 1: altera_tse_lb_read_cntl File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_lb_read_cntl.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_lb_wrt_cntl.v
    Info (12023): Found entity 1: altera_tse_lb_wrt_cntl File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_lb_wrt_cntl.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_hashing.v
    Info (12023): Found entity 1: altera_tse_hashing File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_hashing.v Line: 44
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_host_control.v
    Info (12023): Found entity 1: altera_tse_host_control File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_host_control.v Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_host_control_small.v
    Info (12023): Found entity 1: altera_tse_host_control_small File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_host_control_small.v Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_control.v
    Info (12023): Found entity 1: altera_tse_mac_control File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_control.v Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_register_map.v
    Info (12023): Found entity 1: altera_tse_register_map File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_register_map.v Line: 44
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_register_map_small.v
    Info (12023): Found entity 1: altera_tse_register_map_small File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_register_map_small.v Line: 44
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_counter_cntl.v
    Info (12023): Found entity 1: altera_tse_rx_counter_cntl File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_counter_cntl.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_shared_mac_control.v
    Info (12023): Found entity 1: altera_tse_shared_mac_control File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_shared_mac_control.v Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_shared_register_map.v
    Info (12023): Found entity 1: altera_tse_shared_register_map File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_shared_register_map.v Line: 44
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_counter_cntl.v
    Info (12023): Found entity 1: altera_tse_tx_counter_cntl File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_counter_cntl.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_lfsr_10.v
    Info (12023): Found entity 1: altera_tse_lfsr_10 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_lfsr_10.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_loopback_ff.v
    Info (12023): Found entity 1: altera_tse_loopback_ff File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_loopback_ff.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altshifttaps.v
    Info (12023): Found entity 1: altera_tse_altshifttaps File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altshifttaps.v Line: 32
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_fifoless_mac_rx.v
    Info (12023): Found entity 1: altera_tse_fifoless_mac_rx File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_fifoless_mac_rx.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_rx.v
    Info (12023): Found entity 1: altera_tse_mac_rx File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_rx.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_fifoless_mac_tx.v
    Info (12023): Found entity 1: altera_tse_fifoless_mac_tx File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_fifoless_mac_tx.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_tx.v
    Info (12023): Found entity 1: altera_tse_mac_tx File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_tx.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_magic_detection.v
    Info (12023): Found entity 1: altera_tse_magic_detection File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_magic_detection.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mdio.v
    Info (12023): Found entity 1: altera_tse_mdio File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mdio.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mdio_clk_gen.v
    Info (12023): Found entity 1: altera_tse_mdio_clk_gen File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mdio_clk_gen.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mdio_cntl.v
    Info (12023): Found entity 1: altera_tse_mdio_cntl File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mdio_cntl.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_mdio.v
    Info (12023): Found entity 1: altera_tse_top_mdio File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_mdio.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mii_rx_if.v
    Info (12023): Found entity 1: altera_tse_mii_rx_if File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mii_rx_if.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mii_tx_if.v
    Info (12023): Found entity 1: altera_tse_mii_tx_if File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mii_tx_if.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_pipeline_base.v
    Info (12023): Found entity 1: altera_tse_pipeline_base File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_pipeline_base.v Line: 16
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_pipeline_stage.sv
    Info (12023): Found entity 1: altera_tse_pipeline_stage File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_pipeline_stage.sv Line: 16
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_dpram_16x32.v
    Info (12023): Found entity 1: altera_tse_dpram_16x32 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_dpram_16x32.v Line: 52
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_dpram_8x32.v
    Info (12023): Found entity 1: altera_tse_dpram_8x32 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_dpram_8x32.v Line: 52
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_dpram_ecc_16x32.v
    Info (12023): Found entity 1: altera_tse_dpram_ecc_16x32 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_dpram_ecc_16x32.v Line: 52
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_fifoless_retransmit_cntl.v
    Info (12023): Found entity 1: altera_tse_fifoless_retransmit_cntl File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_fifoless_retransmit_cntl.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_retransmit_cntl.v
    Info (12023): Found entity 1: altera_tse_retransmit_cntl File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_retransmit_cntl.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_in1.v
    Info (12023): Found entity 1: altera_tse_rgmii_in1 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_in1.v Line: 49
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_in4.v
    Info (12023): Found entity 1: altera_tse_rgmii_in4 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_in4.v Line: 49
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_nf_rgmii_module.v
    Info (12023): Found entity 1: altera_tse_nf_rgmii_module File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_nf_rgmii_module.v Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_module.v
    Info (12023): Found entity 1: altera_tse_rgmii_module File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_module.v Line: 44
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_out1.v
    Info (12023): Found entity 1: altera_tse_rgmii_out1 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_out1.v Line: 49
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_out4.v
    Info (12023): Found entity 1: altera_tse_rgmii_out4 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_out4.v Line: 49
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_ff.v
    Info (12023): Found entity 1: altera_tse_rx_ff File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_ff.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_min_ff.v
    Info (12023): Found entity 1: altera_tse_rx_min_ff File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_min_ff.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_ff_cntrl.v
    Info (12023): Found entity 1: altera_tse_rx_ff_cntrl File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_ff_cntrl.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_ff_cntrl_32.v
    Info (12023): Found entity 1: altera_tse_rx_ff_cntrl_32 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_ff_cntrl_32.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_ff_cntrl_32_shift16.v
    Info (12023): Found entity 1: altera_tse_rx_ff_cntrl_32_shift16 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_ff_cntrl_32_shift16.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_ff_length.v
    Info (12023): Found entity 1: altera_tse_rx_ff_length File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_ff_length.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_stat_extract.v
    Info (12023): Found entity 1: altera_tse_rx_stat_extract File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_stat_extract.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_timing_adapter32.v
    Info (12023): Found entity 1: altera_tse_timing_adapter32 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_timing_adapter32.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_timing_adapter8.v
    Info (12023): Found entity 1: altera_tse_timing_adapter8 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_timing_adapter8.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_timing_adapter_fifo32.v
    Info (12023): Found entity 1: altera_tse_timing_adapter_fifo32 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_timing_adapter_fifo32.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_timing_adapter_fifo8.v
    Info (12023): Found entity 1: altera_tse_timing_adapter_fifo8 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_timing_adapter_fifo8.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_1geth.v
    Info (12023): Found entity 1: altera_tse_top_1geth File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_1geth.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_fifoless_1geth.v
    Info (12023): Found entity 1: altera_tse_top_fifoless_1geth File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_fifoless_1geth.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo.v
    Info (12023): Found entity 1: altera_tse_top_w_fifo File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v
    Info (12023): Found entity 1: altera_tse_top_w_fifo_10_100_1000 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_wo_fifo.v
    Info (12023): Found entity 1: altera_tse_top_wo_fifo File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_wo_fifo.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.v
    Info (12023): Found entity 1: altera_tse_top_wo_fifo_10_100_1000 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_gen_host.v
    Info (12023): Found entity 1: altera_tse_top_gen_host File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_gen_host.v Line: 44
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_ff.v
    Info (12023): Found entity 1: altera_tse_tx_ff File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_ff.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_min_ff.v
    Info (12023): Found entity 1: altera_tse_tx_min_ff File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_min_ff.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_ff_cntrl.v
    Info (12023): Found entity 1: altera_tse_tx_ff_cntrl File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_ff_cntrl.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_ff_cntrl_32.v
    Info (12023): Found entity 1: altera_tse_tx_ff_cntrl_32 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_ff_cntrl_32.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_ff_cntrl_32_shift16.v
    Info (12023): Found entity 1: altera_tse_tx_ff_cntrl_32_shift16 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_ff_cntrl_32_shift16.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_ff_length.v
    Info (12023): Found entity 1: altera_tse_tx_ff_length File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_ff_length.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_ff_read_cntl.v
    Info (12023): Found entity 1: altera_tse_tx_ff_read_cntl File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_ff_read_cntl.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_stat_extract.v
    Info (12023): Found entity 1: altera_tse_tx_stat_extract File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_stat_extract.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_std_synchronizer.v
    Info (12023): Found entity 1: altera_eth_tse_std_synchronizer File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_std_synchronizer.v Line: 46
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_std_synchronizer_bundle.v
    Info (12023): Found entity 1: altera_eth_tse_std_synchronizer_bundle File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_std_synchronizer_bundle.v Line: 27
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_ptp_std_synchronizer.v
    Info (12023): Found entity 1: altera_eth_tse_ptp_std_synchronizer File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_ptp_std_synchronizer.v Line: 16
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_false_path_marker.v
    Info (12023): Found entity 1: altera_tse_false_path_marker File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_false_path_marker.v Line: 38
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_reset_synchronizer.v
    Info (12023): Found entity 1: altera_tse_reset_synchronizer File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_reset_synchronizer.v Line: 36
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_clock_crosser.v
    Info (12023): Found entity 1: altera_tse_clock_crosser File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_clock_crosser.v Line: 22
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_13.v
    Info (12023): Found entity 1: altera_tse_a_fifo_13 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_13.v Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_24.v
    Info (12023): Found entity 1: altera_tse_a_fifo_24 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_24.v Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_34.v
    Info (12023): Found entity 1: altera_tse_a_fifo_34 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_34.v Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_opt_1246.v
    Info (12023): Found entity 1: altera_tse_a_fifo_opt_1246 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_opt_1246.v Line: 53
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_opt_14_44.v
    Info (12023): Found entity 1: altera_tse_a_fifo_opt_14_44 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_opt_14_44.v Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_opt_36_10.v
    Info (12023): Found entity 1: altera_tse_a_fifo_opt_36_10 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_opt_36_10.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_gray_cnt.v
    Info (12023): Found entity 1: altera_tse_gray_cnt File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_gray_cnt.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_sdpm_altsyncram.v
    Info (12023): Found entity 1: altera_tse_sdpm_altsyncram File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_sdpm_altsyncram.v Line: 46
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v
    Info (12023): Found entity 1: altera_tse_altsyncram_dpm_fifo File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v Line: 46
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_bin_cnt.v
    Info (12023): Found entity 1: altera_tse_bin_cnt File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_bin_cnt.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ph_calculator.sv
    Info (12023): Found entity 1: altera_tse_ph_calculator File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ph_calculator.sv Line: 16
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_sdpm_gen.v
    Info (12023): Found entity 1: altera_tse_sdpm_gen File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_sdpm_gen.v Line: 42
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x10.v
    Info (12023): Found entity 1: altera_tse_ecc_dec_x10_altecc_decoder_h5f File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x10.v Line: 59
    Info (12023): Found entity 2: altera_tse_ecc_dec_x10 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x10.v Line: 164
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x10.v
    Info (12023): Found entity 1: altera_tse_ecc_enc_x10_altecc_encoder_p8b File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x10.v Line: 59
    Info (12023): Found entity 2: altera_tse_ecc_enc_x10 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x10.v Line: 90
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x10_wrapper.v
    Info (12023): Found entity 1: altera_tse_ecc_enc_x10_wrapper File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x10_wrapper.v Line: 16
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x14.v
    Info (12023): Found entity 1: altera_tse_ecc_dec_x14_altecc_decoder_cre File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x14.v Line: 59
    Info (12023): Found entity 2: altera_tse_ecc_dec_x14 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x14.v Line: 174
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x14.v
    Info (12023): Found entity 1: altera_tse_ecc_enc_x14_altecc_encoder_p8b File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x14.v Line: 59
    Info (12023): Found entity 2: altera_tse_ecc_enc_x14 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x14.v Line: 92
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x14_wrapper.v
    Info (12023): Found entity 1: altera_tse_ecc_enc_x14_wrapper File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x14_wrapper.v Line: 16
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x2.v
    Info (12023): Found entity 1: altera_tse_ecc_dec_x2_altecc_decoder_doe File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x2.v Line: 59
    Info (12023): Found entity 2: altera_tse_ecc_dec_x2 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x2.v Line: 146
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x2.v
    Info (12023): Found entity 1: altera_tse_ecc_enc_x2_altecc_encoder_q5b File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x2.v Line: 59
    Info (12023): Found entity 2: altera_tse_ecc_enc_x2 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x2.v Line: 88
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x2_wrapper.v
    Info (12023): Found entity 1: altera_tse_ecc_enc_x2_wrapper File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x2_wrapper.v Line: 16
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x23.v
    Info (12023): Found entity 1: altera_tse_ecc_dec_x23_altecc_decoder_lre File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x23.v Line: 59
    Info (12023): Found entity 2: altera_tse_ecc_dec_x23 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x23.v Line: 192
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x23.v
    Info (12023): Found entity 1: altera_tse_ecc_enc_x23_altecc_encoder_29b File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x23.v Line: 59
    Info (12023): Found entity 2: altera_tse_ecc_enc_x23 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x23.v Line: 92
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x23_wrapper.v
    Info (12023): Found entity 1: altera_tse_ecc_enc_x23_wrapper File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x23_wrapper.v Line: 16
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x36.v
    Info (12023): Found entity 1: altera_tse_ecc_dec_x36_altecc_decoder_lre File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x36.v Line: 59
    Info (12023): Found entity 2: altera_tse_ecc_dec_x36 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x36.v Line: 220
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x36.v
    Info (12023): Found entity 1: altera_tse_ecc_enc_x36_altecc_encoder_29b File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x36.v Line: 59
    Info (12023): Found entity 2: altera_tse_ecc_enc_x36 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x36.v Line: 94
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x36_wrapper.v
    Info (12023): Found entity 1: altera_tse_ecc_enc_x36_wrapper File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x36_wrapper.v Line: 16
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x40.v
    Info (12023): Found entity 1: altera_tse_ecc_dec_x40_altecc_decoder_kre File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x40.v Line: 59
    Info (12023): Found entity 2: altera_tse_ecc_dec_x40 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x40.v Line: 228
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x40.v
    Info (12023): Found entity 1: altera_tse_ecc_enc_x40_altecc_encoder_19b File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x40.v Line: 59
    Info (12023): Found entity 2: altera_tse_ecc_enc_x40 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x40.v Line: 94
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x40_wrapper.v
    Info (12023): Found entity 1: altera_tse_ecc_enc_x40_wrapper File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x40_wrapper.v Line: 16
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x30.v
    Info (12023): Found entity 1: altera_tse_ecc_dec_x30_altecc_decoder_ire File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x30.v Line: 59
    Info (12023): Found entity 2: altera_tse_ecc_dec_x30 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_dec_x30.v Line: 208
Info (12021): Found 2 design units, including 2 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x30.v
    Info (12023): Found entity 1: altera_tse_ecc_enc_x30_altecc_encoder_v8b File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x30.v Line: 59
    Info (12023): Found entity 2: altera_tse_ecc_enc_x30 File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x30.v Line: 94
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x30_wrapper.v
    Info (12023): Found entity 1: altera_tse_ecc_enc_x30_wrapper File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_enc_x30_wrapper.v Line: 16
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_status_crosser.v
    Info (12023): Found entity 1: altera_tse_ecc_status_crosser File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_ecc_status_crosser.v Line: 18
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_std_synchronizer_nocut.v
    Info (12023): Found entity 1: altera_std_synchronizer_nocut File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_std_synchronizer_nocut.v Line: 44
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_udp_dpram.v
    Info (12023): Found entity 1: nios2_enet_udp_dpram File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_udp_dpram.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_tx_msgdma.v
    Info (12023): Found entity 1: nios2_enet_tx_msgdma File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_tx_msgdma.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_master.v
    Info (12023): Found entity 1: read_master File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_master.v Line: 73
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/mm_to_st_adapter.v
    Info (12023): Found entity 1: MM_to_ST_Adapter File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/MM_to_ST_Adapter.v Line: 53
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_burst_control.v
    Info (12023): Found entity 1: read_burst_control File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_burst_control.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/dispatcher.v
    Info (12023): Found entity 1: dispatcher File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/dispatcher.v Line: 76
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/descriptor_buffers.v
    Info (12023): Found entity 1: descriptor_buffers File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/descriptor_buffers.v Line: 54
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/csr_block.v
    Info (12023): Found entity 1: csr_block File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/csr_block.v Line: 99
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/response_block.v
    Info (12023): Found entity 1: response_block File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/response_block.v Line: 61
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/fifo_with_byteenables.v
    Info (12023): Found entity 1: fifo_with_byteenables File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/fifo_with_byteenables.v Line: 45
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_signal_breakout.v
    Info (12023): Found entity 1: read_signal_breakout File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_signal_breakout.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_signal_breakout.v
    Info (12023): Found entity 1: write_signal_breakout File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_signal_breakout.v Line: 41
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_rx_msgdma.v
    Info (12023): Found entity 1: nios2_enet_rx_msgdma File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_rx_msgdma.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_master.v
    Info (12023): Found entity 1: write_master File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_master.v Line: 66
Info (12021): Found 8 design units, including 8 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/byte_enable_generator.v
    Info (12023): Found entity 1: byte_enable_generator File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/byte_enable_generator.v Line: 54
    Info (12023): Found entity 2: one_thousand_twenty_four_byteenable_FSM File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/byte_enable_generator.v Line: 177
    Info (12023): Found entity 3: five_hundred_twelve_bit_byteenable_FSM File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/byte_enable_generator.v Line: 285
    Info (12023): Found entity 4: two_hundred_fifty_six_bit_byteenable_FSM File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/byte_enable_generator.v Line: 393
    Info (12023): Found entity 5: one_hundred_twenty_eight_bit_byteenable_FSM File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/byte_enable_generator.v Line: 500
    Info (12023): Found entity 6: sixty_four_bit_byteenable_FSM File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/byte_enable_generator.v Line: 606
    Info (12023): Found entity 7: thirty_two_bit_byteenable_FSM File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/byte_enable_generator.v Line: 711
    Info (12023): Found entity 8: sixteen_bit_byteenable_FSM File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/byte_enable_generator.v Line: 818
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/st_to_mm_adapter.v
    Info (12023): Found entity 1: ST_to_MM_Adapter File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/ST_to_MM_Adapter.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_burst_control.v
    Info (12023): Found entity 1: write_burst_control File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_burst_control.v Line: 56
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_nios_tx_dpram.v
    Info (12023): Found entity 1: nios2_enet_nios_tx_dpram File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_nios_tx_dpram.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_nios_rx_dpram.v
    Info (12023): Found entity 1: nios2_enet_nios_rx_dpram File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_nios_rx_dpram.v Line: 21
Info (12021): Found 4 design units, including 4 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_ser_fifo_rx.v
    Info (12023): Found entity 1: nios2_SER_FIFO_RX_dual_clock_fifo File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_SER_FIFO_RX.v Line: 21
    Info (12023): Found entity 2: nios2_SER_FIFO_RX_dcfifo_with_controls File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_SER_FIFO_RX.v Line: 103
    Info (12023): Found entity 3: nios2_SER_FIFO_RX_map_avalonmm_to_avalonst File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_SER_FIFO_RX.v Line: 492
    Info (12023): Found entity 4: nios2_SER_FIFO_RX File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_SER_FIFO_RX.v Line: 519
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/src/eth_msgdma_csr_sm.vhd
    Info (12022): Found design unit 1: ETH_MSGDMA_CSR_SM-Behavioral File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_CSR_SM.vhd Line: 33
    Info (12023): Found entity 1: ETH_MSGDMA_CSR_SM File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_CSR_SM.vhd Line: 10
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/src/eth_msgdma_desc_sm.vhd
    Info (12022): Found design unit 1: ETH_MSGDMA_DESC_SM-Behavioral File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_DESC_SM.vhd Line: 37
    Info (12023): Found entity 1: ETH_MSGDMA_DESC_SM File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_DESC_SM.vhd Line: 10
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/src/eth_msgdma_dispatcher.vhd
    Info (12022): Found design unit 1: ETH_MSGDMA_DISPATCHER-Behavioral File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_DISPATCHER.vhd Line: 57
    Info (12023): Found entity 1: ETH_MSGDMA_DISPATCHER File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_DISPATCHER.vhd Line: 10
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/eth_msgdma_irq_fifo.vhd
    Info (12022): Found design unit 1: eth_msgdma_irq_fifo-SYN File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_MSGDMA_IRQ_FIFO.vhd Line: 58
    Info (12023): Found entity 1: ETH_MSGDMA_IRQ_FIFO File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_MSGDMA_IRQ_FIFO.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/src/eth_fifo_check.vhd
    Info (12022): Found design unit 1: ETH_FIFO_CHECK-Behavioral File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_FIFO_CHECK.vhd Line: 30
    Info (12023): Found entity 1: ETH_FIFO_CHECK File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_FIFO_CHECK.vhd Line: 10
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/src/eth_fifos_to_dpram_sm.vhd
    Info (12022): Found design unit 1: ETH_FIFOS_TO_DPRAM_SM-Behavioral File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_FIFOS_TO_DPRAM_SM.vhd Line: 57
    Info (12023): Found entity 1: ETH_FIFOS_TO_DPRAM_SM File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_FIFOS_TO_DPRAM_SM.vhd Line: 10
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/src/eth_msgdma_wrapper.vhd
    Info (12022): Found design unit 1: ETH_MSGDMA_WRAPPER-Behavioral File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_WRAPPER.vhd Line: 91
    Info (12023): Found entity 1: ETH_MSGDMA_WRAPPER File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_WRAPPER.vhd Line: 13
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/src/eth_wrapper.vhd
    Info (12022): Found design unit 1: ETH_WRAPPER-Behavioral File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_WRAPPER.vhd Line: 91
    Info (12023): Found entity 1: ETH_WRAPPER File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_WRAPPER.vhd Line: 15
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/src/eth_ufp_wrapper.vhd
    Info (12022): Found design unit 1: ETH_UFP_WRAPPER-Behavioral File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_UFP_WRAPPER.vhd Line: 131
    Info (12023): Found entity 1: ETH_UFP_WRAPPER File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_UFP_WRAPPER.vhd Line: 19
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/eth_tx_clk.vhd
    Info (12022): Found design unit 1: eth_tx_clk-SYN File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_TX_CLK.vhd Line: 53
    Info (12023): Found entity 1: ETH_TX_CLK File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_TX_CLK.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/eth_sc_fifo_tx.vhd
    Info (12022): Found design unit 1: eth_sc_fifo_tx-SYN File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_SC_FIFO_TX.vhd Line: 59
    Info (12023): Found entity 1: ETH_SC_FIFO_TX File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_SC_FIFO_TX.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/eth_sc_fifo_rx.vhd
    Info (12022): Found design unit 1: eth_sc_fifo_rx-SYN File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_SC_FIFO_RX.vhd Line: 57
    Info (12023): Found entity 1: ETH_SC_FIFO_RX File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_SC_FIFO_RX.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/pll_main.vhd
    Info (12022): Found design unit 1: PLL_MAIN-rtl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN.vhd Line: 21
    Info (12023): Found entity 1: PLL_MAIN File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN.vhd Line: 11
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/pll_main/pll_main_0002.v
    Info (12023): Found entity 1: PLL_MAIN_0002 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN/PLL_MAIN_0002.v Line: 2
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/pll_4k.vhd
    Info (12022): Found design unit 1: PLL_4K-rtl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K.vhd Line: 29
    Info (12023): Found entity 1: PLL_4K File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K.vhd Line: 11
Info (12021): Found 1 design units, including 1 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/pll_4k/pll_4k_0002.v
    Info (12023): Found entity 1: PLL_4K_0002 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K/PLL_4K_0002.v Line: 2
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/ftr_fine_phase_sm.vhd
    Info (12022): Found design unit 1: FTR_FINE_PHASE_SM-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FINE_PHASE_SM.vhd Line: 37
    Info (12023): Found entity 1: FTR_FINE_PHASE_SM File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FINE_PHASE_SM.vhd Line: 10
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/ftr_patchpanelcontrollersm.vhd
    Info (12022): Found design unit 1: FTR_PatchPanelControllerSM-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PatchPanelControllerSM.vhd Line: 51
    Info (12023): Found entity 1: FTR_PatchPanelControllerSM File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PatchPanelControllerSM.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/ftr_planecontrollersm.vhd
    Info (12022): Found design unit 1: FTR_PlaneControllerSM-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PlaneControllerSM.vhd Line: 69
    Info (12023): Found entity 1: FTR_PlaneControllerSM File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PlaneControllerSM.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/ftr_planecontroller.vhd
    Info (12022): Found design unit 1: FTR_PlaneController-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PlaneController.vhd Line: 70
    Info (12023): Found entity 1: FTR_PlaneController File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PlaneController.vhd Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/ftr_rxdatamodulemanager.vhd
    Info (12022): Found design unit 1: FTR_RXDataModuleManager-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_RXDataModuleManager.vhd Line: 40
    Info (12023): Found entity 1: FTR_RXDataModuleManager File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_RXDataModuleManager.vhd Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/ftr_rxdataplanemanager.vhd
    Info (12022): Found design unit 1: FTR_RXDataPlaneManager-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_RXDataPlaneManager.vhd Line: 48
    Info (12023): Found entity 1: FTR_RXDataPlaneManager File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_RXDataPlaneManager.vhd Line: 16
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/ftr_l2_sm.vhd
    Info (12022): Found design unit 1: FTR_L2_SM-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_SM.vhd Line: 61
    Info (12023): Found entity 1: FTR_L2_SM File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_SM.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/ftr_faserwrapper.vhd
    Info (12022): Found design unit 1: FTR_FaserWrapper-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FaserWrapper.vhd Line: 150
    Info (12023): Found entity 1: FTR_FaserWrapper File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FaserWrapper.vhd Line: 14
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/ftr_clk_wrapper.vhd
    Info (12022): Found design unit 1: FTR_CLK_WRAPPER-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_CLK_WRAPPER.vhd Line: 52
    Info (12023): Found entity 1: FTR_CLK_WRAPPER File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_CLK_WRAPPER.vhd Line: 17
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/ftr_reg_wrapper.vhd
    Info (12022): Found design unit 1: FTR_REG_WRAPPER-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 54
    Info (12023): Found entity 1: FTR_REG_WRAPPER File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 18
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/ftr_l2_fifo.vhd
    Info (12022): Found design unit 1: ftr_l2_fifo-SYN File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_FIFO.vhd Line: 60
    Info (12023): Found entity 1: FTR_L2_FIFO File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_FIFO.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/ftr_l1_fifo.vhd
    Info (12022): Found design unit 1: ftr_l1_fifo-SYN File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L1_FIFO.vhd Line: 60
    Info (12023): Found entity 1: FTR_L1_FIFO File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L1_FIFO.vhd Line: 42
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/projets/ftr_fasertrackerreadout/src/ftr_global_const.vhd
    Info (12022): Found design unit 1: FTR_GLOBAL_CONST File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_GLOBAL_CONST.vhd Line: 14
Info (12021): Found 2 design units, including 1 entities, in source file src/ftr_top.vhd
    Info (12022): Found design unit 1: FTR_TOP-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 217
    Info (12023): Found entity 1: FTR_TOP File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 15
Info (12127): Elaborating entity "FTR_TOP" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at FTR_TOP.vhd(247): object "sl_int_clk32" assigned a value but never read File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 247
Warning (10036): Verilog HDL or VHDL warning at FTR_TOP.vhd(354): object "sl_int_sct_cmd1_0_g" assigned a value but never read File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 354
Info (12128): Elaborating entity "FTR_CLK_WRAPPER" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 371
Info (12128): Elaborating entity "PLL_MAIN" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_CLK_WRAPPER.vhd Line: 104
Info (12128): Elaborating entity "PLL_MAIN_0002" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN.vhd Line: 34
Info (12128): Elaborating entity "altera_pll" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN/PLL_MAIN_0002.v Line: 88
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus
Info (12130): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN/PLL_MAIN_0002.v Line: 88
Info (12133): Instantiated megafunction "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i" with the following parameter: File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN/PLL_MAIN_0002.v Line: 88
    Info (12134): Parameter "fractional_vco_multiplier" = "false"
    Info (12134): Parameter "reference_clock_frequency" = "40.0 MHz"
    Info (12134): Parameter "operation_mode" = "direct"
    Info (12134): Parameter "number_of_clocks" = "2"
    Info (12134): Parameter "output_clock_frequency0" = "40.000000 MHz"
    Info (12134): Parameter "phase_shift0" = "0 ps"
    Info (12134): Parameter "duty_cycle0" = "50"
    Info (12134): Parameter "output_clock_frequency1" = "32.000000 MHz"
    Info (12134): Parameter "phase_shift1" = "0 ps"
    Info (12134): Parameter "duty_cycle1" = "50"
    Info (12134): Parameter "output_clock_frequency2" = "0 MHz"
    Info (12134): Parameter "phase_shift2" = "0 ps"
    Info (12134): Parameter "duty_cycle2" = "50"
    Info (12134): Parameter "output_clock_frequency3" = "0 MHz"
    Info (12134): Parameter "phase_shift3" = "0 ps"
    Info (12134): Parameter "duty_cycle3" = "50"
    Info (12134): Parameter "output_clock_frequency4" = "0 MHz"
    Info (12134): Parameter "phase_shift4" = "0 ps"
    Info (12134): Parameter "duty_cycle4" = "50"
    Info (12134): Parameter "output_clock_frequency5" = "0 MHz"
    Info (12134): Parameter "phase_shift5" = "0 ps"
    Info (12134): Parameter "duty_cycle5" = "50"
    Info (12134): Parameter "output_clock_frequency6" = "0 MHz"
    Info (12134): Parameter "phase_shift6" = "0 ps"
    Info (12134): Parameter "duty_cycle6" = "50"
    Info (12134): Parameter "output_clock_frequency7" = "0 MHz"
    Info (12134): Parameter "phase_shift7" = "0 ps"
    Info (12134): Parameter "duty_cycle7" = "50"
    Info (12134): Parameter "output_clock_frequency8" = "0 MHz"
    Info (12134): Parameter "phase_shift8" = "0 ps"
    Info (12134): Parameter "duty_cycle8" = "50"
    Info (12134): Parameter "output_clock_frequency9" = "0 MHz"
    Info (12134): Parameter "phase_shift9" = "0 ps"
    Info (12134): Parameter "duty_cycle9" = "50"
    Info (12134): Parameter "output_clock_frequency10" = "0 MHz"
    Info (12134): Parameter "phase_shift10" = "0 ps"
    Info (12134): Parameter "duty_cycle10" = "50"
    Info (12134): Parameter "output_clock_frequency11" = "0 MHz"
    Info (12134): Parameter "phase_shift11" = "0 ps"
    Info (12134): Parameter "duty_cycle11" = "50"
    Info (12134): Parameter "output_clock_frequency12" = "0 MHz"
    Info (12134): Parameter "phase_shift12" = "0 ps"
    Info (12134): Parameter "duty_cycle12" = "50"
    Info (12134): Parameter "output_clock_frequency13" = "0 MHz"
    Info (12134): Parameter "phase_shift13" = "0 ps"
    Info (12134): Parameter "duty_cycle13" = "50"
    Info (12134): Parameter "output_clock_frequency14" = "0 MHz"
    Info (12134): Parameter "phase_shift14" = "0 ps"
    Info (12134): Parameter "duty_cycle14" = "50"
    Info (12134): Parameter "output_clock_frequency15" = "0 MHz"
    Info (12134): Parameter "phase_shift15" = "0 ps"
    Info (12134): Parameter "duty_cycle15" = "50"
    Info (12134): Parameter "output_clock_frequency16" = "0 MHz"
    Info (12134): Parameter "phase_shift16" = "0 ps"
    Info (12134): Parameter "duty_cycle16" = "50"
    Info (12134): Parameter "output_clock_frequency17" = "0 MHz"
    Info (12134): Parameter "phase_shift17" = "0 ps"
    Info (12134): Parameter "duty_cycle17" = "50"
    Info (12134): Parameter "pll_type" = "General"
    Info (12134): Parameter "pll_subtype" = "General"
Info (12128): Elaborating entity "PLL_4K" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_CLK_WRAPPER.vhd Line: 116
Info (12128): Elaborating entity "PLL_4K_0002" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K.vhd Line: 50
Info (12128): Elaborating entity "altera_pll" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K/PLL_4K_0002.v Line: 263
Warning (10034): Output port "lvds_clk" at altera_pll.v(319) has no driver File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 319
Warning (10034): Output port "loaden" at altera_pll.v(320) has no driver File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 320
Warning (10034): Output port "extclk_out" at altera_pll.v(321) has no driver File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 321
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus
Info (12130): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K/PLL_4K_0002.v Line: 263
Info (12133): Instantiated megafunction "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" with the following parameter: File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K/PLL_4K_0002.v Line: 263
    Info (12134): Parameter "fractional_vco_multiplier" = "false"
    Info (12134): Parameter "reference_clock_frequency" = "40.0 MHz"
    Info (12134): Parameter "pll_fractional_cout" = "32"
    Info (12134): Parameter "pll_dsm_out_sel" = "1st_order"
    Info (12134): Parameter "operation_mode" = "source synchronous"
    Info (12134): Parameter "number_of_clocks" = "5"
    Info (12134): Parameter "output_clock_frequency0" = "40.000000 MHz"
    Info (12134): Parameter "phase_shift0" = "0 ps"
    Info (12134): Parameter "duty_cycle0" = "50"
    Info (12134): Parameter "output_clock_frequency1" = "40.000000 MHz"
    Info (12134): Parameter "phase_shift1" = "0 ps"
    Info (12134): Parameter "duty_cycle1" = "50"
    Info (12134): Parameter "output_clock_frequency2" = "40.000000 MHz"
    Info (12134): Parameter "phase_shift2" = "0 ps"
    Info (12134): Parameter "duty_cycle2" = "50"
    Info (12134): Parameter "output_clock_frequency3" = "40.000000 MHz"
    Info (12134): Parameter "phase_shift3" = "0 ps"
    Info (12134): Parameter "duty_cycle3" = "50"
    Info (12134): Parameter "output_clock_frequency4" = "40.000000 MHz"
    Info (12134): Parameter "phase_shift4" = "0 ps"
    Info (12134): Parameter "duty_cycle4" = "50"
    Info (12134): Parameter "output_clock_frequency5" = "0 MHz"
    Info (12134): Parameter "phase_shift5" = "0 ps"
    Info (12134): Parameter "duty_cycle5" = "50"
    Info (12134): Parameter "output_clock_frequency6" = "0 MHz"
    Info (12134): Parameter "phase_shift6" = "0 ps"
    Info (12134): Parameter "duty_cycle6" = "50"
    Info (12134): Parameter "output_clock_frequency7" = "0 MHz"
    Info (12134): Parameter "phase_shift7" = "0 ps"
    Info (12134): Parameter "duty_cycle7" = "50"
    Info (12134): Parameter "output_clock_frequency8" = "0 MHz"
    Info (12134): Parameter "phase_shift8" = "0 ps"
    Info (12134): Parameter "duty_cycle8" = "50"
    Info (12134): Parameter "output_clock_frequency9" = "0 MHz"
    Info (12134): Parameter "phase_shift9" = "0 ps"
    Info (12134): Parameter "duty_cycle9" = "50"
    Info (12134): Parameter "output_clock_frequency10" = "0 MHz"
    Info (12134): Parameter "phase_shift10" = "0 ps"
    Info (12134): Parameter "duty_cycle10" = "50"
    Info (12134): Parameter "output_clock_frequency11" = "0 MHz"
    Info (12134): Parameter "phase_shift11" = "0 ps"
    Info (12134): Parameter "duty_cycle11" = "50"
    Info (12134): Parameter "output_clock_frequency12" = "0 MHz"
    Info (12134): Parameter "phase_shift12" = "0 ps"
    Info (12134): Parameter "duty_cycle12" = "50"
    Info (12134): Parameter "output_clock_frequency13" = "0 MHz"
    Info (12134): Parameter "phase_shift13" = "0 ps"
    Info (12134): Parameter "duty_cycle13" = "50"
    Info (12134): Parameter "output_clock_frequency14" = "0 MHz"
    Info (12134): Parameter "phase_shift14" = "0 ps"
    Info (12134): Parameter "duty_cycle14" = "50"
    Info (12134): Parameter "output_clock_frequency15" = "0 MHz"
    Info (12134): Parameter "phase_shift15" = "0 ps"
    Info (12134): Parameter "duty_cycle15" = "50"
    Info (12134): Parameter "output_clock_frequency16" = "0 MHz"
    Info (12134): Parameter "phase_shift16" = "0 ps"
    Info (12134): Parameter "duty_cycle16" = "50"
    Info (12134): Parameter "output_clock_frequency17" = "0 MHz"
    Info (12134): Parameter "phase_shift17" = "0 ps"
    Info (12134): Parameter "duty_cycle17" = "50"
    Info (12134): Parameter "pll_type" = "Cyclone V"
    Info (12134): Parameter "pll_subtype" = "DPS"
    Info (12134): Parameter "m_cnt_hi_div" = "4"
    Info (12134): Parameter "m_cnt_lo_div" = "4"
    Info (12134): Parameter "n_cnt_hi_div" = "256"
    Info (12134): Parameter "n_cnt_lo_div" = "256"
    Info (12134): Parameter "m_cnt_bypass_en" = "false"
    Info (12134): Parameter "n_cnt_bypass_en" = "true"
    Info (12134): Parameter "m_cnt_odd_div_duty_en" = "false"
    Info (12134): Parameter "n_cnt_odd_div_duty_en" = "false"
    Info (12134): Parameter "c_cnt_hi_div0" = "4"
    Info (12134): Parameter "c_cnt_lo_div0" = "4"
    Info (12134): Parameter "c_cnt_prst0" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst0" = "0"
    Info (12134): Parameter "c_cnt_in_src0" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en0" = "false"
    Info (12134): Parameter "c_cnt_odd_div_duty_en0" = "false"
    Info (12134): Parameter "c_cnt_hi_div1" = "4"
    Info (12134): Parameter "c_cnt_lo_div1" = "4"
    Info (12134): Parameter "c_cnt_prst1" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst1" = "0"
    Info (12134): Parameter "c_cnt_in_src1" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en1" = "false"
    Info (12134): Parameter "c_cnt_odd_div_duty_en1" = "false"
    Info (12134): Parameter "c_cnt_hi_div2" = "4"
    Info (12134): Parameter "c_cnt_lo_div2" = "4"
    Info (12134): Parameter "c_cnt_prst2" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst2" = "0"
    Info (12134): Parameter "c_cnt_in_src2" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en2" = "false"
    Info (12134): Parameter "c_cnt_odd_div_duty_en2" = "false"
    Info (12134): Parameter "c_cnt_hi_div3" = "4"
    Info (12134): Parameter "c_cnt_lo_div3" = "4"
    Info (12134): Parameter "c_cnt_prst3" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst3" = "0"
    Info (12134): Parameter "c_cnt_in_src3" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en3" = "false"
    Info (12134): Parameter "c_cnt_odd_div_duty_en3" = "false"
    Info (12134): Parameter "c_cnt_hi_div4" = "4"
    Info (12134): Parameter "c_cnt_lo_div4" = "4"
    Info (12134): Parameter "c_cnt_prst4" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst4" = "0"
    Info (12134): Parameter "c_cnt_in_src4" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en4" = "false"
    Info (12134): Parameter "c_cnt_odd_div_duty_en4" = "false"
    Info (12134): Parameter "c_cnt_hi_div5" = "1"
    Info (12134): Parameter "c_cnt_lo_div5" = "1"
    Info (12134): Parameter "c_cnt_prst5" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst5" = "0"
    Info (12134): Parameter "c_cnt_in_src5" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en5" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en5" = "false"
    Info (12134): Parameter "c_cnt_hi_div6" = "1"
    Info (12134): Parameter "c_cnt_lo_div6" = "1"
    Info (12134): Parameter "c_cnt_prst6" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst6" = "0"
    Info (12134): Parameter "c_cnt_in_src6" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en6" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en6" = "false"
    Info (12134): Parameter "c_cnt_hi_div7" = "1"
    Info (12134): Parameter "c_cnt_lo_div7" = "1"
    Info (12134): Parameter "c_cnt_prst7" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst7" = "0"
    Info (12134): Parameter "c_cnt_in_src7" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en7" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en7" = "false"
    Info (12134): Parameter "c_cnt_hi_div8" = "1"
    Info (12134): Parameter "c_cnt_lo_div8" = "1"
    Info (12134): Parameter "c_cnt_prst8" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst8" = "0"
    Info (12134): Parameter "c_cnt_in_src8" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en8" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en8" = "false"
    Info (12134): Parameter "c_cnt_hi_div9" = "1"
    Info (12134): Parameter "c_cnt_lo_div9" = "1"
    Info (12134): Parameter "c_cnt_prst9" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst9" = "0"
    Info (12134): Parameter "c_cnt_in_src9" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en9" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en9" = "false"
    Info (12134): Parameter "c_cnt_hi_div10" = "1"
    Info (12134): Parameter "c_cnt_lo_div10" = "1"
    Info (12134): Parameter "c_cnt_prst10" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst10" = "0"
    Info (12134): Parameter "c_cnt_in_src10" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en10" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en10" = "false"
    Info (12134): Parameter "c_cnt_hi_div11" = "1"
    Info (12134): Parameter "c_cnt_lo_div11" = "1"
    Info (12134): Parameter "c_cnt_prst11" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst11" = "0"
    Info (12134): Parameter "c_cnt_in_src11" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en11" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en11" = "false"
    Info (12134): Parameter "c_cnt_hi_div12" = "1"
    Info (12134): Parameter "c_cnt_lo_div12" = "1"
    Info (12134): Parameter "c_cnt_prst12" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst12" = "0"
    Info (12134): Parameter "c_cnt_in_src12" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en12" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en12" = "false"
    Info (12134): Parameter "c_cnt_hi_div13" = "1"
    Info (12134): Parameter "c_cnt_lo_div13" = "1"
    Info (12134): Parameter "c_cnt_prst13" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst13" = "0"
    Info (12134): Parameter "c_cnt_in_src13" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en13" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en13" = "false"
    Info (12134): Parameter "c_cnt_hi_div14" = "1"
    Info (12134): Parameter "c_cnt_lo_div14" = "1"
    Info (12134): Parameter "c_cnt_prst14" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst14" = "0"
    Info (12134): Parameter "c_cnt_in_src14" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en14" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en14" = "false"
    Info (12134): Parameter "c_cnt_hi_div15" = "1"
    Info (12134): Parameter "c_cnt_lo_div15" = "1"
    Info (12134): Parameter "c_cnt_prst15" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst15" = "0"
    Info (12134): Parameter "c_cnt_in_src15" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en15" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en15" = "false"
    Info (12134): Parameter "c_cnt_hi_div16" = "1"
    Info (12134): Parameter "c_cnt_lo_div16" = "1"
    Info (12134): Parameter "c_cnt_prst16" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst16" = "0"
    Info (12134): Parameter "c_cnt_in_src16" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en16" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en16" = "false"
    Info (12134): Parameter "c_cnt_hi_div17" = "1"
    Info (12134): Parameter "c_cnt_lo_div17" = "1"
    Info (12134): Parameter "c_cnt_prst17" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst17" = "0"
    Info (12134): Parameter "c_cnt_in_src17" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en17" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en17" = "false"
    Info (12134): Parameter "pll_vco_div" = "2"
    Info (12134): Parameter "pll_cp_current" = "20"
    Info (12134): Parameter "pll_bwctrl" = "4000"
    Info (12134): Parameter "pll_output_clk_frequency" = "320.0 MHz"
    Info (12134): Parameter "pll_fractional_division" = "1"
    Info (12134): Parameter "mimic_fbclk_type" = "gclk"
    Info (12134): Parameter "pll_fbclk_mux_1" = "glb"
    Info (12134): Parameter "pll_fbclk_mux_2" = "fb_1"
    Info (12134): Parameter "pll_m_cnt_in_src" = "ph_mux_clk"
    Info (12134): Parameter "pll_slf_rst" = "false"
Info (12128): Elaborating entity "dps_extra_kick" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 768
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 768
Info (12128): Elaborating entity "dprio_init" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 783
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 783
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 1960
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 1960
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 1971
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 1971
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 1982
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 1982
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 1993
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 1993
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 2004
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 2004
Info (12128): Elaborating entity "altera_cyclonev_pll" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 2223
Warning (10034): Output port "extclk" at altera_cyclonev_pll.v(631) has no driver File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 631
Warning (10034): Output port "clkout[0]" at altera_cyclonev_pll.v(636) has no driver File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 636
Warning (10034): Output port "loaden" at altera_cyclonev_pll.v(640) has no driver File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 640
Warning (10034): Output port "lvdsclk" at altera_cyclonev_pll.v(641) has no driver File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 641
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 2223
Info (12128): Elaborating entity "altera_cyclonev_pll_base" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 1152
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 1152
Info (12128): Elaborating entity "FTR_FINE_PHASE_SM" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_CLK_WRAPPER.vhd Line: 134
Info (12128): Elaborating entity "ETH_UFP_WRAPPER" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 407
Info (12128): Elaborating entity "ETH_WRAPPER" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER" File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_UFP_WRAPPER.vhd Line: 185
Info (12128): Elaborating entity "nios2" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS" File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_WRAPPER.vhd Line: 142
Info (12128): Elaborating entity "nios2_SER_FIFO_RX" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 255
Info (12128): Elaborating entity "nios2_SER_FIFO_RX_dcfifo_with_controls" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_SER_FIFO_RX.v Line: 593
Info (12128): Elaborating entity "nios2_SER_FIFO_RX_dual_clock_fifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_SER_FIFO_RX.v Line: 211
Info (12128): Elaborating entity "dcfifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_SER_FIFO_RX.v Line: 72
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_SER_FIFO_RX.v Line: 72
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_SER_FIFO_RX.v Line: 72
    Info (12134): Parameter "add_ram_output_register" = "OFF"
    Info (12134): Parameter "clocks_are_synchronized" = "FALSE"
    Info (12134): Parameter "intended_device_family" = "CYCLONEV"
    Info (12134): Parameter "lpm_hint" = "DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT"
    Info (12134): Parameter "lpm_numwords" = "2048"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_width" = "32"
    Info (12134): Parameter "lpm_widthu" = "11"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "4"
    Info (12134): Parameter "read_aclr_synch" = "ON"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "write_aclr_synch" = "ON"
    Info (12134): Parameter "wrsync_delaypipe" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_iq62.tdf
    Info (12023): Found entity 1: dcfifo_iq62 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_iq62.tdf Line: 42
Info (12128): Elaborating entity "dcfifo_iq62" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo.tdf Line: 190
Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_qab.tdf
    Info (12023): Found entity 1: a_gray2bin_qab File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_gray2bin_qab.tdf Line: 22
Info (12128): Elaborating entity "a_gray2bin_qab" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_iq62.tdf Line: 57
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_pv6.tdf
    Info (12023): Found entity 1: a_graycounter_pv6 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_graycounter_pv6.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_pv6" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|a_graycounter_pv6:rdptr_g1p" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_iq62.tdf Line: 59
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_ldc.tdf
    Info (12023): Found entity 1: a_graycounter_ldc File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_graycounter_ldc.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_ldc" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|a_graycounter_ldc:wrptr_g1p" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_iq62.tdf Line: 60
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_m8d1.tdf
    Info (12023): Found entity 1: altsyncram_m8d1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_m8d1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_m8d1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|altsyncram_m8d1:fifo_ram" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_iq62.tdf Line: 61
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_3dc.tdf
    Info (12023): Found entity 1: dffpipe_3dc File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_3dc.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_3dc" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|dffpipe_3dc:rdaclr" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_iq62.tdf Line: 68
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_apl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_apl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_apl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_apl" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_iq62.tdf Line: 69
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_re9.tdf
    Info (12023): Found entity 1: dffpipe_re9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_re9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_re9" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe14" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_apl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf
    Info (12023): Found entity 1: dffpipe_qe9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_qe9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_qe9" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|dffpipe_qe9:ws_brp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_iq62.tdf Line: 71
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_bpl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_bpl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_bpl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_bpl" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_iq62.tdf Line: 73
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_se9.tdf
    Info (12023): Found entity 1: dffpipe_se9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_se9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_se9" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_se9:dffpipe18" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_bpl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_b06.tdf
    Info (12023): Found entity 1: cmpr_b06 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cmpr_b06.tdf Line: 22
Info (12128): Elaborating entity "cmpr_b06" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|nios2_SER_FIFO_RX_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_iq62:auto_generated|cmpr_b06:rdempty_eq_comp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_iq62.tdf Line: 77
Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|altera_std_synchronizer:rdreq_sync_i" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_SER_FIFO_RX.v Line: 219
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|altera_std_synchronizer:rdreq_sync_i" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_SER_FIFO_RX.v Line: 219
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_dcfifo_with_controls:the_dcfifo_with_controls|altera_std_synchronizer:rdreq_sync_i" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_SER_FIFO_RX.v Line: 219
    Info (12134): Parameter "depth" = "4"
Info (12128): Elaborating entity "nios2_SER_FIFO_RX_map_avalonmm_to_avalonst" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_SER_FIFO_RX:ser_fifo_rx|nios2_SER_FIFO_RX_map_avalonmm_to_avalonst:the_map_avalonmm_to_avalonst" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_SER_FIFO_RX.v Line: 602
Info (12128): Elaborating entity "nios2_TX_CTRL" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_CTRL:tx_ctrl" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 266
Info (12128): Elaborating entity "nios2_TX_STATUS" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_TX_STATUS:tx_status" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 274
Info (12128): Elaborating entity "nios2_enet_nios_rx_dpram" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 295
Info (12128): Elaborating entity "altsyncram" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram|altsyncram:the_altsyncram" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_nios_rx_dpram.v Line: 94
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram|altsyncram:the_altsyncram" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_nios_rx_dpram.v Line: 94
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram|altsyncram:the_altsyncram" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_nios_rx_dpram.v Line: 94
    Info (12134): Parameter "address_reg_b" = "CLOCK0"
    Info (12134): Parameter "byte_size" = "8"
    Info (12134): Parameter "byteena_reg_b" = "CLOCK0"
    Info (12134): Parameter "indata_reg_b" = "CLOCK0"
    Info (12134): Parameter "init_file" = "UNUSED"
    Info (12134): Parameter "lpm_type" = "altsyncram"
    Info (12134): Parameter "maximum_depth" = "512"
    Info (12134): Parameter "numwords_a" = "512"
    Info (12134): Parameter "numwords_b" = "512"
    Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT"
    Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED"
    Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED"
    Info (12134): Parameter "ram_block_type" = "AUTO"
    Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info (12134): Parameter "width_a" = "32"
    Info (12134): Parameter "width_b" = "32"
    Info (12134): Parameter "width_byteena_a" = "4"
    Info (12134): Parameter "width_byteena_b" = "4"
    Info (12134): Parameter "widthad_a" = "9"
    Info (12134): Parameter "widthad_b" = "9"
    Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_g572.tdf
    Info (12023): Found entity 1: altsyncram_g572 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_g572.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_g572" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_rx_dpram:enet_nios_rx_dpram|altsyncram:the_altsyncram|altsyncram_g572:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
Info (12128): Elaborating entity "nios2_enet_nios_tx_dpram" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_nios_tx_dpram:enet_nios_tx_dpram" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 316
Info (12128): Elaborating entity "nios2_enet_rx_msgdma" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 349
Info (12128): Elaborating entity "dispatcher" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_rx_msgdma.v Line: 94
Info (12128): Elaborating entity "descriptor_buffers" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/dispatcher.v Line: 306
Info (12128): Elaborating entity "write_signal_breakout" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|write_signal_breakout:the_write_signal_breakout" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/descriptor_buffers.v Line: 251
Info (12128): Elaborating entity "read_signal_breakout" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|read_signal_breakout:the_read_signal_breakout" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/descriptor_buffers.v Line: 277
Info (12128): Elaborating entity "fifo_with_byteenables" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/descriptor_buffers.v Line: 296
Info (10264): Verilog HDL Case Statement information at fifo_with_byteenables.v(168): all case item expressions in this case statement are onehot File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/fifo_with_byteenables.v Line: 168
Info (12128): Elaborating entity "altsyncram" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/fifo_with_byteenables.v Line: 136
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/fifo_with_byteenables.v Line: 136
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/fifo_with_byteenables.v Line: 136
    Info (12134): Parameter "operation_mode" = "DUAL_PORT"
    Info (12134): Parameter "lpm_type" = "altsyncram"
    Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info (12134): Parameter "power_up_uninitialized" = "TRUE"
    Info (12134): Parameter "byte_size" = "8"
    Info (12134): Parameter "width_a" = "128"
    Info (12134): Parameter "width_b" = "128"
    Info (12134): Parameter "widthad_a" = "4"
    Info (12134): Parameter "widthad_b" = "4"
    Info (12134): Parameter "width_byteena_a" = "16"
    Info (12134): Parameter "numwords_a" = "16"
    Info (12134): Parameter "numwords_b" = "16"
    Info (12134): Parameter "address_reg_b" = "CLOCK0"
    Info (12134): Parameter "outdata_reg_b" = "CLOCK0"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_p5j1.tdf
    Info (12023): Found entity 1: altsyncram_p5j1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_p5j1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
Info (12128): Elaborating entity "csr_block" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|csr_block:the_csr_block" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/dispatcher.v Line: 351
Info (12128): Elaborating entity "response_block" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/dispatcher.v Line: 379
Info (12128): Elaborating entity "scfifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/response_block.v Line: 149
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/response_block.v Line: 149
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/response_block.v Line: 149
    Info (12134): Parameter "lpm_width" = "41"
    Info (12134): Parameter "lpm_numwords" = "32"
    Info (12134): Parameter "lpm_widthu" = "5"
    Info (12134): Parameter "lpm_showahead" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "overflow_checking" = "OFF"
    Info (12134): Parameter "underflow_checking" = "OFF"
    Info (12134): Parameter "add_ram_output_register" = "ON"
    Info (12134): Parameter "lpm_type" = "scfifo"
Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_o871.tdf
    Info (12023): Found entity 1: scfifo_o871 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/scfifo_o871.tdf Line: 24
Info (12128): Elaborating entity "scfifo_o871" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/scfifo.tdf Line: 299
Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_b071.tdf
    Info (12023): Found entity 1: a_dpfifo_b071 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_b071.tdf Line: 32
Info (12128): Elaborating entity "a_dpfifo_b071" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated|a_dpfifo_b071:dpfifo" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/scfifo_o871.tdf Line: 38
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_rgn1.tdf
    Info (12023): Found entity 1: altsyncram_rgn1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_rgn1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_rgn1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated|a_dpfifo_b071:dpfifo|altsyncram_rgn1:FIFOram" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_b071.tdf Line: 46
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_4l8.tdf
    Info (12023): Found entity 1: cmpr_4l8 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cmpr_4l8.tdf Line: 22
Info (12128): Elaborating entity "cmpr_4l8" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated|a_dpfifo_b071:dpfifo|cmpr_4l8:almost_full_comparer" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_b071.tdf Line: 55
Info (12128): Elaborating entity "cmpr_4l8" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated|a_dpfifo_b071:dpfifo|cmpr_4l8:three_comparison" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_b071.tdf Line: 56
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_hgb.tdf
    Info (12023): Found entity 1: cntr_hgb File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cntr_hgb.tdf Line: 25
Info (12128): Elaborating entity "cntr_hgb" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated|a_dpfifo_b071:dpfifo|cntr_hgb:rd_ptr_msb" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_b071.tdf Line: 57
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_ug7.tdf
    Info (12023): Found entity 1: cntr_ug7 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cntr_ug7.tdf Line: 25
Info (12128): Elaborating entity "cntr_ug7" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated|a_dpfifo_b071:dpfifo|cntr_ug7:usedw_counter" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_b071.tdf Line: 58
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_igb.tdf
    Info (12023): Found entity 1: cntr_igb File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cntr_igb.tdf Line: 25
Info (12128): Elaborating entity "cntr_igb" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block|scfifo:the_response_FIFO|scfifo_o871:auto_generated|a_dpfifo_b071:dpfifo|cntr_igb:wr_ptr" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_b071.tdf Line: 59
Info (12128): Elaborating entity "write_master" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_rx_msgdma.v Line: 143
Info (10264): Verilog HDL Case Statement information at write_master.v(757): all case item expressions in this case statement are onehot File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_master.v Line: 757
Info (12128): Elaborating entity "scfifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_master.v Line: 588
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_master.v Line: 588
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_master.v Line: 588
    Info (12134): Parameter "lpm_width" = "42"
    Info (12134): Parameter "lpm_widthu" = "5"
    Info (12134): Parameter "lpm_numwords" = "32"
    Info (12134): Parameter "lpm_showahead" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "add_ram_output_register" = "ON"
    Info (12134): Parameter "underflow_checking" = "OFF"
    Info (12134): Parameter "overflow_checking" = "OFF"
Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_p871.tdf
    Info (12023): Found entity 1: scfifo_p871 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/scfifo_p871.tdf Line: 24
Info (12128): Elaborating entity "scfifo_p871" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo|scfifo_p871:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/scfifo.tdf Line: 299
Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_c071.tdf
    Info (12023): Found entity 1: a_dpfifo_c071 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_c071.tdf Line: 32
Info (12128): Elaborating entity "a_dpfifo_c071" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo|scfifo_p871:auto_generated|a_dpfifo_c071:dpfifo" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/scfifo_p871.tdf Line: 38
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_tgn1.tdf
    Info (12023): Found entity 1: altsyncram_tgn1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_tgn1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_tgn1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo|scfifo_p871:auto_generated|a_dpfifo_c071:dpfifo|altsyncram_tgn1:FIFOram" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_c071.tdf Line: 46
Info (12128): Elaborating entity "ST_to_MM_Adapter" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|ST_to_MM_Adapter:the_ST_to_MM_Adapter" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_master.v Line: 616
Info (12128): Elaborating entity "byte_enable_generator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|byte_enable_generator:the_byte_enable_generator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_master.v Line: 633
Info (12128): Elaborating entity "thirty_two_bit_byteenable_FSM" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|byte_enable_generator:the_byte_enable_generator|thirty_two_bit_byteenable_FSM:the_thirty_two_bit_byteenable_FSM" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/byte_enable_generator.v Line: 107
Info (12128): Elaborating entity "sixteen_bit_byteenable_FSM" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|byte_enable_generator:the_byte_enable_generator|thirty_two_bit_byteenable_FSM:the_thirty_two_bit_byteenable_FSM|sixteen_bit_byteenable_FSM:lower_sixteen_bit_byteenable_FSM" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/byte_enable_generator.v Line: 797
Info (12128): Elaborating entity "write_burst_control" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|write_burst_control:the_write_burst_control" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_master.v Line: 664
Info (10264): Verilog HDL Case Statement information at write_burst_control.v(268): all case item expressions in this case statement are onehot File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/write_burst_control.v Line: 268
Info (12128): Elaborating entity "nios2_enet_tx_msgdma" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 378
Info (12128): Elaborating entity "dispatcher" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_tx_msgdma.v Line: 90
Info (12128): Elaborating entity "descriptor_buffers" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/dispatcher.v Line: 306
Info (12128): Elaborating entity "response_block" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|response_block:the_response_block" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/dispatcher.v Line: 379
Info (12128): Elaborating entity "read_master" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_tx_msgdma.v Line: 142
Info (10264): Verilog HDL Case Statement information at read_master.v(719): all case item expressions in this case statement are onehot File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_master.v Line: 719
Info (12128): Elaborating entity "MM_to_ST_Adapter" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|MM_to_ST_Adapter:the_MM_to_ST_adapter" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_master.v Line: 548
Info (12128): Elaborating entity "scfifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_master.v Line: 572
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_master.v Line: 572
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_master.v Line: 572
    Info (12134): Parameter "lpm_width" = "45"
    Info (12134): Parameter "lpm_numwords" = "32"
    Info (12134): Parameter "lpm_widthu" = "5"
    Info (12134): Parameter "lpm_showahead" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "add_ram_output_register" = "ON"
    Info (12134): Parameter "underflow_checking" = "OFF"
    Info (12134): Parameter "overflow_checking" = "OFF"
Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_s871.tdf
    Info (12023): Found entity 1: scfifo_s871 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/scfifo_s871.tdf Line: 24
Info (12128): Elaborating entity "scfifo_s871" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/scfifo.tdf Line: 299
Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_f071.tdf
    Info (12023): Found entity 1: a_dpfifo_f071 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_f071.tdf Line: 32
Info (12128): Elaborating entity "a_dpfifo_f071" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/scfifo_s871.tdf Line: 38
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_3hn1.tdf
    Info (12023): Found entity 1: altsyncram_3hn1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_3hn1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_3hn1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo|altsyncram_3hn1:FIFOram" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_f071.tdf Line: 46
Info (12128): Elaborating entity "read_burst_control" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|read_burst_control:the_read_burst_control" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/read_master.v Line: 592
Info (12128): Elaborating entity "nios2_enet_udp_dpram" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 399
Info (12128): Elaborating entity "altsyncram" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram|altsyncram:the_altsyncram" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_udp_dpram.v Line: 94
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram|altsyncram:the_altsyncram" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_udp_dpram.v Line: 94
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram|altsyncram:the_altsyncram" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_enet_udp_dpram.v Line: 94
    Info (12134): Parameter "address_reg_b" = "CLOCK0"
    Info (12134): Parameter "byte_size" = "8"
    Info (12134): Parameter "byteena_reg_b" = "CLOCK0"
    Info (12134): Parameter "indata_reg_b" = "CLOCK0"
    Info (12134): Parameter "init_file" = "UNUSED"
    Info (12134): Parameter "lpm_type" = "altsyncram"
    Info (12134): Parameter "maximum_depth" = "1024"
    Info (12134): Parameter "numwords_a" = "1024"
    Info (12134): Parameter "numwords_b" = "1024"
    Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT"
    Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED"
    Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED"
    Info (12134): Parameter "ram_block_type" = "AUTO"
    Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info (12134): Parameter "width_a" = "32"
    Info (12134): Parameter "width_b" = "32"
    Info (12134): Parameter "width_byteena_a" = "4"
    Info (12134): Parameter "width_byteena_b" = "4"
    Info (12134): Parameter "widthad_a" = "10"
    Info (12134): Parameter "widthad_b" = "10"
    Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_dc72.tdf
    Info (12023): Found entity 1: altsyncram_dc72 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_dc72.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_dc72" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_udp_dpram:enet_udp_dpram|altsyncram:the_altsyncram|altsyncram_dc72:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
Info (12128): Elaborating entity "nios2_eth_tse_mac" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 450
Info (12128): Elaborating entity "altera_eth_tse_mac" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_eth_tse_mac.v Line: 183
Info (12128): Elaborating entity "altera_tse_reset_synchronizer" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_0" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_mac.v Line: 541
Info (12128): Elaborating entity "altera_tse_mac_control" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_mac.v Line: 772
Info (12128): Elaborating entity "altera_tse_register_map" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_control.v Line: 630
Info (12128): Elaborating entity "altera_eth_tse_std_synchronizer" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_SYNC_1" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_register_map.v Line: 446
Info (12128): Elaborating entity "altera_std_synchronizer_nocut" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_eth_tse_std_synchronizer:U_SYNC_1|altera_std_synchronizer_nocut:std_sync_no_cut" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_std_synchronizer.v Line: 62
Info (12128): Elaborating entity "altera_tse_clock_crosser" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_tse_clock_crosser:U_EXCESS_COL" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_register_map.v Line: 509
Info (12128): Elaborating entity "altera_tse_host_control" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_control.v Line: 672
Info (12128): Elaborating entity "altera_tse_top_mdio" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_mac.v Line: 812
Info (12128): Elaborating entity "altera_tse_mdio_clk_gen" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_clk_gen:U_CLKGEN" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_mdio.v Line: 105
Info (12128): Elaborating entity "altera_tse_mdio_cntl" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_cntl:U_CNTL" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_mdio.v Line: 130
Info (12128): Elaborating entity "altera_tse_mdio" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio:U_MDIO" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_mdio.v Line: 147
Info (12128): Elaborating entity "altera_tse_rgmii_module" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_mac.v Line: 941
Info (12128): Elaborating entity "altera_tse_rgmii_in4" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in4:the_rgmii_in4" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_module.v Line: 151
Info (12128): Elaborating entity "altddio_in" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in4:the_rgmii_in4|altddio_in:altddio_in_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_in4.v Line: 74
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in4:the_rgmii_in4|altddio_in:altddio_in_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_in4.v Line: 74
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in4:the_rgmii_in4|altddio_in:altddio_in_component" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_in4.v Line: 74
    Info (12134): Parameter "intended_device_family" = "Stratix II"
    Info (12134): Parameter "invert_input_clocks" = "OFF"
    Info (12134): Parameter "lpm_type" = "altddio_in"
    Info (12134): Parameter "width" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/ddio_in_jsd.tdf
    Info (12023): Found entity 1: ddio_in_jsd File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ddio_in_jsd.tdf Line: 27
Info (12128): Elaborating entity "ddio_in_jsd" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in4:the_rgmii_in4|altddio_in:altddio_in_component|ddio_in_jsd:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altddio_in.tdf Line: 84
Info (12128): Elaborating entity "altera_tse_rgmii_in1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in1:the_rgmii_in1" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_module.v Line: 161
Info (12128): Elaborating entity "altddio_in" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in1:the_rgmii_in1|altddio_in:altddio_in_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_in1.v Line: 78
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in1:the_rgmii_in1|altddio_in:altddio_in_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_in1.v Line: 78
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in1:the_rgmii_in1|altddio_in:altddio_in_component" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_in1.v Line: 78
    Info (12134): Parameter "intended_device_family" = "Stratix II"
    Info (12134): Parameter "invert_input_clocks" = "OFF"
    Info (12134): Parameter "lpm_type" = "altddio_in"
    Info (12134): Parameter "width" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/ddio_in_gsd.tdf
    Info (12023): Found entity 1: ddio_in_gsd File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ddio_in_gsd.tdf Line: 27
Info (12128): Elaborating entity "ddio_in_gsd" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in1:the_rgmii_in1|altddio_in:altddio_in_component|ddio_in_gsd:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altddio_in.tdf Line: 84
Info (12128): Elaborating entity "altera_tse_rgmii_out4" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_out4:the_rgmii_out4" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_module.v Line: 285
Info (12128): Elaborating entity "altddio_out" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_out4:the_rgmii_out4|altddio_out:altddio_out_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_out4.v Line: 73
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_out4:the_rgmii_out4|altddio_out:altddio_out_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_out4.v Line: 73
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_out4:the_rgmii_out4|altddio_out:altddio_out_component" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_out4.v Line: 73
    Info (12134): Parameter "extend_oe_disable" = "UNUSED"
    Info (12134): Parameter "intended_device_family" = "Stratix II"
    Info (12134): Parameter "lpm_type" = "altddio_out"
    Info (12134): Parameter "oe_reg" = "UNUSED"
    Info (12134): Parameter "width" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/ddio_out_jhb.tdf
    Info (12023): Found entity 1: ddio_out_jhb File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ddio_out_jhb.tdf Line: 27
Info (12128): Elaborating entity "ddio_out_jhb" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_out4:the_rgmii_out4|altddio_out:altddio_out_component|ddio_out_jhb:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altddio_out.tdf Line: 100
Info (12128): Elaborating entity "altera_tse_rgmii_out1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_out1:the_rgmii_out1" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_module.v Line: 297
Info (12128): Elaborating entity "altddio_out" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_out1:the_rgmii_out1|altddio_out:altddio_out_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_out1.v Line: 78
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_out1:the_rgmii_out1|altddio_out:altddio_out_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_out1.v Line: 78
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_out1:the_rgmii_out1|altddio_out:altddio_out_component" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rgmii_out1.v Line: 78
    Info (12134): Parameter "extend_oe_disable" = "UNUSED"
    Info (12134): Parameter "intended_device_family" = "Stratix II"
    Info (12134): Parameter "lpm_type" = "altddio_out"
    Info (12134): Parameter "oe_reg" = "UNUSED"
    Info (12134): Parameter "width" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/ddio_out_ghb.tdf
    Info (12023): Found entity 1: ddio_out_ghb File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ddio_out_ghb.tdf Line: 27
Info (12128): Elaborating entity "ddio_out_ghb" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_out1:the_rgmii_out1|altddio_out:altddio_out_component|ddio_out_ghb:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altddio_out.tdf Line: 100
Info (12128): Elaborating entity "altera_tse_top_w_fifo_10_100_1000" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_mac.v Line: 1091
Info (12128): Elaborating entity "altera_tse_clk_cntl" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v Line: 487
Info (12128): Elaborating entity "altera_tse_mii_rx_if" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_rx_if:U_MRX" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v Line: 503
Info (12128): Elaborating entity "altera_tse_mii_tx_if" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_tx_if:U_MTX" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v Line: 516
Info (12128): Elaborating entity "altera_tse_gmii_io" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_gmii_io:U_GMIF" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v Line: 560
Info (12128): Elaborating entity "altera_tse_loopback_ff" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v Line: 668
Info (12128): Elaborating entity "altera_tse_lb_wrt_cntl" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_wrt_cntl:U_LBW" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_loopback_ff.v Line: 114
Info (12128): Elaborating entity "altera_tse_a_fifo_24" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_loopback_ff.v Line: 187
Info (12128): Elaborating entity "altera_tse_sdpm_altsyncram" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_sdpm_altsyncram:U_RAM" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_24.v Line: 132
Info (12128): Elaborating entity "altsyncram" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_sdpm_altsyncram:U_RAM|altsyncram:altsyncram_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_sdpm_altsyncram.v Line: 93
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_sdpm_altsyncram:U_RAM|altsyncram:altsyncram_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_sdpm_altsyncram.v Line: 93
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_sdpm_altsyncram:U_RAM|altsyncram:altsyncram_component" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_sdpm_altsyncram.v Line: 93
    Info (12134): Parameter "enable_ecc" = "FALSE"
    Info (12134): Parameter "address_reg_b" = "CLOCK1"
    Info (12134): Parameter "lpm_type" = "altsyncram"
    Info (12134): Parameter "numwords_a" = "32"
    Info (12134): Parameter "numwords_b" = "32"
    Info (12134): Parameter "operation_mode" = "DUAL_PORT"
    Info (12134): Parameter "outdata_aclr_b" = "NONE"
    Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED"
    Info (12134): Parameter "power_up_uninitialized" = "FALSE"
    Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info (12134): Parameter "widthad_a" = "5"
    Info (12134): Parameter "widthad_b" = "5"
    Info (12134): Parameter "width_a" = "10"
    Info (12134): Parameter "width_b" = "10"
    Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_2vl1.tdf
    Info (12023): Found entity 1: altsyncram_2vl1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_2vl1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_2vl1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_sdpm_altsyncram:U_RAM|altsyncram:altsyncram_component|altsyncram_2vl1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
Info (12128): Elaborating entity "altera_tse_gray_cnt" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_24.v Line: 142
Info (12128): Elaborating entity "altera_eth_tse_std_synchronizer_bundle" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_24.v Line: 157
Info (12128): Elaborating entity "altera_eth_tse_std_synchronizer" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[0].u" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_std_synchronizer_bundle.v Line: 55
Info (12128): Elaborating entity "altera_std_synchronizer_nocut" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:sync[0].u|altera_std_synchronizer_nocut:std_sync_no_cut" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_eth_tse_std_synchronizer.v Line: 62
Info (12128): Elaborating entity "altera_tse_lb_read_cntl" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_loopback_ff:U_LBFF|altera_tse_lb_read_cntl:U_LBR" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_loopback_ff.v Line: 212
Info (12128): Elaborating entity "altera_tse_top_w_fifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v Line: 820
Info (12128): Elaborating entity "altera_tse_top_1geth" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo.v Line: 543
Info (12128): Elaborating entity "altera_tse_rx_stat_extract" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_1geth.v Line: 397
Info (12128): Elaborating entity "altera_tse_mac_rx" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_1geth.v Line: 468
Info (12128): Elaborating entity "altera_tse_crc328checker" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_crc328checker:U_CRC" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_rx.v Line: 2758
Info (12128): Elaborating entity "altera_tse_crc32galois8" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_crc328checker:U_CRC|altera_tse_crc32galois8:U_GALS" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc328checker.v Line: 110
Info (12128): Elaborating entity "altera_tse_altshifttaps" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_altshifttaps:U_SHIFTTAPS" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_rx.v Line: 3207
Info (12128): Elaborating entity "altera_tse_tx_stat_extract" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_tx_stat_extract:U_TXSTAT" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_1geth.v Line: 501
Info (12128): Elaborating entity "altera_tse_mac_tx" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_1geth.v Line: 550
Info (12128): Elaborating entity "altera_eth_tse_std_synchronizer_bundle" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_tx.v Line: 420
Info (12128): Elaborating entity "altera_tse_crc328generator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_mac_tx.v Line: 2332
Info (12128): Elaborating entity "altera_tse_crc32ctl8" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|altera_tse_crc32ctl8:U_CTL" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_crc328generator.v Line: 104
Info (12128): Elaborating entity "altera_tse_rx_min_ff" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo.v Line: 643
Info (12128): Elaborating entity "altera_eth_tse_std_synchronizer_bundle" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_min_ff.v Line: 294
Info (12128): Elaborating entity "altera_tse_a_fifo_opt_1246" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_min_ff.v Line: 556
Info (12128): Elaborating entity "altera_tse_altsyncram_dpm_fifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_opt_1246.v Line: 175
Info (12128): Elaborating entity "altsyncram" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v Line: 94
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v Line: 94
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v Line: 94
    Info (12134): Parameter "enable_ecc" = "FALSE"
    Info (12134): Parameter "address_reg_b" = "CLOCK1"
    Info (12134): Parameter "lpm_type" = "altsyncram"
    Info (12134): Parameter "numwords_a" = "4096"
    Info (12134): Parameter "numwords_b" = "4096"
    Info (12134): Parameter "operation_mode" = "DUAL_PORT"
    Info (12134): Parameter "outdata_aclr_b" = "NONE"
    Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED"
    Info (12134): Parameter "power_up_uninitialized" = "FALSE"
    Info (12134): Parameter "ram_block_type" = "AUTO"
    Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info (12134): Parameter "widthad_a" = "12"
    Info (12134): Parameter "widthad_b" = "12"
    Info (12134): Parameter "width_a" = "40"
    Info (12134): Parameter "width_b" = "40"
    Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_5ao1.tdf
    Info (12023): Found entity 1: altsyncram_5ao1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_5ao1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_5ao1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_5ao1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
Info (12128): Elaborating entity "altera_tse_gray_cnt" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_opt_1246.v Line: 184
Info (12128): Elaborating entity "altera_tse_a_fifo_34" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_rx_min_ff.v Line: 1123
Info (12128): Elaborating entity "altera_tse_altsyncram_dpm_fifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_34.v Line: 112
Info (12128): Elaborating entity "altsyncram" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v Line: 94
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v Line: 94
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v Line: 94
    Info (12134): Parameter "enable_ecc" = "FALSE"
    Info (12134): Parameter "address_reg_b" = "CLOCK1"
    Info (12134): Parameter "lpm_type" = "altsyncram"
    Info (12134): Parameter "numwords_a" = "1024"
    Info (12134): Parameter "numwords_b" = "1024"
    Info (12134): Parameter "operation_mode" = "DUAL_PORT"
    Info (12134): Parameter "outdata_aclr_b" = "NONE"
    Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED"
    Info (12134): Parameter "power_up_uninitialized" = "FALSE"
    Info (12134): Parameter "ram_block_type" = "AUTO"
    Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info (12134): Parameter "widthad_a" = "10"
    Info (12134): Parameter "widthad_b" = "10"
    Info (12134): Parameter "width_a" = "23"
    Info (12134): Parameter "width_b" = "23"
    Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_b9o1.tdf
    Info (12023): Found entity 1: altsyncram_b9o1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_b9o1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
Info (12128): Elaborating entity "altera_tse_gray_cnt" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_34.v Line: 121
Info (12128): Elaborating entity "altera_tse_bin_cnt" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_bin_cnt:U_RD" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_34.v Line: 129
Info (12128): Elaborating entity "altera_eth_tse_std_synchronizer_bundle" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_34.v Line: 149
Info (12128): Elaborating entity "altera_tse_tx_min_ff" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_top_w_fifo.v Line: 695
Info (12128): Elaborating entity "altera_eth_tse_std_synchronizer_bundle" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_min_ff.v Line: 234
Info (12128): Elaborating entity "altera_tse_altsyncram_dpm_fifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_min_ff.v Line: 300
Info (12128): Elaborating entity "altsyncram" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram:altsyncram_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v Line: 94
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram:altsyncram_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v Line: 94
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram:altsyncram_component" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v Line: 94
    Info (12134): Parameter "enable_ecc" = "FALSE"
    Info (12134): Parameter "address_reg_b" = "CLOCK1"
    Info (12134): Parameter "lpm_type" = "altsyncram"
    Info (12134): Parameter "numwords_a" = "128"
    Info (12134): Parameter "numwords_b" = "128"
    Info (12134): Parameter "operation_mode" = "DUAL_PORT"
    Info (12134): Parameter "outdata_aclr_b" = "NONE"
    Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED"
    Info (12134): Parameter "power_up_uninitialized" = "FALSE"
    Info (12134): Parameter "ram_block_type" = "AUTO"
    Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info (12134): Parameter "widthad_a" = "7"
    Info (12134): Parameter "widthad_b" = "7"
    Info (12134): Parameter "width_a" = "10"
    Info (12134): Parameter "width_b" = "10"
    Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_n3o1.tdf
    Info (12023): Found entity 1: altsyncram_n3o1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_n3o1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_n3o1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram:altsyncram_component|altsyncram_n3o1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
Info (12128): Elaborating entity "altera_tse_a_fifo_opt_1246" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_min_ff.v Line: 680
Info (12128): Elaborating entity "altera_tse_altsyncram_dpm_fifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_opt_1246.v Line: 175
Info (12128): Elaborating entity "altsyncram" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v Line: 94
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v Line: 94
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v Line: 94
    Info (12134): Parameter "enable_ecc" = "FALSE"
    Info (12134): Parameter "address_reg_b" = "CLOCK1"
    Info (12134): Parameter "lpm_type" = "altsyncram"
    Info (12134): Parameter "numwords_a" = "2048"
    Info (12134): Parameter "numwords_b" = "2048"
    Info (12134): Parameter "operation_mode" = "DUAL_PORT"
    Info (12134): Parameter "outdata_aclr_b" = "NONE"
    Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED"
    Info (12134): Parameter "power_up_uninitialized" = "FALSE"
    Info (12134): Parameter "ram_block_type" = "AUTO"
    Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info (12134): Parameter "widthad_a" = "11"
    Info (12134): Parameter "widthad_b" = "11"
    Info (12134): Parameter "width_a" = "36"
    Info (12134): Parameter "width_b" = "36"
    Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_3ao1.tdf
    Info (12023): Found entity 1: altsyncram_3ao1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_3ao1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_3ao1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_3ao1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
Info (12128): Elaborating entity "altera_tse_gray_cnt" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_opt_1246.v Line: 184
Info (12128): Elaborating entity "altera_tse_a_fifo_13" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_tx_min_ff.v Line: 701
Info (12128): Elaborating entity "altera_tse_altsyncram_dpm_fifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_13.v Line: 119
Info (12128): Elaborating entity "altsyncram" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v Line: 94
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v Line: 94
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_altsyncram_dpm_fifo.v Line: 94
    Info (12134): Parameter "enable_ecc" = "FALSE"
    Info (12134): Parameter "address_reg_b" = "CLOCK1"
    Info (12134): Parameter "lpm_type" = "altsyncram"
    Info (12134): Parameter "numwords_a" = "512"
    Info (12134): Parameter "numwords_b" = "512"
    Info (12134): Parameter "operation_mode" = "DUAL_PORT"
    Info (12134): Parameter "outdata_aclr_b" = "NONE"
    Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED"
    Info (12134): Parameter "power_up_uninitialized" = "FALSE"
    Info (12134): Parameter "ram_block_type" = "AUTO"
    Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info (12134): Parameter "widthad_a" = "9"
    Info (12134): Parameter "widthad_b" = "9"
    Info (12134): Parameter "width_a" = "2"
    Info (12134): Parameter "width_b" = "2"
    Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_n0o1.tdf
    Info (12023): Found entity 1: altsyncram_n0o1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_n0o1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_n0o1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_n0o1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
Info (12128): Elaborating entity "altera_tse_gray_cnt" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_13.v Line: 128
Info (12128): Elaborating entity "altera_eth_tse_std_synchronizer_bundle" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_tse_a_fifo_13.v Line: 146
Info (12128): Elaborating entity "nios2_fabric_if" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 480
Info (12128): Elaborating entity "nios2_fabric_if_daq_dest_ip_addr" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_daq_dest_ip_addr:daq_dest_ip_addr" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if.v Line: 142
Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_avalon_mm_bridge:if_bridge" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if.v Line: 198
Info (12128): Elaborating entity "nios2_fabric_if_own_ip_addr_in" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_own_ip_addr_in:own_ip_addr_in" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if.v Line: 217
Info (12128): Elaborating entity "nios2_fabric_if_rot_switch" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_rot_switch:rot_switch" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if.v Line: 263
Info (12128): Elaborating entity "nios2_fabric_if_mm_interconnect_0" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if.v Line: 374
Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:if_bridge_m0_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v Line: 1041
Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:own_mac_addr_l_s1_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v Line: 1105
Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:if_bridge_m0_agent" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v Line: 2082
Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_s1_agent" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v Line: 2166
Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:own_mac_addr_l_s1_agent|altera_merlin_burst_uncompressor:uncompressor" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608
Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:own_mac_addr_l_s1_agent_rsp_fifo" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v Line: 2207
Info (12128): Elaborating entity "nios2_fabric_if_mm_interconnect_0_router" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router:router" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v Line: 3973
Info (12128): Elaborating entity "nios2_fabric_if_mm_interconnect_0_router_default_decode" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router:router|nios2_fabric_if_mm_interconnect_0_router_default_decode:the_default_decode" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_router.sv Line: 198
Info (12128): Elaborating entity "nios2_fabric_if_mm_interconnect_0_router_001" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_001" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v Line: 3989
Info (12128): Elaborating entity "nios2_fabric_if_mm_interconnect_0_router_001_default_decode" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_router_001:router_001|nios2_fabric_if_mm_interconnect_0_router_001_default_decode:the_default_decode" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_router_001.sv Line: 173
Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:if_bridge_m0_limiter" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v Line: 4263
Info (12128): Elaborating entity "nios2_fabric_if_mm_interconnect_0_cmd_demux" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_demux:cmd_demux" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v Line: 4364
Info (12128): Elaborating entity "nios2_fabric_if_mm_interconnect_0_cmd_mux" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_cmd_mux:cmd_mux" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v Line: 4381
Info (12128): Elaborating entity "nios2_fabric_if_mm_interconnect_0_rsp_demux" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_demux:rsp_demux" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v Line: 4636
Info (12128): Elaborating entity "nios2_fabric_if_mm_interconnect_0_rsp_mux" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_mux:rsp_mux" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v Line: 4975
Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0_rsp_mux.sv Line: 518
Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_fabric_if_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169
Info (12128): Elaborating entity "nios2_mm_interconnect_0_avalon_st_adapter" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if_mm_interconnect_0.v Line: 5004
Info (12128): Elaborating entity "nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|nios2_fabric_if_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter|nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter.v Line: 200
Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_fabric_if.v Line: 437
Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_reset_controller.v Line: 208
Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_fabric_if:fabric_if|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_reset_controller.v Line: 220
Info (12128): Elaborating entity "nios2_jtag_uart_0" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 493
Info (12128): Elaborating entity "nios2_jtag_uart_0_scfifo_w" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_jtag_uart_0.v Line: 420
Info (12128): Elaborating entity "scfifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_jtag_uart_0.v Line: 139
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_jtag_uart_0.v Line: 139
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_jtag_uart_0.v Line: 139
    Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=AUTO"
    Info (12134): Parameter "lpm_numwords" = "64"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "scfifo"
    Info (12134): Parameter "lpm_width" = "8"
    Info (12134): Parameter "lpm_widthu" = "6"
    Info (12134): Parameter "overflow_checking" = "OFF"
    Info (12134): Parameter "underflow_checking" = "OFF"
    Info (12134): Parameter "use_eab" = "ON"
Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_3291.tdf
    Info (12023): Found entity 1: scfifo_3291 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/scfifo_3291.tdf Line: 24
Info (12128): Elaborating entity "scfifo_3291" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_3291:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/scfifo.tdf Line: 299
Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_5771.tdf
    Info (12023): Found entity 1: a_dpfifo_5771 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_5771.tdf Line: 28
Info (12128): Elaborating entity "a_dpfifo_5771" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/scfifo_3291.tdf Line: 37
Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf
    Info (12023): Found entity 1: a_fefifo_7cf File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_fefifo_7cf.tdf Line: 24
Info (12128): Elaborating entity "a_fefifo_7cf" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|a_fefifo_7cf:fifo_state" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_5771.tdf Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_vg7.tdf
    Info (12023): Found entity 1: cntr_vg7 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cntr_vg7.tdf Line: 25
Info (12128): Elaborating entity "cntr_vg7" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|a_fefifo_7cf:fifo_state|cntr_vg7:count_usedw" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_fefifo_7cf.tdf Line: 38
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_7pu1.tdf
    Info (12023): Found entity 1: altsyncram_7pu1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_7pu1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_7pu1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|altsyncram_7pu1:FIFOram" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_5771.tdf Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_jgb.tdf
    Info (12023): Found entity 1: cntr_jgb File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cntr_jgb.tdf Line: 25
Info (12128): Elaborating entity "cntr_jgb" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_w:the_nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_3291:auto_generated|a_dpfifo_5771:dpfifo|cntr_jgb:rd_ptr_count" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_5771.tdf Line: 44
Info (12128): Elaborating entity "nios2_jtag_uart_0_scfifo_r" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|nios2_jtag_uart_0_scfifo_r:the_nios2_jtag_uart_0_scfifo_r" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_jtag_uart_0.v Line: 434
Info (12128): Elaborating entity "alt_jtag_atlantic" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_jtag_uart_0.v Line: 569
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_jtag_uart_0.v Line: 569
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_jtag_uart_0.v Line: 569
    Info (12134): Parameter "INSTANCE_ID" = "0"
    Info (12134): Parameter "LOG2_RXFIFO_DEPTH" = "6"
    Info (12134): Parameter "LOG2_TXFIFO_DEPTH" = "6"
    Info (12134): Parameter "SLD_AUTO_INSTANCE_INDEX" = "YES"
Info (12128): Elaborating entity "sld_jtag_endpoint_adapter" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|sld_jtag_endpoint_adapter:inst" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/alt_jtag_atlantic.v Line: 276
Info (12128): Elaborating entity "sld_jtag_endpoint_adapter_impl" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:nios2_jtag_uart_0_alt_jtag_atlantic|sld_jtag_endpoint_adapter:inst|sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd Line: 232
Info (12128): Elaborating entity "nios2_nios2" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 522
Info (12128): Elaborating entity "nios2_nios2_cpu" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2.v Line: 65
Info (12128): Elaborating entity "nios2_nios2_cpu_test_bench" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_test_bench:the_nios2_nios2_cpu_test_bench" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 3545
Info (12128): Elaborating entity "nios2_nios2_cpu_register_bank_a_module" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 4061
Info (12128): Elaborating entity "altsyncram" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a|altsyncram:the_altsyncram" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 58
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a|altsyncram:the_altsyncram" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 58
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a|altsyncram:the_altsyncram" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 58
    Info (12134): Parameter "address_reg_b" = "CLOCK0"
    Info (12134): Parameter "init_file" = "UNUSED"
    Info (12134): Parameter "maximum_depth" = "0"
    Info (12134): Parameter "numwords_a" = "32"
    Info (12134): Parameter "numwords_b" = "32"
    Info (12134): Parameter "operation_mode" = "DUAL_PORT"
    Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED"
    Info (12134): Parameter "ram_block_type" = "AUTO"
    Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0"
    Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info (12134): Parameter "width_a" = "32"
    Info (12134): Parameter "width_b" = "32"
    Info (12134): Parameter "widthad_a" = "5"
    Info (12134): Parameter "widthad_b" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_msi1.tdf
    Info (12023): Found entity 1: altsyncram_msi1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_msi1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_msi1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_a_module:nios2_nios2_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_msi1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
Info (12128): Elaborating entity "nios2_nios2_cpu_register_bank_b_module" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_register_bank_b_module:nios2_nios2_cpu_register_bank_b" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 4079
Info (12128): Elaborating entity "nios2_nios2_cpu_nios2_oci" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 4575
Info (12128): Elaborating entity "nios2_nios2_cpu_nios2_oci_debug" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_debug:the_nios2_nios2_cpu_nios2_oci_debug" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2531
Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_debug:the_nios2_nios2_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 220
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_debug:the_nios2_nios2_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 220
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_debug:the_nios2_nios2_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 220
    Info (12134): Parameter "depth" = "2"
Info (12128): Elaborating entity "nios2_nios2_cpu_nios2_oci_break" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_break:the_nios2_nios2_cpu_nios2_oci_break" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2561
Info (12128): Elaborating entity "nios2_nios2_cpu_nios2_oci_xbrk" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_xbrk:the_nios2_nios2_cpu_nios2_oci_xbrk" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2582
Info (12128): Elaborating entity "nios2_nios2_cpu_nios2_oci_dbrk" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_dbrk:the_nios2_nios2_cpu_nios2_oci_dbrk" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2608
Info (12128): Elaborating entity "nios2_nios2_cpu_nios2_oci_itrace" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_itrace:the_nios2_nios2_cpu_nios2_oci_itrace" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2624
Info (12128): Elaborating entity "nios2_nios2_cpu_nios2_oci_dtrace" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_dtrace:the_nios2_nios2_cpu_nios2_oci_dtrace" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2639
Info (12128): Elaborating entity "nios2_nios2_cpu_nios2_oci_td_mode" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_dtrace:the_nios2_nios2_cpu_nios2_oci_dtrace|nios2_nios2_cpu_nios2_oci_td_mode:nios2_nios2_cpu_nios2_oci_trc_ctrl_td_mode" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 1233
Info (12128): Elaborating entity "nios2_nios2_cpu_nios2_oci_fifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_fifo:the_nios2_nios2_cpu_nios2_oci_fifo" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2654
Info (12128): Elaborating entity "nios2_nios2_cpu_nios2_oci_compute_input_tm_cnt" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_fifo:the_nios2_nios2_cpu_nios2_oci_fifo|nios2_nios2_cpu_nios2_oci_compute_input_tm_cnt:the_nios2_nios2_cpu_nios2_oci_compute_input_tm_cnt" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 1546
Info (12128): Elaborating entity "nios2_nios2_cpu_nios2_oci_fifo_wrptr_inc" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_fifo:the_nios2_nios2_cpu_nios2_oci_fifo|nios2_nios2_cpu_nios2_oci_fifo_wrptr_inc:the_nios2_nios2_cpu_nios2_oci_fifo_wrptr_inc" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 1555
Info (12128): Elaborating entity "nios2_nios2_cpu_nios2_oci_fifo_cnt_inc" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_fifo:the_nios2_nios2_cpu_nios2_oci_fifo|nios2_nios2_cpu_nios2_oci_fifo_cnt_inc:the_nios2_nios2_cpu_nios2_oci_fifo_cnt_inc" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 1564
Info (12128): Elaborating entity "nios2_nios2_cpu_nios2_oci_pib" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_pib:the_nios2_nios2_cpu_nios2_oci_pib" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2659
Info (12128): Elaborating entity "nios2_nios2_cpu_nios2_oci_im" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_oci_im:the_nios2_nios2_cpu_nios2_oci_im" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2673
Info (12128): Elaborating entity "nios2_nios2_cpu_nios2_avalon_reg" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_avalon_reg:the_nios2_nios2_cpu_nios2_avalon_reg" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2692
Info (12128): Elaborating entity "nios2_nios2_cpu_nios2_ocimem" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2712
Info (12128): Elaborating entity "nios2_nios2_cpu_ociram_sp_ram_module" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2332
Info (12128): Elaborating entity "altsyncram" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram|altsyncram:the_altsyncram" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2156
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram|altsyncram:the_altsyncram" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2156
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram|altsyncram:the_altsyncram" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2156
    Info (12134): Parameter "init_file" = "UNUSED"
    Info (12134): Parameter "maximum_depth" = "0"
    Info (12134): Parameter "numwords_a" = "256"
    Info (12134): Parameter "operation_mode" = "SINGLE_PORT"
    Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED"
    Info (12134): Parameter "ram_block_type" = "AUTO"
    Info (12134): Parameter "read_during_write_mode_port_a" = "DONT_CARE"
    Info (12134): Parameter "width_a" = "32"
    Info (12134): Parameter "width_byteena_a" = "4"
    Info (12134): Parameter "widthad_a" = "8"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_qid1.tdf
    Info (12023): Found entity 1: altsyncram_qid1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_qid1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_qid1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_nios2_ocimem:the_nios2_nios2_cpu_nios2_ocimem|nios2_nios2_cpu_ociram_sp_ram_module:nios2_nios2_cpu_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_qid1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
Info (12128): Elaborating entity "nios2_nios2_cpu_debug_slave_wrapper" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu.v Line: 2814
Info (12128): Elaborating entity "nios2_nios2_cpu_debug_slave_tck" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_tck:the_nios2_nios2_cpu_debug_slave_tck" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_wrapper.v Line: 157
Info (12128): Elaborating entity "nios2_nios2_cpu_debug_slave_sysclk" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|nios2_nios2_cpu_debug_slave_sysclk:the_nios2_nios2_cpu_debug_slave_sysclk" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_wrapper.v Line: 177
Info (12128): Elaborating entity "sld_virtual_jtag_basic" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:nios2_nios2_cpu_debug_slave_phy" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_wrapper.v Line: 207
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:nios2_nios2_cpu_debug_slave_phy" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_wrapper.v Line: 207
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:nios2_nios2_cpu_debug_slave_phy" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_nios2_cpu_debug_slave_wrapper.v Line: 207
    Info (12134): Parameter "sld_auto_instance_index" = "YES"
    Info (12134): Parameter "sld_instance_index" = "0"
    Info (12134): Parameter "sld_ir_width" = "2"
    Info (12134): Parameter "sld_mfg_id" = "70"
    Info (12134): Parameter "sld_sim_action" = ""
    Info (12134): Parameter "sld_sim_n_scan" = "0"
    Info (12134): Parameter "sld_sim_total_length" = "0"
    Info (12134): Parameter "sld_type_id" = "34"
    Info (12134): Parameter "sld_version" = "3"
Info (12128): Elaborating entity "sld_virtual_jtag_impl" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:nios2_nios2_cpu_debug_slave_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v Line: 151
Info (12131): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:nios2_nios2_cpu_debug_slave_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst", which is child of megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:nios2_nios2_cpu_debug_slave_phy" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v Line: 151
Info (12128): Elaborating entity "sld_jtag_endpoint_adapter" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:nios2_nios2_cpu_debug_slave_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst|sld_jtag_endpoint_adapter:jtag_signal_adapter" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v Line: 414
Info (12128): Elaborating entity "sld_jtag_endpoint_adapter_impl" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_nios2:nios2|nios2_nios2_cpu:cpu|nios2_nios2_cpu_nios2_oci:the_nios2_nios2_cpu_nios2_oci|nios2_nios2_cpu_debug_slave_wrapper:the_nios2_nios2_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:nios2_nios2_cpu_debug_slave_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst|sld_jtag_endpoint_adapter:jtag_signal_adapter|sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd Line: 232
Info (12128): Elaborating entity "nios2_onchip_mem" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 536
Info (12128): Elaborating entity "altsyncram" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_onchip_mem.v Line: 69
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_onchip_mem.v Line: 69
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_onchip_mem.v Line: 69
    Info (12134): Parameter "byte_size" = "8"
    Info (12134): Parameter "init_file" = "J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex"
    Info (12134): Parameter "lpm_type" = "altsyncram"
    Info (12134): Parameter "maximum_depth" = "32768"
    Info (12134): Parameter "numwords_a" = "32768"
    Info (12134): Parameter "operation_mode" = "SINGLE_PORT"
    Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED"
    Info (12134): Parameter "ram_block_type" = "AUTO"
    Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info (12134): Parameter "read_during_write_mode_port_a" = "DONT_CARE"
    Info (12134): Parameter "width_a" = "32"
    Info (12134): Parameter "width_byteena_a" = "4"
    Info (12134): Parameter "widthad_a" = "15"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_pnr1.tdf
    Info (12023): Found entity 1: altsyncram_pnr1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_pnr1.tdf Line: 31
Info (12128): Elaborating entity "altsyncram_pnr1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram|altsyncram_pnr1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
Warning (113015): Width of data items in "NetApp.hex" is greater than the memory width. Wrapping data items to subsequent addresses. Found 4096 warnings, reporting 10 File: J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex Line: 1
    Warning (113009): Data at line (2) of memory initialization file "NetApp.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. File: J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex Line: 2
    Warning (113009): Data at line (3) of memory initialization file "NetApp.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. File: J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex Line: 3
    Warning (113009): Data at line (4) of memory initialization file "NetApp.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. File: J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex Line: 4
    Warning (113009): Data at line (5) of memory initialization file "NetApp.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. File: J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex Line: 5
    Warning (113009): Data at line (6) of memory initialization file "NetApp.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. File: J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex Line: 6
    Warning (113009): Data at line (7) of memory initialization file "NetApp.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. File: J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex Line: 7
    Warning (113009): Data at line (8) of memory initialization file "NetApp.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. File: J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex Line: 8
    Warning (113009): Data at line (9) of memory initialization file "NetApp.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. File: J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex Line: 9
    Warning (113009): Data at line (10) of memory initialization file "NetApp.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. File: J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex Line: 10
    Warning (113009): Data at line (11) of memory initialization file "NetApp.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. File: J:/vhdl_db/trunk/lib/eth_ethernet/etc/software/NetApp/mem_init/NetApp.hex Line: 11
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_8la.tdf
    Info (12023): Found entity 1: decode_8la File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/decode_8la.tdf Line: 22
Info (12128): Elaborating entity "decode_8la" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram|altsyncram_pnr1:auto_generated|decode_8la:decode3" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_pnr1.tdf Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_5hb.tdf
    Info (12023): Found entity 1: mux_5hb File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/mux_5hb.tdf Line: 22
Info (12128): Elaborating entity "mux_5hb" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_onchip_mem:onchip_mem|altsyncram:the_altsyncram|altsyncram_pnr1:auto_generated|mux_5hb:mux2" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_pnr1.tdf Line: 44
Info (12128): Elaborating entity "nios2_pll_enet" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_pll_enet:pll_enet" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 543
Info (12128): Elaborating entity "altera_pll" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_pll_enet:pll_enet|altera_pll:altera_pll_i" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_pll_enet.v Line: 85
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_pll_enet:pll_enet|altera_pll:altera_pll_i" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_pll_enet.v Line: 85
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_pll_enet:pll_enet|altera_pll:altera_pll_i" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_pll_enet.v Line: 85
    Info (12134): Parameter "fractional_vco_multiplier" = "false"
    Info (12134): Parameter "reference_clock_frequency" = "40.0 MHz"
    Info (12134): Parameter "operation_mode" = "direct"
    Info (12134): Parameter "number_of_clocks" = "1"
    Info (12134): Parameter "output_clock_frequency0" = "125.000000 MHz"
    Info (12134): Parameter "phase_shift0" = "0 ps"
    Info (12134): Parameter "duty_cycle0" = "50"
    Info (12134): Parameter "output_clock_frequency1" = "0 MHz"
    Info (12134): Parameter "phase_shift1" = "0 ps"
    Info (12134): Parameter "duty_cycle1" = "50"
    Info (12134): Parameter "output_clock_frequency2" = "0 MHz"
    Info (12134): Parameter "phase_shift2" = "0 ps"
    Info (12134): Parameter "duty_cycle2" = "50"
    Info (12134): Parameter "output_clock_frequency3" = "0 MHz"
    Info (12134): Parameter "phase_shift3" = "0 ps"
    Info (12134): Parameter "duty_cycle3" = "50"
    Info (12134): Parameter "output_clock_frequency4" = "0 MHz"
    Info (12134): Parameter "phase_shift4" = "0 ps"
    Info (12134): Parameter "duty_cycle4" = "50"
    Info (12134): Parameter "output_clock_frequency5" = "0 MHz"
    Info (12134): Parameter "phase_shift5" = "0 ps"
    Info (12134): Parameter "duty_cycle5" = "50"
    Info (12134): Parameter "output_clock_frequency6" = "0 MHz"
    Info (12134): Parameter "phase_shift6" = "0 ps"
    Info (12134): Parameter "duty_cycle6" = "50"
    Info (12134): Parameter "output_clock_frequency7" = "0 MHz"
    Info (12134): Parameter "phase_shift7" = "0 ps"
    Info (12134): Parameter "duty_cycle7" = "50"
    Info (12134): Parameter "output_clock_frequency8" = "0 MHz"
    Info (12134): Parameter "phase_shift8" = "0 ps"
    Info (12134): Parameter "duty_cycle8" = "50"
    Info (12134): Parameter "output_clock_frequency9" = "0 MHz"
    Info (12134): Parameter "phase_shift9" = "0 ps"
    Info (12134): Parameter "duty_cycle9" = "50"
    Info (12134): Parameter "output_clock_frequency10" = "0 MHz"
    Info (12134): Parameter "phase_shift10" = "0 ps"
    Info (12134): Parameter "duty_cycle10" = "50"
    Info (12134): Parameter "output_clock_frequency11" = "0 MHz"
    Info (12134): Parameter "phase_shift11" = "0 ps"
    Info (12134): Parameter "duty_cycle11" = "50"
    Info (12134): Parameter "output_clock_frequency12" = "0 MHz"
    Info (12134): Parameter "phase_shift12" = "0 ps"
    Info (12134): Parameter "duty_cycle12" = "50"
    Info (12134): Parameter "output_clock_frequency13" = "0 MHz"
    Info (12134): Parameter "phase_shift13" = "0 ps"
    Info (12134): Parameter "duty_cycle13" = "50"
    Info (12134): Parameter "output_clock_frequency14" = "0 MHz"
    Info (12134): Parameter "phase_shift14" = "0 ps"
    Info (12134): Parameter "duty_cycle14" = "50"
    Info (12134): Parameter "output_clock_frequency15" = "0 MHz"
    Info (12134): Parameter "phase_shift15" = "0 ps"
    Info (12134): Parameter "duty_cycle15" = "50"
    Info (12134): Parameter "output_clock_frequency16" = "0 MHz"
    Info (12134): Parameter "phase_shift16" = "0 ps"
    Info (12134): Parameter "duty_cycle16" = "50"
    Info (12134): Parameter "output_clock_frequency17" = "0 MHz"
    Info (12134): Parameter "phase_shift17" = "0 ps"
    Info (12134): Parameter "duty_cycle17" = "50"
    Info (12134): Parameter "pll_type" = "General"
    Info (12134): Parameter "pll_subtype" = "General"
Info (12128): Elaborating entity "nios2_mm_interconnect_0" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 646
Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_data_master_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 1061
Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_instruction_master_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 1121
Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 1185
Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:eth_tse_mac_control_port_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 1249
Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_csr_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 1313
Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:nios2_debug_mem_slave_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 1377
Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_rx_msgdma_descriptor_slave_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 1441
Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fabric_if_if_bridge_slave_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 1505
Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 1569
Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:ser_fifo_rx_in_csr_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 1633
Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:onchip_mem_s1_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 1761
Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:enet_nios_tx_dpram_s1_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 1825
Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:tx_ctrl_s1_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 1889
Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_data_master_agent" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 2098
Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_instruction_master_agent" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 2179
Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 2263
Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent|altera_merlin_burst_uncompressor:uncompressor" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608
Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 2304
Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_descriptor_slave_agent" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 2763
Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:enet_rx_msgdma_descriptor_slave_agent|altera_merlin_burst_uncompressor:uncompressor" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608
Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:enet_rx_msgdma_descriptor_slave_agent_rsp_fifo" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 2804
Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fabric_if_if_bridge_slave_agent_rsp_fifo" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 2929
Info (12128): Elaborating entity "nios2_mm_interconnect_0_router" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router:router" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 3945
Info (12128): Elaborating entity "nios2_mm_interconnect_0_router_default_decode" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router:router|nios2_mm_interconnect_0_router_default_decode:the_default_decode" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router.sv Line: 199
Info (12128): Elaborating entity "nios2_mm_interconnect_0_router_001" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_001:router_001" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 3961
Info (12128): Elaborating entity "nios2_mm_interconnect_0_router_001_default_decode" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_001:router_001|nios2_mm_interconnect_0_router_001_default_decode:the_default_decode" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_001.sv Line: 180
Info (12128): Elaborating entity "nios2_mm_interconnect_0_router_002" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_002" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 3977
Info (12128): Elaborating entity "nios2_mm_interconnect_0_router_002_default_decode" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_002:router_002|nios2_mm_interconnect_0_router_002_default_decode:the_default_decode" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_002.sv Line: 173
Info (12128): Elaborating entity "nios2_mm_interconnect_0_router_005" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_005:router_005" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 4025
Info (12128): Elaborating entity "nios2_mm_interconnect_0_router_005_default_decode" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_005:router_005|nios2_mm_interconnect_0_router_005_default_decode:the_default_decode" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_005.sv Line: 178
Info (12128): Elaborating entity "nios2_mm_interconnect_0_router_006" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_006:router_006" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 4041
Info (12128): Elaborating entity "nios2_mm_interconnect_0_router_006_default_decode" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_router_006:router_006|nios2_mm_interconnect_0_router_006_default_decode:the_default_decode" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_router_006.sv Line: 173
Info (12128): Elaborating entity "nios2_mm_interconnect_0_cmd_demux" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux:cmd_demux" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 4280
Info (12128): Elaborating entity "nios2_mm_interconnect_0_cmd_demux_001" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_demux_001:cmd_demux_001" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 4303
Info (12128): Elaborating entity "nios2_mm_interconnect_0_cmd_mux" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux:cmd_mux" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 4320
Info (12128): Elaborating entity "nios2_mm_interconnect_0_cmd_mux_003" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 4377
Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003|altera_merlin_arbitrator:arb" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_mux_003.sv Line: 287
Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_cmd_mux_003:cmd_mux_003|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169
Info (12128): Elaborating entity "nios2_mm_interconnect_0_rsp_demux" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_demux:rsp_demux" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 4570
Info (12128): Elaborating entity "nios2_mm_interconnect_0_rsp_mux" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux:rsp_mux" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 4898
Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_mux.sv Line: 502
Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169
Info (12128): Elaborating entity "nios2_mm_interconnect_0_rsp_mux_001" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux_001:rsp_mux_001" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 4921
Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_rsp_mux_001:rsp_mux_001|altera_merlin_arbitrator:arb" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_mux_001.sv Line: 310
Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_cmd_width_adapter" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 4987
Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_width_adapter.sv Line: 283
Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:enet_rx_msgdma_descriptor_slave_rsp_width_adapter" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 5053
Info (12128): Elaborating entity "nios2_mm_interconnect_0_avalon_st_adapter_004" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter_004:avalon_st_adapter_004" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0.v Line: 5198
Info (12128): Elaborating entity "nios2_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_0:mm_interconnect_0|nios2_mm_interconnect_0_avalon_st_adapter_004:avalon_st_adapter_004|nios2_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0:error_adapter_0" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter_004.v Line: 200
Info (12128): Elaborating entity "nios2_mm_interconnect_1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 671
Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_translator:enet_tx_msgdma_mm_read_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1.v Line: 247
Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_nios_tx_dpram_s2_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1.v Line: 311
Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:enet_udp_dpram_s2_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1.v Line: 375
Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_agent:enet_tx_msgdma_mm_read_agent" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1.v Line: 456
Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_nios_tx_dpram_s2_agent" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1.v Line: 540
Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:enet_nios_tx_dpram_s2_agent|altera_merlin_burst_uncompressor:uncompressor" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608
Info (12128): Elaborating entity "nios2_mm_interconnect_1_router" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router:router" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1.v Line: 722
Info (12128): Elaborating entity "nios2_mm_interconnect_1_router_default_decode" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router:router|nios2_mm_interconnect_1_router_default_decode:the_default_decode" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_router.sv Line: 180
Info (12128): Elaborating entity "nios2_mm_interconnect_1_router_001" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router_001:router_001" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1.v Line: 738
Info (12128): Elaborating entity "nios2_mm_interconnect_1_router_001_default_decode" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_router_001:router_001|nios2_mm_interconnect_1_router_001_default_decode:the_default_decode" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1_router_001.sv Line: 178
Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|altera_merlin_traffic_limiter:enet_tx_msgdma_mm_read_limiter" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1.v Line: 804
Info (12128): Elaborating entity "nios2_mm_interconnect_1_cmd_demux" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_cmd_demux:cmd_demux" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1.v Line: 827
Info (12128): Elaborating entity "nios2_mm_interconnect_1_cmd_mux" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_cmd_mux:cmd_mux" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1.v Line: 844
Info (12128): Elaborating entity "nios2_mm_interconnect_1_rsp_demux" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_rsp_demux:rsp_demux" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1.v Line: 878
Info (12128): Elaborating entity "nios2_mm_interconnect_1_rsp_mux" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_1:mm_interconnect_1|nios2_mm_interconnect_1_rsp_mux:rsp_mux" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_1.v Line: 918
Info (12128): Elaborating entity "nios2_mm_interconnect_2" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_2:mm_interconnect_2" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 689
Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_2:mm_interconnect_2|altera_merlin_master_translator:enet_rx_msgdma_mm_write_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_2.v Line: 97
Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_mm_interconnect_2:mm_interconnect_2|altera_merlin_slave_translator:enet_nios_rx_dpram_s2_translator" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_mm_interconnect_2.v Line: 161
Info (12128): Elaborating entity "nios2_irq_mapper" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_irq_mapper:irq_mapper" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 697
Info (12128): Elaborating entity "nios2_avalon_st_adapter" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 733
Info (12128): Elaborating entity "nios2_avalon_st_adapter_timing_adapter_0" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_avalon_st_adapter.v Line: 214
Info (12128): Elaborating entity "nios2_avalon_st_adapter_timing_adapter_0_fifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/submodules/nios2_avalon_st_adapter_timing_adapter_0.sv Line: 117
Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 796
Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|altera_reset_controller:rst_controller_002" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/nios2/synthesis/nios2.v Line: 922
Info (12128): Elaborating entity "ETH_TX_CLK" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK" File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_WRAPPER.vhd Line: 232
Info (12128): Elaborating entity "altddio_out" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK|altddio_out:ALTDDIO_OUT_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_TX_CLK.vhd Line: 60
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK|altddio_out:ALTDDIO_OUT_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_TX_CLK.vhd Line: 60
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK|altddio_out:ALTDDIO_OUT_component" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_TX_CLK.vhd Line: 60
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "extend_oe_disable" = "OFF"
    Info (12134): Parameter "invert_output" = "OFF"
    Info (12134): Parameter "oe_reg" = "UNREGISTERED"
    Info (12134): Parameter "power_up_high" = "OFF"
    Info (12134): Parameter "width" = "1"
    Info (12134): Parameter "lpm_hint" = "UNUSED"
    Info (12134): Parameter "lpm_type" = "altddio_out"
Info (12021): Found 1 design units, including 1 entities, in source file db/ddio_out_b2j.tdf
    Info (12023): Found entity 1: ddio_out_b2j File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ddio_out_b2j.tdf Line: 27
Info (12128): Elaborating entity "ddio_out_b2j" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_TX_CLK:C_ETH_PCLK|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altddio_out.tdf Line: 100
Info (12128): Elaborating entity "ETH_MSGDMA_WRAPPER" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER" File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_WRAPPER.vhd Line: 240
Info (12128): Elaborating entity "ETH_MSGDMA_CSR_SM" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_CSR_SM:C_MSGDMA_CSR_SM" File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_WRAPPER.vhd Line: 129
Info (12128): Elaborating entity "ETH_MSGDMA_DESC_SM" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DESC_SM:C_MSGDMA_DESC_SM" File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_WRAPPER.vhd Line: 151
Info (12128): Elaborating entity "ETH_FIFOS_TO_DPRAM_SM" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFOS_TO_DPRAM_SM:C_SM" File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_WRAPPER.vhd Line: 178
Info (12128): Elaborating entity "ETH_MSGDMA_DISPATCHER" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_DISPATCHER:C_MSGDMA_DISPATCHER" File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_WRAPPER.vhd Line: 224
Info (12128): Elaborating entity "ETH_MSGDMA_IRQ_FIFO" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO" File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_WRAPPER.vhd Line: 270
Info (12128): Elaborating entity "scfifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_MSGDMA_IRQ_FIFO.vhd Line: 99
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_MSGDMA_IRQ_FIFO.vhd Line: 99
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_MSGDMA_IRQ_FIFO.vhd Line: 99
    Info (12134): Parameter "add_ram_output_register" = "OFF"
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "4"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "scfifo"
    Info (12134): Parameter "lpm_width" = "3"
    Info (12134): Parameter "lpm_widthu" = "2"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "OFF"
Info (12128): Elaborating entity "a_fffifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/scfifo.tdf Line: 278
Info (12131): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo", which is child of megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/scfifo.tdf Line: 278
Info (12128): Elaborating entity "lpm_ff" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_ff:last_data_node[3]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fffifo.tdf Line: 101
Info (12131): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_ff:last_data_node[3]", which is child of megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fffifo.tdf Line: 101
Info (12128): Elaborating entity "lpm_mux" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_mux:last_row_data_out_mux" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fffifo.tdf Line: 102
Info (12131): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_mux:last_row_data_out_mux", which is child of megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fffifo.tdf Line: 102
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_ujc.tdf
    Info (12023): Found entity 1: mux_ujc File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/mux_ujc.tdf Line: 22
Info (12128): Elaborating entity "mux_ujc" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_mux:last_row_data_out_mux|mux_ujc:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_mux.tdf Line: 86
Info (12128): Elaborating entity "lpm_counter" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_counter:rd_ptr" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fffifo.tdf Line: 104
Info (12131): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_counter:rd_ptr", which is child of megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fffifo.tdf Line: 104
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_j3f.tdf
    Info (12023): Found entity 1: cntr_j3f File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cntr_j3f.tdf Line: 25
Info (12128): Elaborating entity "cntr_j3f" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|lpm_counter:rd_ptr|cntr_j3f:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_counter.tdf Line: 258
Info (12128): Elaborating entity "a_fefifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|a_fefifo:fifo_state" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fffifo.tdf Line: 111
Info (12131): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|a_fefifo:fifo_state", which is child of megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fffifo.tdf Line: 111
Info (12128): Elaborating entity "lpm_compare" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_empty_compare" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fefifo.tdf Line: 76
Info (12131): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_empty_compare", which is child of megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fefifo.tdf Line: 76
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_p7g.tdf
    Info (12023): Found entity 1: cmpr_p7g File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cmpr_p7g.tdf Line: 22
Info (12128): Elaborating entity "cmpr_p7g" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_empty_compare|cmpr_p7g:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_compare.tdf Line: 280
Info (12128): Elaborating entity "lpm_compare" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_full_compare" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fefifo.tdf Line: 81
Info (12131): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_full_compare", which is child of megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_MSGDMA_IRQ_FIFO:C_IRQ_FIFO|scfifo:scfifo_component" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fefifo.tdf Line: 81
Info (12128): Elaborating entity "ETH_FIFO_CHECK" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFO_CHECK:C_SC_FIFO_CHECK" File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_WRAPPER.vhd Line: 285
Info (12128): Elaborating entity "ETH_FIFO_CHECK" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|ETH_MSGDMA_WRAPPER:C_ETH_MSGDMA_WRAPPER|ETH_FIFO_CHECK:C_DAQ_FIFO_CHECK" File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_MSGDMA_WRAPPER.vhd Line: 302
Info (12128): Elaborating entity "ETH_SC_FIFO_TX" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX" File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_UFP_WRAPPER.vhd Line: 260
Info (12128): Elaborating entity "dcfifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_SC_FIFO_TX.vhd Line: 104
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_SC_FIFO_TX.vhd Line: 104
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_SC_FIFO_TX.vhd Line: 104
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "128"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_width" = "32"
    Info (12134): Parameter "lpm_widthu" = "7"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "4"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "wrsync_delaypipe" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_p6n1.tdf
    Info (12023): Found entity 1: dcfifo_p6n1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_p6n1.tdf Line: 40
Info (12128): Elaborating entity "dcfifo_p6n1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo.tdf Line: 190
Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_f9b.tdf
    Info (12023): Found entity 1: a_gray2bin_f9b File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_gray2bin_f9b.tdf Line: 22
Info (12128): Elaborating entity "a_gray2bin_f9b" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|a_gray2bin_f9b:rdptr_g_gray2bin" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_p6n1.tdf Line: 54
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_cg6.tdf
    Info (12023): Found entity 1: a_graycounter_cg6 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_graycounter_cg6.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_cg6" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|a_graycounter_cg6:rdptr_g1p" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_p6n1.tdf Line: 58
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_8ub.tdf
    Info (12023): Found entity 1: a_graycounter_8ub File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_graycounter_8ub.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_8ub" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|a_graycounter_8ub:wrptr_g1p" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_p6n1.tdf Line: 59
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_cia1.tdf
    Info (12023): Found entity 1: altsyncram_cia1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_cia1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_cia1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|altsyncram_cia1:fifo_ram" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_p6n1.tdf Line: 60
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_0v8.tdf
    Info (12023): Found entity 1: dffpipe_0v8 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_0v8.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_0v8" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|dffpipe_0v8:rs_brp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_p6n1.tdf Line: 67
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_g9l.tdf
    Info (12023): Found entity 1: alt_synch_pipe_g9l File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_g9l.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_g9l" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_p6n1.tdf Line: 69
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_1v8.tdf
    Info (12023): Found entity 1: dffpipe_1v8 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_1v8.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_1v8" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_g9l:rs_dgwp|dffpipe_1v8:dffpipe13" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_g9l.tdf Line: 33
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_h9l.tdf
    Info (12023): Found entity 1: alt_synch_pipe_h9l File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_h9l.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_h9l" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_p6n1.tdf Line: 72
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_2v8.tdf
    Info (12023): Found entity 1: dffpipe_2v8 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_2v8.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_2v8" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|alt_synch_pipe_h9l:ws_dgrp|dffpipe_2v8:dffpipe16" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_h9l.tdf Line: 33
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_0v5.tdf
    Info (12023): Found entity 1: cmpr_0v5 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cmpr_0v5.tdf Line: 22
Info (12128): Elaborating entity "cmpr_0v5" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_TX:C_SC_FIFO_TX|dcfifo:dcfifo_component|dcfifo_p6n1:auto_generated|cmpr_0v5:rdempty_eq_comp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_p6n1.tdf Line: 79
Info (12128): Elaborating entity "ETH_SC_FIFO_RX" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX" File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_UFP_WRAPPER.vhd Line: 277
Info (12128): Elaborating entity "scfifo" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_SC_FIFO_RX.vhd Line: 97
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component" File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_SC_FIFO_RX.vhd Line: 97
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component" with the following parameter: File: J:/vhdl_db/trunk/lib/eth_ethernet/c_cyclone5/src/ETH_SC_FIFO_RX.vhd Line: 97
    Info (12134): Parameter "add_ram_output_register" = "OFF"
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "64"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "scfifo"
    Info (12134): Parameter "lpm_width" = "32"
    Info (12134): Parameter "lpm_widthu" = "6"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_7l91.tdf
    Info (12023): Found entity 1: scfifo_7l91 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/scfifo_7l91.tdf Line: 24
Info (12128): Elaborating entity "scfifo_7l91" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component|scfifo_7l91:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/scfifo.tdf Line: 299
Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_er91.tdf
    Info (12023): Found entity 1: a_dpfifo_er91 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_er91.tdf Line: 28
Info (12128): Elaborating entity "a_dpfifo_er91" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component|scfifo_7l91:auto_generated|a_dpfifo_er91:dpfifo" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/scfifo_7l91.tdf Line: 36
Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_b6f.tdf
    Info (12023): Found entity 1: a_fefifo_b6f File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_fefifo_b6f.tdf Line: 24
Info (12128): Elaborating entity "a_fefifo_b6f" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component|scfifo_7l91:auto_generated|a_dpfifo_er91:dpfifo|a_fefifo_b6f:fifo_state" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_er91.tdf Line: 41
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_sqs1.tdf
    Info (12023): Found entity 1: altsyncram_sqs1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_sqs1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_sqs1" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_SC_FIFO_RX:C_SC_FIFO_RX|scfifo:scfifo_component|scfifo_7l91:auto_generated|a_dpfifo_er91:dpfifo|altsyncram_sqs1:FIFOram" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_dpfifo_er91.tdf Line: 42
Info (12128): Elaborating entity "ser_crc_pol16_DIN16_D4_1a2eb" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC" File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_UFP_WRAPPER.vhd Line: 293
Info (12128): Elaborating entity "ser_crc" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/crc_pol/ser_crc_pol16_DIN16_D4_1a2eb.vhd Line: 47
Info (12128): Elaborating entity "UFP_ENCODER_UART" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_ENCODER_UART:C_ENCODER" File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_UFP_WRAPPER.vhd Line: 308
Info (12128): Elaborating entity "UFP_DECODER" for hierarchy "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|UFP_DECODER:C_DECODER" File: J:/vhdl_db/trunk/lib/eth_ethernet/src/ETH_UFP_WRAPPER.vhd Line: 364
Info (12128): Elaborating entity "FTR_L2_FIFO" for hierarchy "FTR_L2_FIFO:C_L2_FIFO" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 514
Info (12128): Elaborating entity "dcfifo" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_FIFO.vhd Line: 108
Info (12130): Elaborated megafunction instantiation "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_FIFO.vhd Line: 108
Info (12133): Instantiated megafunction "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component" with the following parameter: File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_FIFO.vhd Line: 108
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "65536"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_width" = "33"
    Info (12134): Parameter "lpm_widthu" = "16"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "4"
    Info (12134): Parameter "read_aclr_synch" = "OFF"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "write_aclr_synch" = "OFF"
    Info (12134): Parameter "wrsync_delaypipe" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_kvr1.tdf
    Info (12023): Found entity 1: dcfifo_kvr1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_kvr1.tdf Line: 40
Info (12128): Elaborating entity "dcfifo_kvr1" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo.tdf Line: 190
Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_vab.tdf
    Info (12023): Found entity 1: a_gray2bin_vab File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_gray2bin_vab.tdf Line: 22
Info (12128): Elaborating entity "a_gray2bin_vab" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_gray2bin_vab:rdptr_g_gray2bin" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_kvr1.tdf Line: 55
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_uv6.tdf
    Info (12023): Found entity 1: a_graycounter_uv6 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_graycounter_uv6.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_uv6" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_uv6:rdptr_g1p" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_kvr1.tdf Line: 59
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_qdc.tdf
    Info (12023): Found entity 1: a_graycounter_qdc File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/a_graycounter_qdc.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_qdc" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_qdc:wrptr_g1p" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_kvr1.tdf Line: 60
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_29d1.tdf
    Info (12023): Found entity 1: altsyncram_29d1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_29d1.tdf Line: 31
Info (12128): Elaborating entity "altsyncram_29d1" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_kvr1.tdf Line: 61
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_417.tdf
    Info (12023): Found entity 1: decode_417 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/decode_417.tdf Line: 22
Info (12128): Elaborating entity "decode_417" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|decode_417:decode12" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_29d1.tdf Line: 48
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_2t7.tdf
    Info (12023): Found entity 1: mux_2t7 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/mux_2t7.tdf Line: 22
Info (12128): Elaborating entity "mux_2t7" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|mux_2t7:mux13" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_29d1.tdf Line: 50
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_2f9.tdf
    Info (12023): Found entity 1: dffpipe_2f9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_2f9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_2f9" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_2f9:rs_brp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_kvr1.tdf Line: 68
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_gpl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_gpl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_gpl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_gpl" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_kvr1.tdf Line: 70
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_3f9.tdf
    Info (12023): Found entity 1: dffpipe_3f9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_3f9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_3f9" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_gpl:rs_dgwp|dffpipe_3f9:dffpipe15" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_gpl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_hpl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_hpl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_hpl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_hpl" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_kvr1.tdf Line: 73
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_4f9.tdf
    Info (12023): Found entity 1: dffpipe_4f9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_4f9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_4f9" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_hpl:ws_dgrp|dffpipe_4f9:dffpipe18" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_hpl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_g06.tdf
    Info (12023): Found entity 1: cmpr_g06 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cmpr_g06.tdf Line: 22
Info (12128): Elaborating entity "cmpr_g06" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|cmpr_g06:rdempty_eq_comp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_kvr1.tdf Line: 80
Info (12128): Elaborating entity "FTR_REG_WRAPPER" for hierarchy "FTR_REG_WRAPPER:C_REGS" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 534
Info (12128): Elaborating entity "UFP_USER_SET_CONFIG" for hierarchy "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 90
Info (12128): Elaborating entity "UFP_USER_GET_CONFIG" for hierarchy "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 110
Info (12128): Elaborating entity "UFP_USER_SET_CONFIG" for hierarchy "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 135
Info (12128): Elaborating entity "UFP_USER_GET_CONFIG" for hierarchy "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 155
Info (12128): Elaborating entity "UFP_USER_SET_CONFIG" for hierarchy "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 180
Info (12128): Elaborating entity "UFP_USER_GET_CONFIG" for hierarchy "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 201
Info (12128): Elaborating entity "UFP_USER_SET_CONFIG" for hierarchy "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 226
Info (12128): Elaborating entity "UFP_USER_SETGET_ACK" for hierarchy "FTR_REG_WRAPPER:C_REGS|UFP_USER_SETGET_ACK:C_GET_ACK" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 248
Info (12128): Elaborating entity "FTR_FaserWrapper" for hierarchy "FTR_FaserWrapper:C_WRAPPER" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 569
Info (12128): Elaborating entity "FTR_L2_SM" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FaserWrapper.vhd Line: 196
Info (12128): Elaborating entity "FTR_RXDataPlaneManager" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FaserWrapper.vhd Line: 247
Info (12128): Elaborating entity "FTR_RXDataModuleManager" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_RXDataPlaneManager.vhd Line: 80
Info (12128): Elaborating entity "FTR_L1_FIFO" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_RXDataPlaneManager.vhd Line: 139
Info (12128): Elaborating entity "dcfifo" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L1_FIFO.vhd Line: 108
Info (12130): Elaborated megafunction instantiation "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L1_FIFO.vhd Line: 108
Info (12133): Instantiated megafunction "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component" with the following parameter: File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L1_FIFO.vhd Line: 108
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "2048"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_width" = "26"
    Info (12134): Parameter "lpm_widthu" = "11"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "4"
    Info (12134): Parameter "read_aclr_synch" = "OFF"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "write_aclr_synch" = "OFF"
    Info (12134): Parameter "wrsync_delaypipe" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_jtr1.tdf
    Info (12023): Found entity 1: dcfifo_jtr1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_jtr1.tdf Line: 40
Info (12128): Elaborating entity "dcfifo_jtr1" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo.tdf Line: 190
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_t8d1.tdf
    Info (12023): Found entity 1: altsyncram_t8d1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_t8d1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_t8d1" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_jtr1.tdf Line: 61
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_epl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_epl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_epl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_epl" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_jtr1.tdf Line: 70
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_0f9.tdf
    Info (12023): Found entity 1: dffpipe_0f9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_0f9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_0f9" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_epl:rs_dgwp|dffpipe_0f9:dffpipe6" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_epl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_fpl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_fpl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_fpl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_fpl" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dcfifo_jtr1.tdf Line: 73
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_1f9.tdf
    Info (12023): Found entity 1: dffpipe_1f9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/dffpipe_1f9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_1f9" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_fpl:ws_dgrp|dffpipe_1f9:dffpipe9" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/alt_synch_pipe_fpl.tdf Line: 34
Info (12128): Elaborating entity "FTR_PlaneController" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FaserWrapper.vhd Line: 280
Info (12128): Elaborating entity "FTR_PlaneControllerSM" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PlaneController.vhd Line: 104
Info (12128): Elaborating entity "FTR_PatchPanelControllerSM" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PlaneController.vhd Line: 160
Info (12128): Elaborating entity "USB_UC_PCLK" for hierarchy "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FaserWrapper.vhd Line: 342
Warning (12030): Port "extclk" on the entity instantiation of "cyclonev_pll" is connected to a signal of width 1. The formal width of the signal in the module is 2.  The extra bits will be left dangling without any fan-out logic. File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 2223
Info (11170): Starting IP generation for the debug fabric: alt_sld_fab.
Info (11172): 2020.11.30.09:46:25 Progress: Loading sldb91a0071/alt_sld_fab_wrapper_hw.tcl
Info (11172): Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG
Info (11172): Alt_sld_fab: Generating alt_sld_fab "alt_sld_fab" for QUARTUS_SYNTH
Info (11172): Alt_sld_fab: "alt_sld_fab" instantiated alt_sld_fab "alt_sld_fab"
Info (11172): Presplit: "alt_sld_fab" instantiated altera_super_splitter "presplit"
Info (11172): Splitter: "alt_sld_fab" instantiated altera_sld_splitter "splitter"
Info (11172): Sldfabric: "alt_sld_fab" instantiated altera_sld_jtag_hub "sldfabric"
Info (11172): Ident: "alt_sld_fab" instantiated altera_connection_identification_hub "ident"
Info (11172): Alt_sld_fab: Done "alt_sld_fab" with 6 modules, 6 files
Info (11171): Finished IP generation for the debug fabric: alt_sld_fab.
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sldb91a0071/alt_sld_fab.v
    Info (12023): Found entity 1: alt_sld_fab File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ip/sldb91a0071/alt_sld_fab.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab.v
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_ident.sv
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_ident File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_ident.sv Line: 33
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_presplit.sv
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_presplit File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_presplit.sv Line: 3
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd
    Info (12022): Found design unit 1: alt_sld_fab_alt_sld_fab_sldfabric-rtl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd Line: 142
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_sldfabric File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd Line: 11
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_splitter.sv
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_splitter File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/ip/sldb91a0071/submodules/alt_sld_fab_alt_sld_fab_splitter.sv Line: 3
Warning (14284): Synthesized away the following node(s):
    Warning (14285): Synthesized away the following RAM node(s):
        Warning (14320): Synthesized away node "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|ram_block11a32" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_29d1.tdf Line: 1075
        Warning (14320): Synthesized away node "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|ram_block11a65" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_29d1.tdf Line: 2131
        Warning (14320): Synthesized away node "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|ram_block11a98" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_29d1.tdf Line: 3187
        Warning (14320): Synthesized away node "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|ram_block11a131" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_29d1.tdf Line: 4243
        Warning (14320): Synthesized away node "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|ram_block11a164" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_29d1.tdf Line: 5299
        Warning (14320): Synthesized away node "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|ram_block11a197" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_29d1.tdf Line: 6355
        Warning (14320): Synthesized away node "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|ram_block11a230" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_29d1.tdf Line: 7411
        Warning (14320): Synthesized away node "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|ram_block11a263" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_29d1.tdf Line: 8467
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram:altsyncram_component|altsyncram_n3o1:auto_generated|q_b[0]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_n3o1.tdf Line: 38
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram:altsyncram_component|altsyncram_n3o1:auto_generated|q_b[1]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_n3o1.tdf Line: 69
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram:altsyncram_component|altsyncram_n3o1:auto_generated|q_b[2]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_n3o1.tdf Line: 100
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram:altsyncram_component|altsyncram_n3o1:auto_generated|q_b[3]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_n3o1.tdf Line: 131
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram:altsyncram_component|altsyncram_n3o1:auto_generated|q_b[4]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_n3o1.tdf Line: 162
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram:altsyncram_component|altsyncram_n3o1:auto_generated|q_b[5]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_n3o1.tdf Line: 193
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram:altsyncram_component|altsyncram_n3o1:auto_generated|q_b[6]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_n3o1.tdf Line: 224
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram:altsyncram_component|altsyncram_n3o1:auto_generated|q_b[7]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_n3o1.tdf Line: 255
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram:altsyncram_component|altsyncram_n3o1:auto_generated|q_b[8]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_n3o1.tdf Line: 286
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram:altsyncram_component|altsyncram_n3o1:auto_generated|q_b[9]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_n3o1.tdf Line: 317
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[4]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 162
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[5]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 193
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[6]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 224
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[7]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 255
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[8]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 286
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[9]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 317
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[10]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 348
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[11]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 379
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[12]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 410
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[13]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 441
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[14]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 472
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[15]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 503
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[16]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 534
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[17]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 565
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[18]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 596
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[19]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 627
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[20]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 658
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_b9o1:auto_generated|q_b[22]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_b9o1.tdf Line: 720
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_5ao1:auto_generated|q_b[34]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_5ao1.tdf Line: 1092
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_5ao1:auto_generated|q_b[35]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_5ao1.tdf Line: 1123
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_5ao1:auto_generated|q_b[36]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_5ao1.tdf Line: 1154
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_5ao1:auto_generated|q_b[37]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_5ao1.tdf Line: 1185
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo|altsyncram_3hn1:FIFOram|q_b[36]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_3hn1.tdf Line: 1191
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo|altsyncram_3hn1:FIFOram|q_b[37]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_3hn1.tdf Line: 1223
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo|altsyncram_3hn1:FIFOram|q_b[38]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_3hn1.tdf Line: 1255
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo|altsyncram_3hn1:FIFOram|q_b[39]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_3hn1.tdf Line: 1287
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo|altsyncram_3hn1:FIFOram|q_b[40]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_3hn1.tdf Line: 1319
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo|altsyncram_3hn1:FIFOram|q_b[41]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_3hn1.tdf Line: 1351
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo|altsyncram_3hn1:FIFOram|q_b[42]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_3hn1.tdf Line: 1383
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|read_master:read_mstr_internal|scfifo:the_master_to_st_fifo|scfifo_s871:auto_generated|a_dpfifo_f071:dpfifo|altsyncram_3hn1:FIFOram|q_b[43]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_3hn1.tdf Line: 1415
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[0]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 38
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[1]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 71
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[2]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 104
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[3]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 137
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[4]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 170
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[5]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 203
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[6]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 236
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[7]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 269
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[8]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 302
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[9]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 335
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[10]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 368
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[11]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 401
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[12]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 434
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[13]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 467
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[14]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 500
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[15]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 533
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[16]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 566
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[17]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 599
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[18]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 632
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[19]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 665
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[20]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 698
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[21]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 731
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[22]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 764
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[23]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 797
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[24]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 830
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[25]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 863
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[26]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 896
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[27]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 929
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[28]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 962
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[29]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 995
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[30]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1028
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[31]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1061
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[32]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1094
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[33]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1127
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[34]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1160
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[35]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1193
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[36]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1226
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[37]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1259
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[38]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1292
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[39]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1325
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[40]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1358
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[41]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1391
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[42]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1424
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[43]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1457
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[44]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1490
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[45]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1523
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[46]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1556
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[47]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1589
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[48]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1622
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[49]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1655
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[50]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1688
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[51]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1721
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[52]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1754
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[53]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1787
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[54]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1820
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[55]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1853
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[56]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1886
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[57]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1919
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[58]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1952
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[59]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1985
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[60]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2018
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[61]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2051
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[62]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2084
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[63]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2117
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[64]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2150
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[65]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2183
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[66]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2216
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[67]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2249
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[68]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2282
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[69]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2315
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[70]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2348
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[71]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2381
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[72]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2414
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[73]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2447
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[74]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2480
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[75]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2513
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[76]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2546
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[77]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2579
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[78]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2612
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[79]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2645
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[80]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2678
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[81]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2711
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[82]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2744
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[83]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2777
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[84]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2810
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[85]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2843
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[86]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2876
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[87]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2909
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[88]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2942
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[89]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2975
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[90]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3008
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[91]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3041
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[92]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3074
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[93]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3107
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[94]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3140
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[95]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3173
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[96]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3206
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[97]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3239
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[98]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3272
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[99]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3305
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[100]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3338
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[101]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3371
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[102]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3404
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[103]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3437
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[104]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3470
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[105]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3503
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[106]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3536
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[107]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3569
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[108]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3602
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[109]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3635
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[110]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3668
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[111]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3701
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[112]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3734
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[113]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3767
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[114]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3800
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[115]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3833
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[116]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3866
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[117]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3899
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[118]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3932
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[119]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3965
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[120]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3998
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[121]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4031
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[122]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4064
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[123]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4097
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[124]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4130
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[125]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4163
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[126]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4196
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[127]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4229
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[14]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 500
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[15]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 533
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[16]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 566
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[17]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 599
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[18]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 632
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[19]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 665
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[20]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 698
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[21]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 731
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[22]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 764
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[23]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 797
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[24]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 830
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[25]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 863
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[26]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 896
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[27]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 929
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[28]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 962
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[29]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 995
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[30]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1028
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[31]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1061
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[32]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1094
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[33]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1127
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[34]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1160
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[35]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1193
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[36]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1226
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[37]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1259
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[38]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1292
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[39]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1325
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[40]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1358
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[41]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1391
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[42]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1424
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[43]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1457
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[44]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1490
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[45]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1523
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[46]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1556
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[47]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1589
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[48]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1622
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[49]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1655
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[50]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1688
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[51]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1721
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[52]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1754
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[53]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1787
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[54]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1820
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[55]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1853
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[56]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1886
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[57]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1919
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[58]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1952
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[59]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1985
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[60]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2018
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[61]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2051
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[62]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2084
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[63]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2117
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[76]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2546
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[77]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2579
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[78]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2612
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[79]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2645
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[80]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2678
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[81]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2711
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[82]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2744
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[83]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2777
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[84]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2810
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[85]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2843
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[86]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2876
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[87]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2909
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[88]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2942
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[89]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2975
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[90]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3008
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[91]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3041
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[92]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3074
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[93]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3107
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[94]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3140
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[95]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3173
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[107]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3569
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[108]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3602
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[109]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3635
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[111]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3701
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[113]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3767
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[114]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3800
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[115]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3833
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[116]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3866
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[117]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3899
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[118]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3932
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[119]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3965
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[120]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3998
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[121]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4031
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[122]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4064
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[123]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4097
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[124]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4130
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[125]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4163
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[126]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4196
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[127]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4229
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|write_master:write_mstr_internal|scfifo:the_st_to_master_fifo|scfifo_p871:auto_generated|a_dpfifo_c071:dpfifo|altsyncram_tgn1:FIFOram|q_b[33]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_tgn1.tdf Line: 1095
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[0]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 38
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[1]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 71
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[2]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 104
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[3]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 137
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[4]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 170
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[5]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 203
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[6]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 236
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[7]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 269
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[8]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 302
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[9]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 335
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[10]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 368
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[11]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 401
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[12]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 434
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[13]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 467
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[14]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 500
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[15]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 533
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[16]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 566
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[17]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 599
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[18]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 632
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[19]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 665
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[20]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 698
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[21]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 731
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[22]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 764
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[23]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 797
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[24]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 830
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[25]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 863
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[26]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 896
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[27]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 929
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[28]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 962
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[29]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 995
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[30]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1028
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[31]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1061
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[43]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1457
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[44]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1490
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[45]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1523
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[46]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1556
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[47]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1589
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[48]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1622
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[49]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1655
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[50]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1688
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[51]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1721
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[52]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1754
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[53]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1787
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[54]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1820
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[55]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1853
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[56]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1886
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[57]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1919
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[58]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1952
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[59]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1985
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[60]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2018
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[61]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2051
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[62]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2084
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[63]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2117
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[76]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2546
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[77]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2579
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[78]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2612
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[79]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2645
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[80]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2678
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[81]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2711
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[82]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2744
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[83]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2777
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[84]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2810
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[85]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2843
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[86]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2876
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[87]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2909
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[88]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2942
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[89]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2975
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[90]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3008
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[91]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3041
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[92]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3074
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[93]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3107
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[94]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3140
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[95]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3173
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[96]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3206
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[97]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3239
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[98]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3272
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[99]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3305
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[100]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3338
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[101]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3371
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[102]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3404
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[103]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3437
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[104]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3470
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[105]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3503
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[106]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3536
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[109]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3635
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[118]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3932
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[119]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3965
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[120]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3998
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[121]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4031
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[122]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4064
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[123]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4097
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[124]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4130
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[125]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4163
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[126]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4196
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[127]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4229
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[0]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 38
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[1]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 71
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[2]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 104
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[3]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 137
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[4]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 170
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[5]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 203
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[6]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 236
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[7]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 269
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[8]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 302
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[9]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 335
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[10]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 368
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[11]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 401
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[12]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 434
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[13]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 467
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[14]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 500
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[15]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 533
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[16]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 566
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[17]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 599
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[18]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 632
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[19]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 665
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[20]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 698
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[21]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 731
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[22]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 764
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[23]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 797
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[24]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 830
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[25]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 863
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[26]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 896
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[27]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 929
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[28]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 962
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[29]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 995
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[30]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1028
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[31]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1061
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[32]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1094
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[33]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1127
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[34]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1160
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[35]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1193
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[36]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1226
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[37]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1259
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[38]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1292
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[39]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1325
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[40]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1358
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[41]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1391
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[42]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1424
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[43]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1457
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[44]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1490
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[45]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1523
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[46]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1556
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[47]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1589
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[48]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1622
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[49]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1655
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[50]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1688
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[51]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1721
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[52]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1754
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[53]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1787
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[54]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1820
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[55]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1853
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[56]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1886
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[57]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1919
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[58]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1952
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[59]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1985
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[60]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2018
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[61]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2051
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[62]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2084
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[63]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2117
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[64]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2150
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[65]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2183
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[66]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2216
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[67]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2249
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[68]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2282
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[69]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2315
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[70]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2348
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[71]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2381
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[72]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2414
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[73]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2447
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[74]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2480
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[75]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2513
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[76]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2546
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[77]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2579
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[78]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2612
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[79]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2645
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[80]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2678
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[81]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2711
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[82]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2744
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[83]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2777
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[84]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2810
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[85]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2843
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[86]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2876
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[87]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2909
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[88]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2942
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[89]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 2975
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[90]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3008
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[91]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3041
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[92]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3074
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[93]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3107
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[94]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3140
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[95]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3173
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[96]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3206
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[97]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3239
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[98]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3272
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[99]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3305
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[100]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3338
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[101]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3371
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[102]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3404
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[103]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3437
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[104]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3470
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[105]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3503
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[106]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3536
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[107]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3569
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[108]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3602
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[109]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3635
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[110]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3668
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[111]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3701
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[112]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3734
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[113]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3767
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[114]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3800
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[115]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3833
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[116]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3866
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[117]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3899
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[118]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3932
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[119]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3965
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[120]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3998
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[121]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4031
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[122]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4064
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[123]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4097
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[124]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4130
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[125]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4163
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[126]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4196
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[127]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 4229
    Warning (14285): Synthesized away the following PLL node(s):
        Warning (14320): Synthesized away node "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i|outclk_wire[1]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 748
Warning (14284): Synthesized away the following node(s):
    Warning (14285): Synthesized away the following RAM node(s):
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[96]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3206
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[97]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3239
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[98]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3272
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[99]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3305
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[100]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3338
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[101]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3371
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[102]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3404
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[103]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 3437
Warning (19016): Clock multiplexers are found and protected
    Warning (19017): Found clock multiplexer FTR_CLK_WRAPPER:C_CLK_WRAPPER|sl_int_sel_clk~0 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_CLK_WRAPPER.vhd Line: 74
Warning (14284): Synthesized away the following node(s):
    Warning (14285): Synthesized away the following RAM node(s):
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[33]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1127
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_rx_msgdma:enet_rx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_write_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[32]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 1094
Warning (14284): Synthesized away the following node(s):
    Warning (14285): Synthesized away the following RAM node(s):
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[1]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 71
        Warning (14320): Synthesized away node "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_enet_tx_msgdma:enet_tx_msgdma|dispatcher:dispatcher_internal|descriptor_buffers:the_descriptor_buffers|fifo_with_byteenables:the_read_command_FIFO|altsyncram:the_dp_ram|altsyncram_p5j1:auto_generated|q_b[0]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_p5j1.tdf Line: 38
Info (19000): Inferred 2 megafunctions from design logic
    Info (276029): Inferred altsyncram megafunction from the following design logic: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo|mem_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 42
        Info (286033): Parameter WIDTHAD_A set to 4
        Info (286033): Parameter NUMWORDS_A set to 16
        Info (286033): Parameter WIDTH_B set to 42
        Info (286033): Parameter WIDTHAD_B set to 4
        Info (286033): Parameter NUMWORDS_B set to 16
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
    Info (276034): Inferred altshift_taps megafunction from the following design logic: "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_altshifttaps:U_SHIFTTAPS|shift_reg_rtl_0"
        Info (286033): Parameter NUMBER_OF_TAPS set to 1
        Info (286033): Parameter TAP_DISTANCE set to 16
        Info (286033): Parameter WIDTH set to 8
        Info (286033): Parameter POWER_UP_STATE set to DONT_CARE
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_altshifttaps:U_SHIFTTAPS|altshift_taps:shift_reg_rtl_0"
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_eth_tse_mac:eth_tse_mac|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_altshifttaps:U_SHIFTTAPS|altshift_taps:shift_reg_rtl_0" with the following parameter:
    Info (12134): Parameter "NUMBER_OF_TAPS" = "1"
    Info (12134): Parameter "TAP_DISTANCE" = "16"
    Info (12134): Parameter "WIDTH" = "8"
    Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE"
Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_ffv.tdf
    Info (12023): Found entity 1: shift_taps_ffv File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/shift_taps_ffv.tdf Line: 26
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_1r91.tdf
    Info (12023): Found entity 1: altsyncram_1r91 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_1r91.tdf Line: 27
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_eif.tdf
    Info (12023): Found entity 1: cntr_eif File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/cntr_eif.tdf Line: 25
Info (12130): Elaborated megafunction instantiation "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo|altsyncram:mem_rtl_0"
Info (12133): Instantiated megafunction "ETH_UFP_WRAPPER:C_ETH_UFP_WRAPPER|ETH_WRAPPER:C_ETH_WRAPPER|nios2:C_NIOS_SYS|nios2_avalon_st_adapter:avalon_st_adapter|nios2_avalon_st_adapter_timing_adapter_0:timing_adapter_0|nios2_avalon_st_adapter_timing_adapter_0_fifo:nios2_avalon_st_adapter_timing_adapter_0_fifo|altsyncram:mem_rtl_0" with the following parameter:
    Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
    Info (12134): Parameter "WIDTH_A" = "42"
    Info (12134): Parameter "WIDTHAD_A" = "4"
    Info (12134): Parameter "NUMWORDS_A" = "16"
    Info (12134): Parameter "WIDTH_B" = "42"
    Info (12134): Parameter "WIDTHAD_B" = "4"
    Info (12134): Parameter "NUMWORDS_B" = "16"
    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
    Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
    Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
    Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
    Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
    Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_23n1.tdf
    Info (12023): Found entity 1: altsyncram_23n1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/db/altsyncram_23n1.tdf Line: 27
Warning (12241): 22 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Info (13000): Registers with preset signals will power-up high File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc.vhd Line: 148
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "x_DAC_SCK" is stuck at GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 48
    Warning (13410): Pin "x_UC_CLK_USB" is stuck at GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 28
    Warning (13410): Pin "x_UC_SLCSn" is stuck at VCC File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 29
    Warning (13410): Pin "x_UC_SLWRn" is stuck at VCC File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 30
    Warning (13410): Pin "x_UC_SLRDn" is stuck at VCC File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 31
    Warning (13410): Pin "x_UC_SLOEn" is stuck at VCC File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 32
    Warning (13410): Pin "x_UC_PKENDn" is stuck at VCC File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 33
    Warning (13410): Pin "x_UC_A[0]" is stuck at GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 34
    Warning (13410): Pin "x_UC_A[1]" is stuck at GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 34
    Warning (13410): Pin "x_UC_UART_RX" is stuck at VCC File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 40
    Warning (13410): Pin "x_UC_UART_CTSn" is stuck at VCC File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 42
    Warning (13410): Pin "x_DAC_CS" is stuck at GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 46
    Warning (13410): Pin "x_DAC_SDI" is stuck at GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 47
    Warning (13410): Pin "x_NIM_OUT" is stuck at GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 206
Info (17049): 667 registers lost all their fanouts during netlist optimizations.
Info (17016): Found the following redundant logic cells in design
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0|combout" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll_dps_lcell_comb.v Line: 106
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1|combout" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll_dps_lcell_comb.v Line: 106
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2|combout" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll_dps_lcell_comb.v Line: 106
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3|combout" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll_dps_lcell_comb.v Line: 106
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4|combout" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll_dps_lcell_comb.v Line: 106
    Info (17048): Logic cell "sl_int_sct_tx_clk[0]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 260
    Info (17048): Logic cell "sl_int_sct_tx_clk[1]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 260
    Info (17048): Logic cell "sl_int_sel_clk" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 248
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[0]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[1]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[2]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[3]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[4]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[5]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[6]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[7]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[8]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[9]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[10]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[11]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[12]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[13]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[14]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[15]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|cntsel_temp[0]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 424
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|cntsel_temp[1]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 424
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|cntsel_temp[2]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 424
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|cntsel_temp[3]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 424
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|cntsel_temp[4]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 424
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|gnd" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 426
    Info (17048): Logic cell "sl_int_sct_rx_clk[0]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 261
    Info (17048): Logic cell "sl_int_sct_rx_clk[1]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 261
Info (144001): Generated suppressed messages file J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/output_files/FTR_TOP.map.smsg
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 156 node(s), including 43 DDIO, 2 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 43 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "x_ETH_PHY_INTn" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 59
    Warning (15610): No output dependent on input pin "x_5A_TXP1" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 136
    Warning (15610): No output dependent on input pin "x_5A_TXN1" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 137
    Warning (15610): No output dependent on input pin "x_5A_RXP6" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 138
    Warning (15610): No output dependent on input pin "x_5A_RXN6" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 139
    Warning (15610): No output dependent on input pin "x_5A_RXP8" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 140
    Warning (15610): No output dependent on input pin "x_5A_RXN8" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 141
    Warning (15610): No output dependent on input pin "x_5A_RXP4" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 142
    Warning (15610): No output dependent on input pin "x_5A_RXN4" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 143
    Warning (15610): No output dependent on input pin "x_5A_TXP7" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 144
    Warning (15610): No output dependent on input pin "x_5A_TXN7" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 145
    Warning (15610): No output dependent on input pin "x_5A_RXN2" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 146
    Warning (15610): No output dependent on input pin "x_7A_RXN1" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 149
    Warning (15610): No output dependent on input pin "x_7A_RXP1" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 150
    Warning (15610): No output dependent on input pin "x_7A_RXP5" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 151
    Warning (15610): No output dependent on input pin "x_7A_RXN5" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 152
    Warning (15610): No output dependent on input pin "x_7A_TXP8" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 153
    Warning (15610): No output dependent on input pin "x_7A_TXN8" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 154
    Warning (15610): No output dependent on input pin "x_7A_RXP9" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 155
    Warning (15610): No output dependent on input pin "x_7A_TXP2" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 158
    Warning (15610): No output dependent on input pin "x_7A_TXN2" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 159
    Warning (15610): No output dependent on input pin "x_7A_RXP3" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 160
    Warning (15610): No output dependent on input pin "x_7A_RXN3" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 161
    Warning (15610): No output dependent on input pin "x_7A_TXP4" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 162
    Warning (15610): No output dependent on input pin "x_7A_TXN4" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 163
    Warning (15610): No output dependent on input pin "x_7A_TXP6" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 164
    Warning (15610): No output dependent on input pin "x_7A_TXN6" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 165
    Warning (15610): No output dependent on input pin "x_7A_TXP10" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 168
    Warning (15610): No output dependent on input pin "x_7A_TXN10" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 169
    Warning (15610): No output dependent on input pin "x_7A_RXP11" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 170
    Warning (15610): No output dependent on input pin "x_7A_RXN11" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 171
    Warning (15610): No output dependent on input pin "x_7A_TXP12" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 172
    Warning (15610): No output dependent on input pin "x_7A_TXN12" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 173
    Warning (15610): No output dependent on input pin "x_7A_RXP33" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 185
    Warning (15610): No output dependent on input pin "x_7A_RXN33" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 186
    Warning (15610): No output dependent on input pin "x_8A_TXP54" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 193
    Warning (15610): No output dependent on input pin "x_8A_TXN54" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 194
    Warning (15610): No output dependent on input pin "x_8A_TXP56" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 195
    Warning (15610): No output dependent on input pin "x_8A_RXP55" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 200
    Warning (15610): No output dependent on input pin "x_8A_RXN55" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 201
    Warning (15610): No output dependent on input pin "x_8A_TXN56" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 202
    Warning (15610): No output dependent on input pin "x_NIM_IN[0]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 207
    Warning (15610): No output dependent on input pin "x_NIM_IN[1]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/src/FTR_TOP.vhd Line: 207
Info (21057): Implemented 17846 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 77 input pins
    Info (21059): Implemented 89 output pins
    Info (21060): Implemented 33 bidirectional pins
    Info (21061): Implemented 16171 logic cells
    Info (21064): Implemented 1422 RAM segments
    Info (21065): Implemented 2 PLLs
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 596 warnings
    Info: Peak virtual memory: 5433 megabytes
    Info: Processing ended: Mon Nov 30 09:47:21 2020
    Info: Elapsed time: 00:02:19
    Info: Total CPU time (on all processors): 00:02:53


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/ETH_TOP/output_files/FTR_TOP.map.smsg.


